| /external/llvm/include/llvm/ |
| Instruction.h | 102 return Opcode >= Shl && Opcode <= AShr;
113 return getOpcode() == AShr;
|
| Operator.h | 152 OpC == Instruction::AShr ||
238 : public ConcreteOperator<PossiblyExactOperator, Instruction::AShr> {
|
| InstrTypes.h | 278 DEFINE_HELPERS(AShr, Exact) // CreateExactAShr
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineShifts.cpp | 319 if (I.getOpcode() != Instruction::AShr &&
337 if (I.getOpcode() != Instruction::AShr)
339 // ashr i32 X, 32 --> ashr i32 X, 31
362 // If 'shift2' is an ashr, we would have to get the sign bit into a funny
509 if (isValid && I.getOpcode() == Instruction::AShr)
544 // If this is oversized composite shift, then unsigned shifts get 0, ashr
547 if (I.getOpcode() != Instruction::AShr)
549 AmtSum = TypeBits-1; // Saturate to 31 for i32 ashr.
578 ShiftOp->getOpcode() == Instruction::AShr);
[all...] |
| InstCombineSelect.cpp | 95 case Instruction::AShr:
113 case Instruction::AShr:
467 Value *AShr = Builder->CreateAShr(CmpLHS, Ty->getBitWidth()-1);
471 return ReplaceInstUsesWith(SI, Builder->CreateOr(AShr, C1));
473 Value *And = Builder->CreateAnd(AShr, C2->getValue()-C1->getValue());
[all...] |
| InstCombineCompares.cpp | [all...] |
| InstCombineSimplifyDemanded.cpp | 630 case Instruction::AShr:
642 // If the sign bit is the only bit demanded by this ashr, then there is no
[all...] |
| InstCombineAndOrXor.cpp | 246 case Instruction::AShr:
257 // (Val ashr C1) & C2 -> (Val lshr C1) & C2
[all...] |
| InstCombineCasts.cpp | 175 case Instruction::AShr:
[all...] |
| /external/llvm/include/llvm/Support/ |
| PatternMatch.h | 415 inline BinaryOp_match<LHS, RHS, Instruction::AShr>
417 return BinaryOp_match<LHS, RHS, Instruction::AShr>(L, R);
444 /// m_Shr - Matches LShr or AShr.
446 inline BinOp2_match<LHS, RHS, Instruction::LShr, Instruction::AShr>
448 return BinOp2_match<LHS, RHS, Instruction::LShr, Instruction::AShr>(L, R);
|
| /external/mesa3d/include/pixelflinger2/ |
| pixelflinger2_vector4.h | 83 void AShr(const unsigned shift) { i[0] >>= shift; i[1] >>= shift; i[2] >>= shift; i[3] >>= shift; }
|
| /external/llvm/lib/Transforms/Scalar/ |
| LoopRotation.cpp | 186 case Instruction::AShr:
|
| /external/llvm/lib/VMCore/ |
| Instruction.cpp | 157 case AShr: return "ashr";
|
| ConstantFold.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | [all...] |
| /external/llvm/lib/Target/CppBackend/ |
| CPPBackend.cpp | 879 case Instruction::AShr: Out << "getAShr("; break;
[all...] |
| /external/llvm/lib/Analysis/ |
| ValueTracking.cpp | 500 case Instruction::AShr:
501 // (ashr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0
[all...] |
| InstructionSimplify.cpp | [all...] |
| /external/llvm/lib/AsmParser/ |
| LLLexer.cpp | 600 INSTKEYWORD(shl, Shl); INSTKEYWORD(lshr, LShr); INSTKEYWORD(ashr, AShr);
|
| /external/llvm/tools/llvm-stress/ |
| llvm-stress.cpp | 339 case 9: {Op = Instruction::AShr; break; }
|
| /external/llvm/lib/Bitcode/Reader/ |
| BitcodeReader.cpp | 135 case bitc::BINOP_ASHR: return Instruction::AShr;
[all...] |
| /frameworks/compile/libbcc/bcinfo/BitReader_2_7/ |
| BitcodeReader.cpp | 192 case bitc::BINOP_ASHR: return Instruction::AShr;
[all...] |
| /frameworks/compile/libbcc/bcinfo/BitReader_3_0/ |
| BitcodeReader.cpp | 433 case bitc::BINOP_ASHR: return Instruction::AShr;
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FastISel.cpp | [all...] |
| /external/llvm/lib/ExecutionEngine/Interpreter/ |
| Execution.cpp | [all...] |
