| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 119 MachineBasicBlock* EmitInstrWithCustomInserter(MachineInstr *MI,
121 MachineBasicBlock* EmitShiftInstr(MachineInstr *MI,
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| MSP430FrameLowering.cpp | 97 MachineInstr *MI =
159 MachineInstr *MI =
169 MachineInstr *MI =
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| /external/llvm/lib/Target/PowerPC/ |
| PPCHazardRecognizers.cpp | 140 MachineInstr *MI = SU->getInstr();
198 MachineInstr *MI = SU->getInstr();
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| PPCInstrInfo.cpp | 78 unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
96 unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
116 MachineInstr *
117 PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
207 MachineInstr *LastInst = I;
230 MachineInstr *SecondLastInst = I;
355 SmallVectorImpl<MachineInstr*> &NewMIs) const{
501 SmallVector<MachineInstr*, 4> NewMIs;
524 SmallVectorImpl<MachineInstr*> &NewMIs)const{
636 SmallVector<MachineInstr*, 4> NewMIs
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcRegisterInfo.cpp | 62 MachineInstr &MI = *I;
78 MachineInstr &MI = *II;
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| SparcISelLowering.h | 59 EmitInstrWithCustomInserter(MachineInstr *MI,
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| /external/llvm/lib/Target/X86/ |
| X86VZeroUpper.cpp | 124 static bool hasYmmReg(MachineInstr *MI) {
221 MachineInstr *MI = I;
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| X86FrameLowering.cpp | 174 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
177 MI->setFlag(MachineInstr::FrameSetup);
183 MachineInstr *MI = NULL;
196 MI->setFlag(MachineInstr::FrameSetup);
525 MachineInstr &MI = *MBBI;
528 if (!MI.getFlag(MachineInstr::FrameSetup)) break;
692 MachineInstr *MI =
698 .setMIFlag(MachineInstr::FrameSetup);
737 .setMIFlag(MachineInstr::FrameSetup);
766 .setMIFlag(MachineInstr::FrameSetup)
[all...] |
| X86InstrInfo.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| RegisterScavenging.h | 56 const MachineInstr *ScavengeRestore;
|
| MachineOperand.h | 27 class MachineInstr;
118 /// by the MachineInstr before all input registers are read. This is used to
137 MachineInstr *ParentMI;
184 MachineInstr *getParent() { return ParentMI; }
185 const MachineInstr *getParent() const { return ParentMI; }
191 /// MachineInstr, the parent pointer must be cleared.
193 /// Never call clearParent() on an operand in a MachineInstr.
642 friend class MachineInstr;
|
| ScheduleDAG.h | 12 // which is shared between SelectionDAG and MachineInstr scheduling.
33 class MachineInstr;
231 MachineInstr *Instr; // Alternatively, a MachineInstr.
293 /// a MachineInstr.
294 SUnit(MachineInstr *instr, unsigned nodenum)
322 assert(!Instr && "Setting SDNode of SUnit with MachineInstr!");
329 assert(!Instr && "Reading SDNode of SUnit with MachineInstr!");
339 void setInstr(MachineInstr *MI) {
340 assert(!Node && "Setting MachineInstr of SUnit with SDNode!")
[all...] |
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| AsmPrinterInlineAsm.cpp | 143 void AsmPrinter::EmitInlineAsm(const MachineInstr *MI) const {
386 void AsmPrinter::PrintSpecial(const MachineInstr *MI, raw_ostream &OS,
415 bool AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
422 bool AsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
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| /external/llvm/lib/Target/Hexagon/ |
| HexagonMCInstLower.cpp | 1 //===- HexagonMCInstLower.cpp - Convert Hexagon MachineInstr to an MCInst -===//
40 // Create an MCInst from a MachineInstr
41 void llvm::HexagonLowerToMC(const MachineInstr* MI, MCInst& MCI,
|
| HexagonInstrInfo.cpp | 68 unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
98 unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
148 MachineInstr *Term = MBB.getFirstTerminator();
216 MachineInstr *LastInst = I;
242 MachineInstr *SecondLastInst = I;
396 SmallVectorImpl<MachineInstr*> &NewMIs) const
437 SmallVectorImpl<MachineInstr*> &NewMIs) const {
442 MachineInstr *HexagonInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
443 MachineInstr* MI,
471 bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const
[all...] |
| HexagonFrameLowering.cpp | 102 const std::vector<MachineInstr*>& AdjustRegs =
104 for (std::vector<MachineInstr*>::const_iterator i = AdjustRegs.begin(),
107 MachineInstr* MI = *i;
|
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeInstrInfo.cpp | 44 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const {
63 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const {
134 MachineInstr *LastInst = I;
155 MachineInstr *SecondLastInst = I;
|
| /external/llvm/lib/CodeGen/ |
| LocalStackSlotAllocation.cpp | 201 const MachineInstr *MI,
241 MachineInstr *MI = I;
278 MachineInstr *MI = I;
|
| CriticalAntiDepBreaker.cpp | 128 void CriticalAntiDepBreaker::Observe(MachineInstr *MI, unsigned Count,
180 void CriticalAntiDepBreaker::PrescanInstruction(MachineInstr *MI) {
247 void CriticalAntiDepBreaker::ScanInstruction(MachineInstr *MI,
367 MachineInstr *MI = RefOper->getParent();
444 // Keep a map of the MachineInstr*'s back to the SUnit representing them.
448 DenseMap<MachineInstr*,const SUnit*> MISUnitMap;
475 MachineInstr *CriticalPathMI = CriticalPathSU->getInstr();
527 MachineInstr *MI = --I;
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| MachineVerifier.cpp | 75 typedef DenseMap<unsigned, const MachineInstr*> RegMap;
77 const MachineInstr *FirstTerminator;
194 void visitMachineInstrBefore(const MachineInstr *MI);
196 void visitMachineInstrAfter(const MachineInstr *MI);
202 void report(const char *msg, const MachineInstr *MI);
352 void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
578 void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
587 for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
629 const MachineInstr *MI = MO->getParent();
757 const MachineInstr *MI = MO->getParent()
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGSDNodes.cpp | 658 bool operator()(const std::pair<unsigned, MachineInstr*> &A,
659 const std::pair<unsigned, MachineInstr*> &B) {
668 SmallVector<std::pair<unsigned, MachineInstr*>, 32> &Orders,
684 MachineInstr *DbgMI = Emitter.EmitDbgValue(DVs[i], VRBaseMap);
700 SmallVector<std::pair<unsigned, MachineInstr*>, 32> &Orders,
713 Orders.push_back(std::make_pair(Order, (MachineInstr*)0));
766 SmallVector<std::pair<unsigned, MachineInstr*>, 32> Orders;
775 MachineInstr *DbgMI= Emitter.EmitDbgValue(*PDI, VRBaseMap);
833 MachineInstr *MI = Orders[i].second;
841 MachineInstr *DbgMI = Emitter.EmitDbgValue(*DI, VRBaseMap)
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsInstrInfo.cpp | 49 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
74 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
235 MachineInstr*
281 static void AnalyzeCondBr(const MachineInstr* Inst, unsigned Opc,
315 MachineInstr *LastInst = &*I;
324 MachineInstr *SecondLastInst = NULL;
|
| /external/llvm/include/llvm/Target/ |
| TargetRegisterInfo.h | 621 virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
630 virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
652 virtual bool isFrameOffsetLegal(const MachineInstr *MI,
|
| /external/llvm/lib/Target/PTX/ |
| PTXFPRoundingModePass.cpp | 61 void processInstruction(MachineInstr &MI);
77 MachineInstr &MI = *ii;
164 void PTXFPRoundingModePass::processInstruction(MachineInstr &MI) {
|
| /external/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.cpp | 109 MachineInstr *Old = I;
131 MachineInstr *New;
155 MachineInstr &MI = *II;
|
