1 //===-- PPCHazardRecognizers.cpp - PowerPC Hazard Recognizer Impls --------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements hazard recognizers for scheduling on PowerPC processors. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #define DEBUG_TYPE "pre-RA-sched" 15 #include "PPCHazardRecognizers.h" 16 #include "PPC.h" 17 #include "PPCInstrInfo.h" 18 #include "llvm/CodeGen/ScheduleDAG.h" 19 #include "llvm/Support/Debug.h" 20 #include "llvm/Support/ErrorHandling.h" 21 #include "llvm/Support/raw_ostream.h" 22 using namespace llvm; 23 24 //===----------------------------------------------------------------------===// 25 // PowerPC Scoreboard Hazard Recognizer 26 void PPCScoreboardHazardRecognizer::EmitInstruction(SUnit *SU) { 27 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); 28 if (!MCID) 29 // This is a PPC pseudo-instruction. 30 return; 31 32 ScoreboardHazardRecognizer::EmitInstruction(SU); 33 } 34 35 ScheduleHazardRecognizer::HazardType 36 PPCScoreboardHazardRecognizer::getHazardType(SUnit *SU, int Stalls) { 37 return ScoreboardHazardRecognizer::getHazardType(SU, Stalls); 38 } 39 40 void PPCScoreboardHazardRecognizer::AdvanceCycle() { 41 ScoreboardHazardRecognizer::AdvanceCycle(); 42 } 43 44 void PPCScoreboardHazardRecognizer::Reset() { 45 ScoreboardHazardRecognizer::Reset(); 46 } 47 48 //===----------------------------------------------------------------------===// 49 // PowerPC 970 Hazard Recognizer 50 // 51 // This models the dispatch group formation of the PPC970 processor. Dispatch 52 // groups are bundles of up to five instructions that can contain various mixes 53 // of instructions. The PPC970 can dispatch a peak of 4 non-branch and one 54 // branch instruction per-cycle. 55 // 56 // There are a number of restrictions to dispatch group formation: some 57 // instructions can only be issued in the first slot of a dispatch group, & some 58 // instructions fill an entire dispatch group. Additionally, only branches can 59 // issue in the 5th (last) slot. 60 // 61 // Finally, there are a number of "structural" hazards on the PPC970. These 62 // conditions cause large performance penalties due to misprediction, recovery, 63 // and replay logic that has to happen. These cases include setting a CTR and 64 // branching through it in the same dispatch group, and storing to an address, 65 // then loading from the same address within a dispatch group. To avoid these 66 // conditions, we insert no-op instructions when appropriate. 67 // 68 // FIXME: This is missing some significant cases: 69 // 1. Modeling of microcoded instructions. 70 // 2. Handling of serialized operations. 71 // 3. Handling of the esoteric cases in "Resource-based Instruction Grouping". 72 // 73 74 PPCHazardRecognizer970::PPCHazardRecognizer970(const TargetInstrInfo &tii) 75 : TII(tii) { 76 EndDispatchGroup(); 77 } 78 79 void PPCHazardRecognizer970::EndDispatchGroup() { 80 DEBUG(errs() << "=== Start of dispatch group\n"); 81 NumIssued = 0; 82 83 // Structural hazard info. 84 HasCTRSet = false; 85 NumStores = 0; 86 } 87 88 89 PPCII::PPC970_Unit 90 PPCHazardRecognizer970::GetInstrType(unsigned Opcode, 91 bool &isFirst, bool &isSingle, 92 bool &isCracked, 93 bool &isLoad, bool &isStore) { 94 const MCInstrDesc &MCID = TII.get(Opcode); 95 96 isLoad = MCID.mayLoad(); 97 isStore = MCID.mayStore(); 98 99 uint64_t TSFlags = MCID.TSFlags; 100 101 isFirst = TSFlags & PPCII::PPC970_First; 102 isSingle = TSFlags & PPCII::PPC970_Single; 103 isCracked = TSFlags & PPCII::PPC970_Cracked; 104 return (PPCII::PPC970_Unit)(TSFlags & PPCII::PPC970_Mask); 105 } 106 107 /// isLoadOfStoredAddress - If we have a load from the previously stored pointer 108 /// as indicated by StorePtr1/StorePtr2/StoreSize, return true. 109 bool PPCHazardRecognizer970:: 110 isLoadOfStoredAddress(uint64_t LoadSize, int64_t LoadOffset, 111 const Value *LoadValue) const { 112 for (unsigned i = 0, e = NumStores; i != e; ++i) { 113 // Handle exact and commuted addresses. 114 if (LoadValue == StoreValue[i] && LoadOffset == StoreOffset[i]) 115 return true; 116 117 // Okay, we don't have an exact match, if this is an indexed offset, see if 118 // we have overlap (which happens during fp->int conversion for example). 119 if (StoreValue[i] == LoadValue) { 120 // Okay the base pointers match, so we have [c1+r] vs [c2+r]. Check 121 // to see if the load and store actually overlap. 122 if (StoreOffset[i] < LoadOffset) { 123 if (int64_t(StoreOffset[i]+StoreSize[i]) > LoadOffset) return true; 124 } else { 125 if (int64_t(LoadOffset+LoadSize) > StoreOffset[i]) return true; 126 } 127 } 128 } 129 return false; 130 } 131 132 /// getHazardType - We return hazard for any non-branch instruction that would 133 /// terminate the dispatch group. We turn NoopHazard for any 134 /// instructions that wouldn't terminate the dispatch group that would cause a 135 /// pipeline flush. 136 ScheduleHazardRecognizer::HazardType PPCHazardRecognizer970:: 137 getHazardType(SUnit *SU, int Stalls) { 138 assert(Stalls == 0 && "PPC hazards don't support scoreboard lookahead"); 139 140 MachineInstr *MI = SU->getInstr(); 141 142 if (MI->isDebugValue()) 143 return NoHazard; 144 145 unsigned Opcode = MI->getOpcode(); 146 bool isFirst, isSingle, isCracked, isLoad, isStore; 147 PPCII::PPC970_Unit InstrType = 148 GetInstrType(Opcode, isFirst, isSingle, isCracked, 149 isLoad, isStore); 150 if (InstrType == PPCII::PPC970_Pseudo) return NoHazard; 151 152 // We can only issue a PPC970_First/PPC970_Single instruction (such as 153 // crand/mtspr/etc) if this is the first cycle of the dispatch group. 154 if (NumIssued != 0 && (isFirst || isSingle)) 155 return Hazard; 156 157 // If this instruction is cracked into two ops by the decoder, we know that 158 // it is not a branch and that it cannot issue if 3 other instructions are 159 // already in the dispatch group. 160 if (isCracked && NumIssued > 2) 161 return Hazard; 162 163 switch (InstrType) { 164 default: llvm_unreachable("Unknown instruction type!"); 165 case PPCII::PPC970_FXU: 166 case PPCII::PPC970_LSU: 167 case PPCII::PPC970_FPU: 168 case PPCII::PPC970_VALU: 169 case PPCII::PPC970_VPERM: 170 // We can only issue a branch as the last instruction in a group. 171 if (NumIssued == 4) return Hazard; 172 break; 173 case PPCII::PPC970_CRU: 174 // We can only issue a CR instruction in the first two slots. 175 if (NumIssued >= 2) return Hazard; 176 break; 177 case PPCII::PPC970_BRU: 178 break; 179 } 180 181 // Do not allow MTCTR and BCTRL to be in the same dispatch group. 182 if (HasCTRSet && (Opcode == PPC::BCTRL_Darwin || Opcode == PPC::BCTRL_SVR4)) 183 return NoopHazard; 184 185 // If this is a load following a store, make sure it's not to the same or 186 // overlapping address. 187 if (isLoad && NumStores && !MI->memoperands_empty()) { 188 MachineMemOperand *MO = *MI->memoperands_begin(); 189 if (isLoadOfStoredAddress(MO->getSize(), 190 MO->getOffset(), MO->getValue())) 191 return NoopHazard; 192 } 193 194 return NoHazard; 195 } 196 197 void PPCHazardRecognizer970::EmitInstruction(SUnit *SU) { 198 MachineInstr *MI = SU->getInstr(); 199 200 if (MI->isDebugValue()) 201 return; 202 203 unsigned Opcode = MI->getOpcode(); 204 bool isFirst, isSingle, isCracked, isLoad, isStore; 205 PPCII::PPC970_Unit InstrType = 206 GetInstrType(Opcode, isFirst, isSingle, isCracked, 207 isLoad, isStore); 208 if (InstrType == PPCII::PPC970_Pseudo) return; 209 210 // Update structural hazard information. 211 if (Opcode == PPC::MTCTR || Opcode == PPC::MTCTR8) HasCTRSet = true; 212 213 // Track the address stored to. 214 if (isStore && NumStores < 4 && !MI->memoperands_empty()) { 215 MachineMemOperand *MO = *MI->memoperands_begin(); 216 StoreSize[NumStores] = MO->getSize(); 217 StoreOffset[NumStores] = MO->getOffset(); 218 StoreValue[NumStores] = MO->getValue(); 219 ++NumStores; 220 } 221 222 if (InstrType == PPCII::PPC970_BRU || isSingle) 223 NumIssued = 4; // Terminate a d-group. 224 ++NumIssued; 225 226 // If this instruction is cracked into two ops by the decoder, remember that 227 // we issued two pieces. 228 if (isCracked) 229 ++NumIssued; 230 231 if (NumIssued == 5) 232 EndDispatchGroup(); 233 } 234 235 void PPCHazardRecognizer970::AdvanceCycle() { 236 assert(NumIssued < 5 && "Illegal dispatch group!"); 237 ++NumIssued; 238 if (NumIssued == 5) 239 EndDispatchGroup(); 240 } 241 242 void PPCHazardRecognizer970::Reset() { 243 EndDispatchGroup(); 244 } 245 246
