| /external/llvm/include/llvm/Transforms/Utils/ |
| AddrModeMatcher.h | 37 Value *BaseReg;
39 ExtAddrMode() : BaseReg(0), ScaledReg(0) {}
44 return (BaseReg == O.BaseReg) && (ScaledReg == O.ScaledReg) &&
|
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86ATTInstPrinter.cpp | 138 const MCOperand &BaseReg = MI->getOperand(Op);
151 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
158 if (IndexReg.getReg() || BaseReg.getReg()) {
160 if (BaseReg.getReg())
|
| X86IntelInstPrinter.cpp | 129 const MCOperand &BaseReg = MI->getOperand(Op);
144 if (BaseReg.getReg()) {
164 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
|
| /external/llvm/lib/CodeGen/ |
| LocalStackSlotAllocation.cpp | 290 unsigned BaseReg = 0;
310 BaseReg = RegOffset.first;
318 BaseReg = Fn.getRegInfo().createVirtualRegister(RC);
320 DEBUG(dbgs() << " Materializing base register " << BaseReg <<
327 TRI->materializeFrameBaseRegister(Entry, BaseReg, FrameIdx,
338 std::pair<unsigned, int64_t>(BaseReg, BaseOffset));
342 assert(BaseReg != 0 && "Unable to allocate virtual base register!");
346 TRI->resolveFrameIndex(I, BaseReg, Offset);
|
| /external/llvm/lib/Target/Mips/ |
| MipsMCInstLower.cpp | 149 MCOperand SPReg = MCOperand::CreateReg(Mips::SP), BaseReg = SPReg;
156 BaseReg = ATReg;
166 CreateMCInst(Sw, Mips::SW, GPReg, BaseReg, MCOperand::CreateImm(Offset));
|
| /external/llvm/lib/Target/X86/ |
| X86AsmPrinter.cpp | 306 const MachineOperand &BaseReg = MI->getOperand(Op);
311 bool HasBaseReg = BaseReg.getReg() != 0;
313 BaseReg.getReg() == X86::RIP)
|
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCCodeEmitter.cpp | 165 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
168 if ((BaseReg.getReg() != 0 &&
169 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) ||
180 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
183 if ((BaseReg.getReg() != 0 &&
184 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) ||
195 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
198 if ((BaseReg.getReg() != 0 &&
199 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) ||
305 unsigned BaseReg = Base.getReg()
[all...] |
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 171 unsigned BaseReg = MI->getOperand(0).getReg();
173 if (MI->getOperand(i).getReg() == BaseReg)
180 O << '\t' << getRegisterName(BaseReg);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb2SizeReduction.cpp | 126 // ARM::t2STM (with no basereg writeback) has no Thumb1 equivalent
379 unsigned BaseReg = MI->getOperand(0).getReg();
380 if (!isARMLowRegister(BaseReg) || Entry.WideOpc != ARM::t2LDMIA)
387 if (MI->getOperand(i).getReg() == BaseReg) {
401 unsigned BaseReg = MI->getOperand(1).getReg();
402 if (BaseReg != ARM::SP)
415 unsigned BaseReg = MI->getOperand(1).getReg();
416 if (BaseReg == ARM::SP &&
421 } else if (!isARMLowRegister(BaseReg) ||
[all...] |
| ARMBaseInstrInfo.cpp | 154 unsigned BaseReg = Base.getReg();
170 .addReg(BaseReg).addImm(Amt)
177 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
182 .addReg(BaseReg).addReg(OffReg)
193 .addReg(BaseReg).addImm(Amt)
198 .addReg(BaseReg).addReg(OffReg)
220 .addReg(BaseReg).addImm(0).addImm(Pred);
224 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
[all...] |
| ARMConstantIslandPass.cpp | [all...] |
| ARMLoadStoreOptimizer.cpp | [all...] |
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmParser.cpp | 176 unsigned BaseReg;
225 return Mem.BaseReg;
425 Res->Mem.BaseReg = 0;
434 unsigned BaseReg, unsigned IndexReg,
439 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
447 Res->Mem.BaseReg = BaseReg;
458 unsigned basereg = is64BitMode() ? X86::RSI : X86::ESI; local
464 Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0)
468 unsigned basereg = is64BitMode() ? X86::RDI : X86::EDI; local
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| LoopStrengthReduce.cpp | 906 const SCEV *BaseReg = *I;
907 if (VisitedRegs.count(BaseReg)) {
911 RatePrimaryRegister(BaseReg, Regs, L, SE, DT, LoserRegs);
[all...] |
