1 //===---- LiveRangeEdit.h - Basic tools for split and spill -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // The LiveRangeEdit class represents changes done to a virtual register when it 11 // is spilled or split. 12 // 13 // The parent register is never changed. Instead, a number of new virtual 14 // registers are created and added to the newRegs vector. 15 // 16 //===----------------------------------------------------------------------===// 17 18 #ifndef LLVM_CODEGEN_LIVERANGEEDIT_H 19 #define LLVM_CODEGEN_LIVERANGEEDIT_H 20 21 #include "llvm/ADT/ArrayRef.h" 22 #include "llvm/ADT/SmallPtrSet.h" 23 #include "llvm/CodeGen/LiveInterval.h" 24 #include "llvm/Target/TargetMachine.h" 25 26 namespace llvm { 27 28 class AliasAnalysis; 29 class LiveIntervals; 30 class MachineLoopInfo; 31 class MachineRegisterInfo; 32 class VirtRegMap; 33 34 class LiveRangeEdit { 35 public: 36 /// Callback methods for LiveRangeEdit owners. 37 class Delegate { 38 virtual void anchor(); 39 public: 40 /// Called immediately before erasing a dead machine instruction. 41 virtual void LRE_WillEraseInstruction(MachineInstr *MI) {} 42 43 /// Called when a virtual register is no longer used. Return false to defer 44 /// its deletion from LiveIntervals. 45 virtual bool LRE_CanEraseVirtReg(unsigned) { return true; } 46 47 /// Called before shrinking the live range of a virtual register. 48 virtual void LRE_WillShrinkVirtReg(unsigned) {} 49 50 /// Called after cloning a virtual register. 51 /// This is used for new registers representing connected components of Old. 52 virtual void LRE_DidCloneVirtReg(unsigned New, unsigned Old) {} 53 54 virtual ~Delegate() {} 55 }; 56 57 private: 58 LiveInterval &parent_; 59 SmallVectorImpl<LiveInterval*> &newRegs_; 60 MachineRegisterInfo &MRI; 61 LiveIntervals &LIS; 62 VirtRegMap *VRM; 63 const TargetInstrInfo &TII; 64 Delegate *const delegate_; 65 66 /// firstNew_ - Index of the first register added to newRegs_. 67 const unsigned firstNew_; 68 69 /// scannedRemattable_ - true when remattable values have been identified. 70 bool scannedRemattable_; 71 72 /// remattable_ - Values defined by remattable instructions as identified by 73 /// tii.isTriviallyReMaterializable(). 74 SmallPtrSet<const VNInfo*,4> remattable_; 75 76 /// rematted_ - Values that were actually rematted, and so need to have their 77 /// live range trimmed or entirely removed. 78 SmallPtrSet<const VNInfo*,4> rematted_; 79 80 /// scanRemattable - Identify the parent_ values that may rematerialize. 81 void scanRemattable(AliasAnalysis *aa); 82 83 /// allUsesAvailableAt - Return true if all registers used by OrigMI at 84 /// OrigIdx are also available with the same value at UseIdx. 85 bool allUsesAvailableAt(const MachineInstr *OrigMI, SlotIndex OrigIdx, 86 SlotIndex UseIdx); 87 88 /// foldAsLoad - If LI has a single use and a single def that can be folded as 89 /// a load, eliminate the register by folding the def into the use. 90 bool foldAsLoad(LiveInterval *LI, SmallVectorImpl<MachineInstr*> &Dead); 91 92 public: 93 /// Create a LiveRangeEdit for breaking down parent into smaller pieces. 94 /// @param parent The register being spilled or split. 95 /// @param newRegs List to receive any new registers created. This needn't be 96 /// empty initially, any existing registers are ignored. 97 /// @param MF The MachineFunction the live range edit is taking place in. 98 /// @param lis The collection of all live intervals in this function. 99 /// @param vrm Map of virtual registers to physical registers for this 100 /// function. If NULL, no virtual register map updates will 101 /// be done. This could be the case if called before Regalloc. 102 LiveRangeEdit(LiveInterval &parent, 103 SmallVectorImpl<LiveInterval*> &newRegs, 104 MachineFunction &MF, 105 LiveIntervals &lis, 106 VirtRegMap *vrm, 107 Delegate *delegate = 0) 108 : parent_(parent), newRegs_(newRegs), 109 MRI(MF.getRegInfo()), LIS(lis), VRM(vrm), 110 TII(*MF.getTarget().getInstrInfo()), 111 delegate_(delegate), 112 firstNew_(newRegs.size()), 113 scannedRemattable_(false) {} 114 115 LiveInterval &getParent() const { return parent_; } 116 unsigned getReg() const { return parent_.reg; } 117 118 /// Iterator for accessing the new registers added by this edit. 119 typedef SmallVectorImpl<LiveInterval*>::const_iterator iterator; 120 iterator begin() const { return newRegs_.begin()+firstNew_; } 121 iterator end() const { return newRegs_.end(); } 122 unsigned size() const { return newRegs_.size()-firstNew_; } 123 bool empty() const { return size() == 0; } 124 LiveInterval *get(unsigned idx) const { return newRegs_[idx+firstNew_]; } 125 126 ArrayRef<LiveInterval*> regs() const { 127 return makeArrayRef(newRegs_).slice(firstNew_); 128 } 129 130 /// createFrom - Create a new virtual register based on OldReg. 131 LiveInterval &createFrom(unsigned OldReg); 132 133 /// create - Create a new register with the same class and original slot as 134 /// parent. 135 LiveInterval &create() { 136 return createFrom(getReg()); 137 } 138 139 /// anyRematerializable - Return true if any parent values may be 140 /// rematerializable. 141 /// This function must be called before any rematerialization is attempted. 142 bool anyRematerializable(AliasAnalysis*); 143 144 /// checkRematerializable - Manually add VNI to the list of rematerializable 145 /// values if DefMI may be rematerializable. 146 bool checkRematerializable(VNInfo *VNI, const MachineInstr *DefMI, 147 AliasAnalysis*); 148 149 /// Remat - Information needed to rematerialize at a specific location. 150 struct Remat { 151 VNInfo *ParentVNI; // parent_'s value at the remat location. 152 MachineInstr *OrigMI; // Instruction defining ParentVNI. 153 explicit Remat(VNInfo *ParentVNI) : ParentVNI(ParentVNI), OrigMI(0) {} 154 }; 155 156 /// canRematerializeAt - Determine if ParentVNI can be rematerialized at 157 /// UseIdx. It is assumed that parent_.getVNINfoAt(UseIdx) == ParentVNI. 158 /// When cheapAsAMove is set, only cheap remats are allowed. 159 bool canRematerializeAt(Remat &RM, 160 SlotIndex UseIdx, 161 bool cheapAsAMove); 162 163 /// rematerializeAt - Rematerialize RM.ParentVNI into DestReg by inserting an 164 /// instruction into MBB before MI. The new instruction is mapped, but 165 /// liveness is not updated. 166 /// Return the SlotIndex of the new instruction. 167 SlotIndex rematerializeAt(MachineBasicBlock &MBB, 168 MachineBasicBlock::iterator MI, 169 unsigned DestReg, 170 const Remat &RM, 171 const TargetRegisterInfo&, 172 bool Late = false); 173 174 /// markRematerialized - explicitly mark a value as rematerialized after doing 175 /// it manually. 176 void markRematerialized(const VNInfo *ParentVNI) { 177 rematted_.insert(ParentVNI); 178 } 179 180 /// didRematerialize - Return true if ParentVNI was rematerialized anywhere. 181 bool didRematerialize(const VNInfo *ParentVNI) const { 182 return rematted_.count(ParentVNI); 183 } 184 185 /// eraseVirtReg - Notify the delegate that Reg is no longer in use, and try 186 /// to erase it from LIS. 187 void eraseVirtReg(unsigned Reg); 188 189 /// eliminateDeadDefs - Try to delete machine instructions that are now dead 190 /// (allDefsAreDead returns true). This may cause live intervals to be trimmed 191 /// and further dead efs to be eliminated. 192 /// RegsBeingSpilled lists registers currently being spilled by the register 193 /// allocator. These registers should not be split into new intervals 194 /// as currently those new intervals are not guaranteed to spill. 195 void eliminateDeadDefs(SmallVectorImpl<MachineInstr*> &Dead, 196 ArrayRef<unsigned> RegsBeingSpilled 197 = ArrayRef<unsigned>()); 198 199 /// calculateRegClassAndHint - Recompute register class and hint for each new 200 /// register. 201 void calculateRegClassAndHint(MachineFunction&, 202 const MachineLoopInfo&); 203 }; 204 205 } 206 207 #endif 208
