| /external/llvm/include/llvm/CodeGen/ |
| CalcSpillWeights.h | 44 LiveIntervals &LIS;
48 VirtRegAuxInfo(MachineFunction &mf, LiveIntervals &lis,
50 MF(mf), LIS(lis), Loops(loops) {}
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| MachineScheduler.h | 48 LiveIntervals *LIS;
50 MachineSchedContext(): MF(0), MLI(0), MDT(0), PassConfig(0), AA(0), LIS(0) {}
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| LiveRangeEdit.h | 61 LiveIntervals &LIS;
98 /// @param lis The collection of all live intervals in this function.
105 LiveIntervals &lis,
109 MRI(MF.getRegInfo()), LIS(lis), VRM(vrm),
186 /// to erase it from LIS.
|
| ScheduleDAGInstrs.h | 175 LiveIntervals *LIS;
245 LiveIntervals *LIS = 0);
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| LiveInterval.h | 289 void RenumberValues(LiveIntervals &lis);
540 /// // allocate numComps-1 new LiveIntervals into LIS[1..]
541 /// ConEQ.Distribute(LIS);
545 LiveIntervals &LIS;
554 explicit ConnectedVNInfoEqClasses(LiveIntervals &lis) : LIS(lis) {}
|
| /external/llvm/lib/CodeGen/ |
| RegisterCoalescer.cpp | 87 LiveIntervals *LIS;
409 if (!LIS->hasInterval(CP.getDstReg()))
413 LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
415 LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
416 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot();
438 MachineInstr *ACopyMI = LIS->getInstructionFromIndex(AValNo->def);
451 LIS->getInstructionFromIndex(ValLR->end.getPrevSlot());
465 if (LIS->hasInterval(*AS) && IntA.overlaps(LIS->getInterval(*AS))) {
468 LIS->getInterval(*AS).print(dbgs(), TRI)
[all...] |
| LiveRangeEdit.cpp | 40 LiveInterval &LI = LIS.getOrCreateInterval(VReg);
62 MachineInstr *DefMI = LIS.getInstructionFromIndex(VNI->def);
88 if (MO.isUndef() || !LIS.hasInterval(MO.getReg()))
91 LiveInterval &li = LIS.getInterval(MO.getReg());
113 DefIdx = LIS.getInstructionIndex(RM.OrigMI);
116 RM.OrigMI = LIS.getInstructionFromIndex(DefIdx);
140 return LIS.getSlotIndexes()->insertMachineInstrInMaps(--MI, Late)
146 LIS.removeInterval(Reg);
187 LIS.ReplaceMachineInstrInMaps(UseMI, FoldMI);
206 SlotIndex Idx = LIS.getInstructionIndex(MI).getRegSlot()
[all...] |
| LiveDebugVariables.cpp | 129 LiveIntervals &LIS, const TargetInstrInfo &TII);
223 /// @param LIS Live intervals analysis.
228 LiveIntervals &LIS, MachineDominatorTree &MDT,
242 LiveIntervals &LIS);
247 LiveIntervals &LIS, MachineDominatorTree &MDT,
264 LiveIntervals &LIS, const TargetInstrInfo &TRI);
284 LiveIntervals *LIS;
470 LIS->getMBBStartIdx(MBB) :
471 LIS->getInstructionIndex(llvm::prior(MBBI)).getRegSlot();
488 LiveIntervals &LIS, MachineDominatorTree &MDT
[all...] |
| InlineSpiller.cpp | 57 LiveIntervals &LIS;
142 LIS(pass.getAnalysis<LiveIntervals>()),
234 if (SnipLI.getNumValNums() > 2 || !LIS.intervalIsInOneMBB(SnipLI))
284 LiveInterval &SnipLI = LIS.getInterval(SnipReg);
370 SV.SpillMBB = LIS.getMBBFromIndex(SV.SpillVNI->def);
388 DepSV.SpillMBB = LIS.getMBBFromIndex(DepSV.SpillVNI->def);
528 LiveInterval &LI = LIS.getInterval(Reg);
529 LiveInterval &OrigLI = LIS.getInterval(Original);
574 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);
580 LiveInterval &SrcLI = LIS.getInterval(SrcReg)
[all...] |
| RegAllocBase.h | 95 LiveIntervals *LIS;
98 RegAllocBase(): UserTag(0), TRI(0), MRI(0), VRM(0), LIS(0) {}
103 void init(VirtRegMap &vrm, LiveIntervals &lis);
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| SplitKit.cpp | 43 const LiveIntervals &lis,
47 LIS(lis),
65 SlotIndex MBBEnd = LIS.getMBBEndIdx(MBB);
74 LSP.first = LIS.getInstructionIndex(FirstTerm);
85 LSP.second = LIS.getInstructionIndex(I);
93 if (!LPad || !LSP.second || !LIS.isLiveInToMBB(*CurLI, LPad))
116 if (LSP == LIS.getMBBEndIdx(MBB))
118 return LIS.getInstructionFromIndex(LSP);
138 UseSlots.push_back(LIS.getInstructionIndex(&*I).getRegSlot())
[all...] |
| InterferenceCache.h | 56 /// LIS - Used for accessing register mask interference maps.
57 LiveIntervals *LIS;
78 Entry() : PhysReg(0), Tag(0), RefCount(0), Indexes(0), LIS(0) {}
80 void clear(MachineFunction *mf, SlotIndexes *indexes, LiveIntervals *lis) {
85 LIS = lis;
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| CalcSpillWeights.cpp | 48 LiveIntervals &lis = getAnalysis<LiveIntervals>(); local
49 VirtRegAuxInfo vrai(fn, lis, getAnalysis<MachineLoopInfo>());
50 for (LiveIntervals::iterator I = lis.begin(), E = lis.end(); I != E; ++I) {
132 if (writes && isExiting && LIS.isLiveOutOfMBB(li, mbb))
146 if (hweight > bestPhys && LIS.isAllocatable(hint))
168 if (li.isZeroLength(LIS.getSlotIndexes())) {
179 if (LIS.isReMaterializable(li, 0, isLoad)) {
|
| RegAllocBase.cpp | 69 for (LiveIntervals::iterator liItr = LIS->begin(), liEnd = LIS->end();
99 void RegAllocBase::init(VirtRegMap &vrm, LiveIntervals &lis) {
104 LIS = &lis;
136 for (LiveIntervals::iterator I = LIS->begin(), E = LIS->end(); I != E; ++I) {
177 LIS->removeInterval(VirtReg->reg);
222 LIS->removeInterval(SplitVirtReg->reg);
248 SlotIndexes *Indexes = LIS->getSlotIndexes()
[all...] |
| RegAllocBasic.cpp | 190 LiveRangeEdit LRE(SpilledVReg, SplitVRegs, *MF, *LIS, VRM);
240 bool CrossRegMasks = LIS->checkRegMaskInterference(VirtReg, UsableRegs);
290 LiveRangeEdit LRE(VirtReg, SplitVRegs, *MF, *LIS, VRM);
340 VRM->rewrite(LIS->getSlotIndexes());
|
| SplitKit.h | 45 const LiveIntervals &LIS;
119 SplitAnalysis(const VirtRegMap &vrm, const LiveIntervals &lis,
212 LiveIntervals &LIS;
|
| LiveIntervalAnalysis.cpp | [all...] |
| MachineScheduler.cpp | 149 LIS = &getAnalysis<LiveIntervals>();
231 DEBUG(LIS->print(dbgs()));
295 ScheduleDAGInstrs(*C->MF, *C->MLI, *C->MDT, /*IsPostRA=*/false, C->LIS),
378 LIS->handleMove(MI);
|
| InterferenceCache.cpp | 28 LiveIntervals *lis,
35 Entries[i].clear(mf, indexes, lis);
145 RegMaskSlots = LIS->getRegMaskSlotsInBlock(MBBNum);
146 RegMaskBits = LIS->getRegMaskBitsInBlock(MBBNum);
|
| RegAllocGreedy.cpp | 364 unassign(LIS->getInterval(VirtReg), PhysReg);
378 LiveInterval &LI = LIS->getInterval(VirtReg);
437 LiveInterval *LI = &LIS->getInterval(~Queue.top().second);
[all...] |
| ScheduleDAGInstrs.cpp | 39 LiveIntervals *lis)
41 InstrItins(mf.getTarget().getInstrItineraryData()), LIS(lis),
44 assert((IsPostRA || LIS) && "PreRA scheduling requires LiveIntervals");
438 assert(LIS && "vreg dependencies requires LiveIntervals");
439 SlotIndex UseIdx = LIS->getInstructionIndex(MI).getRegSlot();
440 LiveInterval *LI = &LIS->getInterval(Reg);
443 MachineInstr *Def = LIS->getInstructionFromIndex(VNI->def);
[all...] |
| LiveInterval.cpp | 149 void LiveInterval::RenumberValues(LiveIntervals &lis) {
679 const MachineBasicBlock *MBB = LIS.getMBBFromIndex(VNI->def);
684 if (const VNInfo *PVNI = LI->getVNInfoBefore(LIS.getMBBEndIdx(*PI)))
718 SlotIndex Idx = LIS.getInstructionIndex(MI);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 212 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS;
577 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SReg)
|
| PPCFrameLowering.cpp | 379 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0)
590 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0)
669 unsigned LISInstr = isPPC64 ? PPC::LIS8 : PPC::LIS;
[all...] |
| PPCISelLowering.cpp | [all...] |
