1 //==- ScheduleDAGInstrs.h - MachineInstr Scheduling --------------*- C++ -*-==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the ScheduleDAGInstrs class, which implements 11 // scheduling for a MachineInstr-based dependency graph. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef SCHEDULEDAGINSTRS_H 16 #define SCHEDULEDAGINSTRS_H 17 18 #include "llvm/CodeGen/MachineDominators.h" 19 #include "llvm/CodeGen/MachineLoopInfo.h" 20 #include "llvm/CodeGen/ScheduleDAG.h" 21 #include "llvm/Support/Compiler.h" 22 #include "llvm/Target/TargetRegisterInfo.h" 23 #include "llvm/ADT/SmallSet.h" 24 #include "llvm/ADT/SparseSet.h" 25 #include <map> 26 27 namespace llvm { 28 class MachineLoopInfo; 29 class MachineDominatorTree; 30 class LiveIntervals; 31 32 /// LoopDependencies - This class analyzes loop-oriented register 33 /// dependencies, which are used to guide scheduling decisions. 34 /// For example, loop induction variable increments should be 35 /// scheduled as soon as possible after the variable's last use. 36 /// 37 class LoopDependencies { 38 const MachineLoopInfo &MLI; 39 const MachineDominatorTree &MDT; 40 41 public: 42 typedef std::map<unsigned, std::pair<const MachineOperand *, unsigned> > 43 LoopDeps; 44 LoopDeps Deps; 45 46 LoopDependencies(const MachineLoopInfo &mli, 47 const MachineDominatorTree &mdt) : 48 MLI(mli), MDT(mdt) {} 49 50 /// VisitLoop - Clear out any previous state and analyze the given loop. 51 /// 52 void VisitLoop(const MachineLoop *Loop) { 53 assert(Deps.empty() && "stale loop dependencies"); 54 55 MachineBasicBlock *Header = Loop->getHeader(); 56 SmallSet<unsigned, 8> LoopLiveIns; 57 for (MachineBasicBlock::livein_iterator LI = Header->livein_begin(), 58 LE = Header->livein_end(); LI != LE; ++LI) 59 LoopLiveIns.insert(*LI); 60 61 const MachineDomTreeNode *Node = MDT.getNode(Header); 62 const MachineBasicBlock *MBB = Node->getBlock(); 63 assert(Loop->contains(MBB) && 64 "Loop does not contain header!"); 65 VisitRegion(Node, MBB, Loop, LoopLiveIns); 66 } 67 68 private: 69 void VisitRegion(const MachineDomTreeNode *Node, 70 const MachineBasicBlock *MBB, 71 const MachineLoop *Loop, 72 const SmallSet<unsigned, 8> &LoopLiveIns) { 73 unsigned Count = 0; 74 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end(); 75 I != E; ++I) { 76 const MachineInstr *MI = I; 77 if (MI->isDebugValue()) 78 continue; 79 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 80 const MachineOperand &MO = MI->getOperand(i); 81 if (!MO.isReg() || !MO.isUse()) 82 continue; 83 unsigned MOReg = MO.getReg(); 84 if (LoopLiveIns.count(MOReg)) 85 Deps.insert(std::make_pair(MOReg, std::make_pair(&MO, Count))); 86 } 87 ++Count; // Not every iteration due to dbg_value above. 88 } 89 90 const std::vector<MachineDomTreeNode*> &Children = Node->getChildren(); 91 for (std::vector<MachineDomTreeNode*>::const_iterator I = 92 Children.begin(), E = Children.end(); I != E; ++I) { 93 const MachineDomTreeNode *ChildNode = *I; 94 MachineBasicBlock *ChildBlock = ChildNode->getBlock(); 95 if (Loop->contains(ChildBlock)) 96 VisitRegion(ChildNode, ChildBlock, Loop, LoopLiveIns); 97 } 98 } 99 }; 100 101 /// An individual mapping from virtual register number to SUnit. 102 struct VReg2SUnit { 103 unsigned VirtReg; 104 SUnit *SU; 105 106 VReg2SUnit(unsigned reg, SUnit *su): VirtReg(reg), SU(su) {} 107 108 unsigned getSparseSetKey() const { 109 return TargetRegisterInfo::virtReg2Index(VirtReg); 110 } 111 }; 112 113 /// Combine a SparseSet with a 1x1 vector to track physical registers. 114 /// The SparseSet allows iterating over the (few) live registers for quickly 115 /// comparing against a regmask or clearing the set. 116 /// 117 /// Storage for the map is allocated once for the pass. The map can be 118 /// cleared between scheduling regions without freeing unused entries. 119 class Reg2SUnitsMap { 120 SparseSet<unsigned> PhysRegSet; 121 std::vector<std::vector<SUnit*> > SUnits; 122 public: 123 typedef SparseSet<unsigned>::const_iterator const_iterator; 124 125 // Allow iteration over register numbers (keys) in the map. If needed, we 126 // can provide an iterator over SUnits (values) as well. 127 const_iterator reg_begin() const { return PhysRegSet.begin(); } 128 const_iterator reg_end() const { return PhysRegSet.end(); } 129 130 /// Initialize the map with the number of registers. 131 /// If the map is already large enough, no allocation occurs. 132 /// For simplicity we expect the map to be empty(). 133 void setRegLimit(unsigned Limit); 134 135 /// Returns true if the map is empty. 136 bool empty() const { return PhysRegSet.empty(); } 137 138 /// Clear the map without deallocating storage. 139 void clear(); 140 141 bool contains(unsigned Reg) const { return PhysRegSet.count(Reg); } 142 143 /// If this register is mapped, return its existing SUnits vector. 144 /// Otherwise map the register and return an empty SUnits vector. 145 std::vector<SUnit *> &operator[](unsigned Reg) { 146 bool New = PhysRegSet.insert(Reg).second; 147 assert((!New || SUnits[Reg].empty()) && "stale SUnits vector"); 148 (void)New; 149 return SUnits[Reg]; 150 } 151 152 /// Erase an existing element without freeing memory. 153 void erase(unsigned Reg) { 154 PhysRegSet.erase(Reg); 155 SUnits[Reg].clear(); 156 } 157 }; 158 159 /// Use SparseSet as a SparseMap by relying on the fact that it never 160 /// compares ValueT's, only unsigned keys. This allows the set to be cleared 161 /// between scheduling regions in constant time as long as ValueT does not 162 /// require a destructor. 163 typedef SparseSet<VReg2SUnit> VReg2SUnitMap; 164 165 /// ScheduleDAGInstrs - A ScheduleDAG subclass for scheduling lists of 166 /// MachineInstrs. 167 class ScheduleDAGInstrs : public ScheduleDAG { 168 protected: 169 const MachineLoopInfo &MLI; 170 const MachineDominatorTree &MDT; 171 const MachineFrameInfo *MFI; 172 const InstrItineraryData *InstrItins; 173 174 /// Live Intervals provides reaching defs in preRA scheduling. 175 LiveIntervals *LIS; 176 177 /// isPostRA flag indicates vregs cannot be present. 178 bool IsPostRA; 179 180 /// UnitLatencies (misnamed) flag avoids computing def-use latencies, using 181 /// the def-side latency only. 182 bool UnitLatencies; 183 184 /// The standard DAG builder does not normally include terminators as DAG 185 /// nodes because it does not create the necessary dependencies to prevent 186 /// reordering. A specialized scheduler can overide 187 /// TargetInstrInfo::isSchedulingBoundary then enable this flag to indicate 188 /// it has taken responsibility for scheduling the terminator correctly. 189 bool CanHandleTerminators; 190 191 /// State specific to the current scheduling region. 192 /// ------------------------------------------------ 193 194 /// The block in which to insert instructions 195 MachineBasicBlock *BB; 196 197 /// The beginning of the range to be scheduled. 198 MachineBasicBlock::iterator RegionBegin; 199 200 /// The end of the range to be scheduled. 201 MachineBasicBlock::iterator RegionEnd; 202 203 /// The index in BB of RegionEnd. 204 unsigned EndIndex; 205 206 /// After calling BuildSchedGraph, each machine instruction in the current 207 /// scheduling region is mapped to an SUnit. 208 DenseMap<MachineInstr*, SUnit*> MISUnitMap; 209 210 /// State internal to DAG building. 211 /// ------------------------------- 212 213 /// Defs, Uses - Remember where defs and uses of each register are as we 214 /// iterate upward through the instructions. This is allocated here instead 215 /// of inside BuildSchedGraph to avoid the need for it to be initialized and 216 /// destructed for each block. 217 Reg2SUnitsMap Defs; 218 Reg2SUnitsMap Uses; 219 220 /// Track the last instructon in this region defining each virtual register. 221 VReg2SUnitMap VRegDefs; 222 223 /// PendingLoads - Remember where unknown loads are after the most recent 224 /// unknown store, as we iterate. As with Defs and Uses, this is here 225 /// to minimize construction/destruction. 226 std::vector<SUnit *> PendingLoads; 227 228 /// LoopRegs - Track which registers are used for loop-carried dependencies. 229 /// 230 LoopDependencies LoopRegs; 231 232 /// DbgValues - Remember instruction that preceeds DBG_VALUE. 233 /// These are generated by buildSchedGraph but persist so they can be 234 /// referenced when emitting the final schedule. 235 typedef std::vector<std::pair<MachineInstr *, MachineInstr *> > 236 DbgValueVector; 237 DbgValueVector DbgValues; 238 MachineInstr *FirstDbgValue; 239 240 public: 241 explicit ScheduleDAGInstrs(MachineFunction &mf, 242 const MachineLoopInfo &mli, 243 const MachineDominatorTree &mdt, 244 bool IsPostRAFlag, 245 LiveIntervals *LIS = 0); 246 247 virtual ~ScheduleDAGInstrs() {} 248 249 /// begin - Return an iterator to the top of the current scheduling region. 250 MachineBasicBlock::iterator begin() const { return RegionBegin; } 251 252 /// end - Return an iterator to the bottom of the current scheduling region. 253 MachineBasicBlock::iterator end() const { return RegionEnd; } 254 255 /// newSUnit - Creates a new SUnit and return a ptr to it. 256 SUnit *newSUnit(MachineInstr *MI); 257 258 /// getSUnit - Return an existing SUnit for this MI, or NULL. 259 SUnit *getSUnit(MachineInstr *MI) const; 260 261 /// startBlock - Prepare to perform scheduling in the given block. 262 virtual void startBlock(MachineBasicBlock *BB); 263 264 /// finishBlock - Clean up after scheduling in the given block. 265 virtual void finishBlock(); 266 267 /// Initialize the scheduler state for the next scheduling region. 268 virtual void enterRegion(MachineBasicBlock *bb, 269 MachineBasicBlock::iterator begin, 270 MachineBasicBlock::iterator end, 271 unsigned endcount); 272 273 /// Notify that the scheduler has finished scheduling the current region. 274 virtual void exitRegion(); 275 276 /// buildSchedGraph - Build SUnits from the MachineBasicBlock that we are 277 /// input. 278 void buildSchedGraph(AliasAnalysis *AA); 279 280 /// addSchedBarrierDeps - Add dependencies from instructions in the current 281 /// list of instructions being scheduled to scheduling barrier. We want to 282 /// make sure instructions which define registers that are either used by 283 /// the terminator or are live-out are properly scheduled. This is 284 /// especially important when the definition latency of the return value(s) 285 /// are too high to be hidden by the branch or when the liveout registers 286 /// used by instructions in the fallthrough block. 287 void addSchedBarrierDeps(); 288 289 /// computeLatency - Compute node latency. 290 /// 291 virtual void computeLatency(SUnit *SU); 292 293 /// computeOperandLatency - Override dependence edge latency using 294 /// operand use/def information 295 /// 296 virtual void computeOperandLatency(SUnit *Def, SUnit *Use, 297 SDep& dep) const; 298 299 /// schedule - Order nodes according to selected style, filling 300 /// in the Sequence member. 301 /// 302 /// Typically, a scheduling algorithm will implement schedule() without 303 /// overriding enterRegion() or exitRegion(). 304 virtual void schedule() = 0; 305 306 /// finalizeSchedule - Allow targets to perform final scheduling actions at 307 /// the level of the whole MachineFunction. By default does nothing. 308 virtual void finalizeSchedule() {} 309 310 virtual void dumpNode(const SUnit *SU) const; 311 312 /// Return a label for a DAG node that points to an instruction. 313 virtual std::string getGraphNodeLabel(const SUnit *SU) const; 314 315 /// Return a label for the region of code covered by the DAG. 316 virtual std::string getDAGName() const; 317 318 protected: 319 void initSUnits(); 320 void addPhysRegDataDeps(SUnit *SU, const MachineOperand &MO); 321 void addPhysRegDeps(SUnit *SU, unsigned OperIdx); 322 void addVRegDefDeps(SUnit *SU, unsigned OperIdx); 323 void addVRegUseDeps(SUnit *SU, unsigned OperIdx); 324 325 VReg2SUnitMap::iterator findVRegDef(unsigned VirtReg) { 326 return VRegDefs.find(TargetRegisterInfo::virtReg2Index(VirtReg)); 327 } 328 }; 329 330 /// newSUnit - Creates a new SUnit and return a ptr to it. 331 inline SUnit *ScheduleDAGInstrs::newSUnit(MachineInstr *MI) { 332 #ifndef NDEBUG 333 const SUnit *Addr = SUnits.empty() ? 0 : &SUnits[0]; 334 #endif 335 SUnits.push_back(SUnit(MI, (unsigned)SUnits.size())); 336 assert((Addr == 0 || Addr == &SUnits[0]) && 337 "SUnits std::vector reallocated on the fly!"); 338 SUnits.back().OrigNode = &SUnits.back(); 339 return &SUnits.back(); 340 } 341 342 /// getSUnit - Return an existing SUnit for this MI, or NULL. 343 inline SUnit *ScheduleDAGInstrs::getSUnit(MachineInstr *MI) const { 344 DenseMap<MachineInstr*, SUnit*>::const_iterator I = MISUnitMap.find(MI); 345 if (I == MISUnitMap.end()) 346 return 0; 347 return I->second; 348 } 349 } // namespace llvm 350 351 #endif 352