| /external/llvm/lib/CodeGen/SelectionDAG/ |
| TargetLowering.cpp | [all...] |
| DAGCombiner.cpp | [all...] |
| SelectionDAGBuilder.cpp | [all...] |
| /external/llvm/lib/MC/MCParser/ |
| AsmParser.cpp | 786 const MCExpr *Sub = ApplyModifierToExpr(UE->getSubExpr(), Variant);
787 if (!Sub)
789 return MCUnaryExpr::Create(UE->getOpcode(), Sub, getContext());
[all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | 497 const MCExpr *Sub = NULL;
502 Sub = MCSymbolRefExpr::Create(Sym, *Ctx);
504 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx);
513 if (Sub) {
516 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx);
518 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx);
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenRegisters.cpp | 204 // Add this as a super-register of SR now all sub-registers are in the list.
214 // Noop sub-register indexes are possible, so avoid duplicates.
241 // We found a new name for the orphaned sub-register.
331 assert(SubRegsComplete && "Must precompute sub-registers");
356 // sub-registers. We provide a SetTheory expander class that returns the new
367 throw TGError(Def->getLoc(), "Tuples must have at least 2 sub-registers");
369 // Evaluate the sub-register lists to be zipped.
420 // Replace the sub-register list with Tuple.
432 // Composite registers are always covered by sub-registers.
608 // RC is a sub-class of this class if it is a valid replacement for an
[all...] |
| /external/regex-re2/lib/codereview/ |
| codereview.py | 563 who = re.sub('@.*', '', m.get('sender', ''))
564 text = re.sub("\n(.|\n)*", '', m.get('text', ''))
785 l = Sub(l, taken.keys())
808 def Sub(l1, l2):
812 l = l1 + Sub(l2, l1)
999 pats = Sub(pats, taken) + ['path:'+f for f in files]
[all...] |
| /external/clang/lib/Analysis/ |
| CFG.cpp | [all...] |
| /external/llvm/bindings/ocaml/llvm/ |
| llvm.ml | 151 | Sub
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | [all...] |
| /external/llvm/lib/Transforms/Utils/ |
| SimplifyCFG.cpp | 228 case Instruction::Sub:
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 316 // add/sub are legal for all supported vector VT's.
318 setOperationAction(ISD::SUB , VT, Legal);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 358 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
472 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
712 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
[all...] |
| /prebuilt/common/jython/ |
| jython.jar | |
