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      1 //===-- RegisterClassInfo.h - Dynamic Register Class Info -*- C++ -*-------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file implements the RegisterClassInfo class which provides dynamic
     11 // information about target register classes. Callee saved and reserved
     12 // registers depends on calling conventions and other dynamic information, so
     13 // some things cannot be determined statically.
     14 //
     15 //===----------------------------------------------------------------------===//
     16 
     17 #ifndef LLVM_CODEGEN_REGISTERCLASSINFO_H
     18 #define LLVM_CODEGEN_REGISTERCLASSINFO_H
     19 
     20 #include "llvm/ADT/ArrayRef.h"
     21 #include "llvm/ADT/BitVector.h"
     22 #include "llvm/ADT/OwningPtr.h"
     23 #include "llvm/Target/TargetRegisterInfo.h"
     24 
     25 namespace llvm {
     26 
     27 class RegisterClassInfo {
     28   struct RCInfo {
     29     unsigned Tag;
     30     unsigned NumRegs;
     31     bool ProperSubClass;
     32     OwningArrayPtr<unsigned> Order;
     33 
     34     RCInfo() : Tag(0), NumRegs(0), ProperSubClass(false) {}
     35     operator ArrayRef<unsigned>() const {
     36       return makeArrayRef(Order.get(), NumRegs);
     37     }
     38   };
     39 
     40   // Brief cached information for each register class.
     41   OwningArrayPtr<RCInfo> RegClass;
     42 
     43   // Tag changes whenever cached information needs to be recomputed. An RCInfo
     44   // entry is valid when its tag matches.
     45   unsigned Tag;
     46 
     47   const MachineFunction *MF;
     48   const TargetRegisterInfo *TRI;
     49 
     50   // Callee saved registers of last MF. Assumed to be valid until the next
     51   // runOnFunction() call.
     52   const uint16_t *CalleeSaved;
     53 
     54   // Map register number to CalleeSaved index + 1;
     55   SmallVector<uint8_t, 4> CSRNum;
     56 
     57   // Reserved registers in the current MF.
     58   BitVector Reserved;
     59 
     60   // Compute all information about RC.
     61   void compute(const TargetRegisterClass *RC) const;
     62 
     63   // Return an up-to-date RCInfo for RC.
     64   const RCInfo &get(const TargetRegisterClass *RC) const {
     65     const RCInfo &RCI = RegClass[RC->getID()];
     66     if (Tag != RCI.Tag)
     67       compute(RC);
     68     return RCI;
     69   }
     70 
     71 public:
     72   RegisterClassInfo();
     73 
     74   /// runOnFunction - Prepare to answer questions about MF. This must be called
     75   /// before any other methods are used.
     76   void runOnMachineFunction(const MachineFunction &MF);
     77 
     78   /// getNumAllocatableRegs - Returns the number of actually allocatable
     79   /// registers in RC in the current function.
     80   unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const {
     81     return get(RC).NumRegs;
     82   }
     83 
     84   /// getOrder - Returns the preferred allocation order for RC. The order
     85   /// contains no reserved registers, and registers that alias callee saved
     86   /// registers come last.
     87   ArrayRef<unsigned> getOrder(const TargetRegisterClass *RC) const {
     88     return get(RC);
     89   }
     90 
     91   /// isProperSubClass - Returns true if RC has a legal super-class with more
     92   /// allocatable registers.
     93   ///
     94   /// Register classes like GR32_NOSP are not proper sub-classes because %esp
     95   /// is not allocatable.  Similarly, tGPR is not a proper sub-class in Thumb
     96   /// mode because the GPR super-class is not legal.
     97   bool isProperSubClass(const TargetRegisterClass *RC) const {
     98     return get(RC).ProperSubClass;
     99   }
    100 
    101   /// getLastCalleeSavedAlias - Returns the last callee saved register that
    102   /// overlaps PhysReg, or 0 if Reg doesn't overlap a CSR.
    103   unsigned getLastCalleeSavedAlias(unsigned PhysReg) const {
    104     assert(TargetRegisterInfo::isPhysicalRegister(PhysReg));
    105     if (unsigned N = CSRNum[PhysReg])
    106       return CalleeSaved[N-1];
    107     return 0;
    108   }
    109 
    110   /// isReserved - Returns true when PhysReg is a reserved register.
    111   ///
    112   /// Reserved registers may belong to an allocatable register class, but the
    113   /// target has explicitly requested that they are not used.
    114   ///
    115   bool isReserved(unsigned PhysReg) const {
    116     return Reserved.test(PhysReg);
    117   }
    118 
    119   /// isAllocatable - Returns true when PhysReg belongs to an allocatable
    120   /// register class and it hasn't been reserved.
    121   ///
    122   /// Allocatable registers may show up in the allocation order of some virtual
    123   /// register, so a register allocator needs to track its liveness and
    124   /// availability.
    125   bool isAllocatable(unsigned PhysReg) const {
    126     return TRI->isInAllocatableClass(PhysReg) && !isReserved(PhysReg);
    127   }
    128 };
    129 } // end namespace llvm
    130 
    131 #endif
    132 
    133