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    Searched refs:IndexReg (Results 1 - 10 of 10) sorted by null

  /external/llvm/lib/Target/X86/InstPrinter/
X86ATTInstPrinter.cpp 139 const MCOperand &IndexReg = MI->getOperand(Op+2);
151 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
158 if (IndexReg.getReg() || BaseReg.getReg()) {
163 if (IndexReg.getReg()) {
X86IntelInstPrinter.cpp 131 const MCOperand &IndexReg = MI->getOperand(Op+2);
149 if (IndexReg.getReg()) {
164 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
  /external/llvm/lib/Target/X86/
X86InstrBuilder.h 49 unsigned IndexReg;
55 : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(0), GVOpFlags(0) {
72 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false,
133 MIB.addImm(AM.Scale).addReg(AM.IndexReg);
X86CodeEmitter.cpp 479 const MachineOperand &IndexReg = MI.getOperand(Op+2);
486 assert(IndexReg.getReg() == 0 && Is64BitMode &&
507 IndexReg.getReg() == 0 &&
545 assert(IndexReg.getReg() != X86::ESP &&
546 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
579 if (IndexReg.getReg())
580 IndexRegNo = X86_MC::getX86RegNum(IndexReg.getReg());
587 if (IndexReg.getReg())
588 IndexRegNo = X86_MC::getX86RegNum(IndexReg.getReg());
613 const MachineOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg)
    [all...]
X86ISelDAGToDAG.cpp 63 SDValue IndexReg;
75 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0),
85 return IndexReg.getNode() != 0 || Base_Reg.getNode() != 0;
113 << "IndexReg ";
114 if (IndexReg.getNode() != 0)
115 IndexReg.getNode()->dump();
239 Index = AM.IndexReg;
711 AM.Base_Reg = AM.IndexReg;
723 AM.IndexReg.getNode() == 0 &&
782 AM.IndexReg = And
    [all...]
X86FastISel.cpp 411 unsigned IndexReg = AM.IndexReg;
448 if (IndexReg == 0 &&
453 IndexReg = getRegForGEPIndex(Op).first;
454 if (IndexReg == 0)
467 AM.IndexReg = IndexReg;
506 (AM.Base.Reg == 0 && AM.IndexReg == 0)) {
525 assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
587 if (AM.IndexReg == 0)
    [all...]
X86AsmPrinter.cpp 313 const MachineOperand &IndexReg = MI->getOperand(Op+2);
323 bool HasParenPart = IndexReg.getReg() || HasBaseReg;
339 assert(IndexReg.getReg() != X86::ESP &&
346 if (IndexReg.getReg()) {
X86ISelLowering.cpp     [all...]
  /external/llvm/lib/Target/X86/AsmParser/
X86AsmParser.cpp 192 unsigned IndexReg;
244 return Mem.IndexReg;
470 Res->Mem.IndexReg = 0;
478 unsigned BaseReg, unsigned IndexReg,
483 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
492 Res->Mem.IndexReg = IndexReg;
508 Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0);
518 Op.Mem.BaseReg == basereg && Op.Mem.IndexReg == 0;
649 unsigned BaseReg = 0, IndexReg = 0, Scale = 1
    [all...]
  /external/llvm/lib/Target/X86/MCTargetDesc/
X86MCCodeEmitter.cpp 167 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
171 (IndexReg.getReg() != 0 &&
172 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg())))
182 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
186 (IndexReg.getReg() != 0 &&
187 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.getReg())))
197 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
201 (IndexReg.getReg() != 0 &&
202 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg())))
305 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg)
    [all...]

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