| /external/llvm/include/llvm/MC/ |
| MCInstrDesc.h | 136 unsigned short Opcode; // The opcode number
159 /// getOpcode - Return the opcode number for this descriptor.
161 return Opcode;
522 /// or zero if the encoding size cannot be known from the opcode.
|
| MCExpr.h | 257 enum Opcode {
265 Opcode Op;
268 MCUnaryExpr(Opcode _Op, const MCExpr *_Expr)
275 static const MCUnaryExpr *Create(Opcode Op, const MCExpr *Expr,
295 Opcode getOpcode() const { return Op; }
311 enum Opcode {
337 Opcode Op;
340 MCBinaryExpr(Opcode _Op, const MCExpr *_LHS, const MCExpr *_RHS)
347 static const MCBinaryExpr *Create(Opcode Op, const MCExpr *LHS,
427 Opcode getOpcode() const { return Op;
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMExpandPseudoInsts.cpp | 326 static const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) {
341 std::lower_bound(NEONLdStTable, NEONLdStTable + NumEntries, Opcode);
342 if (I != NEONLdStTable + NumEntries && I->PseudoOpc == Opcode)
614 unsigned Opcode = MI.getOpcode();
619 bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm;
624 (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) {
[all...] |
| Thumb2SizeReduction.cpp | 42 uint16_t WideOpc; // Wide opcode
43 uint16_t NarrowOpc1; // Narrow opcode to transform to
44 uint16_t NarrowOpc2; // Narrow opcode when it's two-address
107 // FIXME: Clean this up after splitting each Thumb load / store opcode
147 /// ReduceOpcodeMap - Maps wide opcode to index of entry in ReduceTable.
278 /// Old opcode has an optional def of CPSR.
281 // If old opcode does not implicitly define CPSR, then it's not ok since
343 llvm_unreachable("Unexpected Thumb2 load / store opcode!");
579 // source insn opcode. So for now, we hack a local entry record to use.
868 unsigned Opcode = MI->getOpcode()
[all...] |
| ARMAsmPrinter.cpp | [all...] |
| ARMCodeEmitter.cpp | 282 unsigned Reloc = (MCID.Opcode == ARM::MOVi16 ?
362 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
427 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
869 unsigned Opcode = MI.getDesc().Opcode;
[all...] |
| ARMBaseInstrInfo.cpp | 54 uint16_t MLxOpc; // MLA / MLS opcode
55 uint16_t MulOpc; // Expanded multiplication opcode
56 uint16_t AddSubOpc; // Expanded add / sub opcode
[all...] |
| ARMConstantIslandPass.cpp | 232 /// opcode.
[all...] |
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 53 unsigned Opcode = MI->getOpcode();
56 if (Opcode == ARM::HINT || Opcode == ARM::t2HINT) {
70 if (Opcode == ARM::t2HINT)
77 if (Opcode == ARM::MOVsr) {
97 if (Opcode == ARM::MOVsi) {
122 if ((Opcode == ARM::STMDB_UPD || Opcode == ARM::t2STMDB_UPD) &&
128 if (Opcode == ARM::t2STMDB_UPD)
135 if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP &
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 85 /// rotate and mask opcode and mask operation.
159 /// Reg in an asm, because the load or store opcode would have to change.
319 // opcode and that it has a immediate integer right operand.
357 unsigned Opcode = N->getOpcode();
362 if (Opcode == ISD::SHL) {
367 } else if (Opcode == ISD::SRL) {
374 } else if (Opcode == ISD::ROTL) {
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| Reassociate.cpp | 159 /// opcode and if it only has one use.
160 static BinaryOperator *isReassociableOp(Value *V, unsigned Opcode) {
162 cast<Instruction>(V)->getOpcode() == Opcode)
270 static void IncorporateWeight(APInt &LHS, const APInt &RHS, unsigned Opcode) {
288 if (Instruction::isIdempotent(Opcode)) {
295 if (Instruction::isNilpotent(Opcode)) {
301 if (Opcode == Instruction::Add) {
307 assert(Opcode == Instruction::Mul && "Unknown associative operation!");
344 static Constant *EvaluateRepeatedConstant(unsigned Opcode, Constant *C,
348 if (Opcode == Instruction::Add
[all...] |
| IndVarSimplify.cpp | 748 unsigned Opcode = DU.NarrowUse->getOpcode();
749 switch (Opcode) {
[all...] |
| /external/llvm/examples/Kaleidoscope/Chapter6/ |
| toy.cpp | 129 char Opcode;
132 UnaryExprAST(char opcode, ExprAST *operand)
133 : Opcode(opcode), Operand(operand) {}
562 Function *F = TheModule->getFunction(std::string("unary")+Opcode);
|
| /external/llvm/examples/Kaleidoscope/Chapter7/ |
| toy.cpp | 134 char Opcode;
137 UnaryExprAST(char opcode, ExprAST *operand)
138 : Opcode(opcode), Operand(operand) {}
640 Function *F = TheModule->getFunction(std::string("unary")+Opcode);
[all...] |
| /external/llvm/lib/Analysis/ |
| InstructionSimplify.cpp | 124 /// it into "(A op B) op' (A op C)". Here "op" is given by Opcode and "op'" is
128 static Value *ExpandBinOp(unsigned Opcode, Value *LHS, Value *RHS,
142 if (Value *L = SimplifyBinOp(Opcode, A, C, Q, MaxRecurse))
143 if (Value *R = SimplifyBinOp(Opcode, B, C, Q, MaxRecurse)) {
165 if (Value *L = SimplifyBinOp(Opcode, A, B, Q, MaxRecurse))
166 if (Value *R = SimplifyBinOp(Opcode, A, C, Q, MaxRecurse)) {
185 /// FactorizeBinOp - Simplify "LHS Opcode RHS" by factorizing out a common term
186 /// using the operation OpCodeToExtract. For example, when Opcode is Add and
189 static Value *FactorizeBinOp(unsigned Opcode, Value *LHS, Value *RHS,
215 if (Value *V = SimplifyBinOp(Opcode, B, DD, Q, MaxRecurse))
[all...] |
| ValueTracking.cpp | 655 unsigned Opcode = LU->getOpcode();
659 if (Opcode == Instruction::Add ||
660 Opcode == Instruction::Sub ||
661 Opcode == Instruction::And ||
662 Opcode == Instruction::Or ||
663 Opcode == Instruction::Mul) {
[all...] |
| /external/llvm/lib/CodeGen/ |
| MachineLICM.cpp | 102 // For each opcode, keep a list of potential CSE instructions.
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGRRList.cpp | 264 /// opcode to determine what register class is being generated.
277 unsigned Opcode = Node->getMachineOpcode();
279 if (Opcode == TargetOpcode::REG_SEQUENCE) {
288 const MCInstrDesc Desc = TII->get(Opcode);
[all...] |
| /external/llvm/lib/MC/ |
| MCDwarf.cpp | 38 // First special line opcode - leave room for the standard opcodes.
43 // Minimum line offset in a special line info. opcode. This value
47 // Range of line offsets in a special line info. opcode.
252 // Standard opcode lengths
351 uint64_t Temp, Opcode;
376 // If the line increment is out of range of a special opcode, we must encode
387 // Use DW_LNS_copy instead of a "line +0, addr +0" special opcode.
393 // Bias the opcode by the special opcode base.
398 // Try using a special opcode
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelDAGToDAG.cpp | 80 SDNode *SelectIndexedLoadZeroExtend64(LoadSDNode *LD, unsigned Opcode,
82 SDNode *SelectIndexedLoadSignExtend64(LoadSDNode *LD, unsigned Opcode,
302 unsigned Opcode = 0;
318 // Figure out base + offset opcode
319 if (LoadedVT == MVT::i64) Opcode = Hexagon::LDrid_indexed;
320 else if (LoadedVT == MVT::i32) Opcode = Hexagon::LDriw_indexed;
321 else if (LoadedVT == MVT::i16) Opcode = Hexagon::LDrih_indexed;
322 else if (LoadedVT == MVT::i8) Opcode = Hexagon::LDrib_indexed;
327 SDNode* Result = CurDAG->getMachineNode(Opcode, dl,
346 unsigned Opcode,
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 43 const char *MBlazeTargetLowering::getTargetNodeName(unsigned Opcode) const {
44 switch (Opcode) {
356 // true/false values to select between, and a branch opcode to use.
492 unsigned opcode = 0; local
495 case MBlaze::LAA32: opcode = MBlaze::ADDIK; break;
496 case MBlaze::LAS32: opcode = MBlaze::RSUBIK; break;
497 case MBlaze::LAD32: opcode = MBlaze::AND; break;
498 case MBlaze::LAO32: opcode = MBlaze::OR; break;
499 case MBlaze::LAX32: opcode = MBlaze::XOR; break;
500 case MBlaze::LAN32: opcode = MBlaze::AND; break
[all...] |
| /external/llvm/utils/TableGen/ |
| DAGISelMatcher.h | 60 CheckOpcode, // Fail if not opcode.
61 SwitchOpcode, // Dispatch based on opcode.
448 /// specified opcode, if not it fails to match.
450 const SDNodeInfo &Opcode;
452 CheckOpcodeMatcher(const SDNodeInfo &opcode)
453 : Matcher(CheckOpcode), Opcode(opcode) {}
455 const SDNodeInfo &getOpcode() const { return Opcode; }
470 /// SwitchOpcodeMatcher - Switch based on the current node's opcode, dispatching
471 /// to one matcher per opcode. If the opcode doesn't match any of the cases
[all...] |
| /sdk/emulator/qtools/ |
| opcode.h | 9 // the opflags[] array in opcode.cpp.
10 enum Opcode {
113 // Define bit flags for the opcode categories
132 inline bool isALU(Opcode op) { return (opcode_flags[op] & kCatAlu) != 0; }
133 inline bool isBranch(Opcode op) { return (opcode_flags[op] & kCatBranch) != 0; }
134 inline bool isBranchLink(Opcode op) {
137 inline bool isBranchExch(Opcode op) {
140 inline bool isLoad(Opcode op) { return (opcode_flags[op] & kCatLoad) != 0; }
141 inline bool isLoadMultiple(Opcode op) {
144 inline bool isStoreMultiple(Opcode op)
[all...] |
| /external/javassist/src/main/javassist/bytecode/ |
| Opcode.java | 26 public interface Opcode {
440 0, // wide, 196 depends on the following opcode
|
| /external/llvm/lib/MC/MCParser/ |
| AsmParser.cpp | [all...] |
