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      1 //===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file implements the ARM specific subclass of TargetSubtargetInfo.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #include "ARMSubtarget.h"
     15 #include "ARMBaseRegisterInfo.h"
     16 #include "llvm/GlobalValue.h"
     17 #include "llvm/Target/TargetSubtargetInfo.h"
     18 #include "llvm/Support/CommandLine.h"
     19 
     20 #define GET_SUBTARGETINFO_TARGET_DESC
     21 #define GET_SUBTARGETINFO_CTOR
     22 #include "ARMGenSubtargetInfo.inc"
     23 
     24 using namespace llvm;
     25 
     26 cl::opt<bool>
     27 ReserveR9("arm-reserve-r9", cl::Hidden,
     28           cl::desc("Reserve R9, making it unavailable as GPR"));
     29 
     30 static cl::opt<bool>
     31 DarwinUseMOVT("arm-darwin-use-movt", cl::init(true), cl::Hidden);
     32 
     33 static cl::opt<bool>
     34 StrictAlign("arm-strict-align", cl::Hidden,
     35             cl::desc("Disallow all unaligned memory accesses"));
     36 
     37 ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
     38                            const std::string &FS)
     39   : ARMGenSubtargetInfo(TT, CPU, FS)
     40   , ARMProcFamily(Others)
     41   , HasV4TOps(false)
     42   , HasV5TOps(false)
     43   , HasV5TEOps(false)
     44   , HasV6Ops(false)
     45   , HasV6T2Ops(false)
     46   , HasV7Ops(false)
     47   , HasVFPv2(false)
     48   , HasVFPv3(false)
     49   , HasVFPv4(false)
     50   , HasNEON(false)
     51   , UseNEONForSinglePrecisionFP(false)
     52   , SlowFPVMLx(false)
     53   , HasVMLxForwarding(false)
     54   , SlowFPBrcc(false)
     55   , InThumbMode(false)
     56   , HasThumb2(false)
     57   , IsMClass(false)
     58   , NoARM(false)
     59   , PostRAScheduler(false)
     60   , IsR9Reserved(ReserveR9)
     61   , UseMovt(false)
     62   , SupportsTailCall(false)
     63   , HasFP16(false)
     64   , HasD16(false)
     65   , HasHardwareDivide(false)
     66   , HasT2ExtractPack(false)
     67   , HasDataBarrier(false)
     68   , Pref32BitThumb(false)
     69   , AvoidCPSRPartialUpdate(false)
     70   , HasRAS(false)
     71   , HasMPExtension(false)
     72   , FPOnlySP(false)
     73   , AllowsUnalignedMem(false)
     74   , Thumb2DSP(false)
     75   , stackAlignment(4)
     76   , CPUString(CPU)
     77   , TargetTriple(TT)
     78   , TargetABI(ARM_ABI_APCS) {
     79   // Determine default and user specified characteristics
     80   if (CPUString.empty())
     81     CPUString = "generic";
     82 
     83   // Insert the architecture feature derived from the target triple into the
     84   // feature string. This is important for setting features that are implied
     85   // based on the architecture version.
     86   std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPUString);
     87   if (!FS.empty()) {
     88     if (!ArchFS.empty())
     89       ArchFS = ArchFS + "," + FS;
     90     else
     91       ArchFS = FS;
     92   }
     93   ParseSubtargetFeatures(CPUString, ArchFS);
     94 
     95   // Thumb2 implies at least V6T2. FIXME: Fix tests to explicitly specify a
     96   // ARM version or CPU and then remove this.
     97   if (!HasV6T2Ops && hasThumb2())
     98     HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true;
     99 
    100   // Keep a pointer to static instruction cost data for the specified CPU.
    101   SchedModel = getSchedModelForCPU(CPUString);
    102 
    103   // Initialize scheduling itinerary for the specified CPU.
    104   InstrItins = getInstrItineraryForCPU(CPUString);
    105 
    106   if ((TT.find("eabi") != std::string::npos) || (isTargetIOS() && isMClass()))
    107     // FIXME: We might want to separate AAPCS and EABI. Some systems, e.g.
    108     // Darwin-EABI conforms to AACPS but not the rest of EABI.
    109     TargetABI = ARM_ABI_AAPCS;
    110 
    111   if (isAAPCS_ABI())
    112     stackAlignment = 8;
    113 
    114   if (!isTargetIOS())
    115     UseMovt = hasV6T2Ops();
    116   else {
    117     IsR9Reserved = ReserveR9 | !HasV6Ops;
    118     UseMovt = DarwinUseMOVT && hasV6T2Ops();
    119     SupportsTailCall = !getTargetTriple().isOSVersionLT(5, 0);
    120   }
    121 
    122   if (!isThumb() || hasThumb2())
    123     PostRAScheduler = true;
    124 
    125   // v6+ may or may not support unaligned mem access depending on the system
    126   // configuration.
    127   if (!StrictAlign && hasV6Ops() && isTargetDarwin())
    128     AllowsUnalignedMem = true;
    129 }
    130 
    131 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol.
    132 bool
    133 ARMSubtarget::GVIsIndirectSymbol(const GlobalValue *GV,
    134                                  Reloc::Model RelocM) const {
    135   if (RelocM == Reloc::Static)
    136     return false;
    137 
    138   // Materializable GVs (in JIT lazy compilation mode) do not require an extra
    139   // load from stub.
    140   bool isDecl = GV->hasAvailableExternallyLinkage();
    141   if (GV->isDeclaration() && !GV->isMaterializable())
    142     isDecl = true;
    143 
    144   if (!isTargetDarwin()) {
    145     // Extra load is needed for all externally visible.
    146     if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
    147       return false;
    148     return true;
    149   } else {
    150     if (RelocM == Reloc::PIC_) {
    151       // If this is a strong reference to a definition, it is definitely not
    152       // through a stub.
    153       if (!isDecl && !GV->isWeakForLinker())
    154         return false;
    155 
    156       // Unless we have a symbol with hidden visibility, we have to go through a
    157       // normal $non_lazy_ptr stub because this symbol might be resolved late.
    158       if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
    159         return true;
    160 
    161       // If symbol visibility is hidden, we have a stub for common symbol
    162       // references and external declarations.
    163       if (isDecl || GV->hasCommonLinkage())
    164         // Hidden $non_lazy_ptr reference.
    165         return true;
    166 
    167       return false;
    168     } else {
    169       // If this is a strong reference to a definition, it is definitely not
    170       // through a stub.
    171       if (!isDecl && !GV->isWeakForLinker())
    172         return false;
    173 
    174       // Unless we have a symbol with hidden visibility, we have to go through a
    175       // normal $non_lazy_ptr stub because this symbol might be resolved late.
    176       if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
    177         return true;
    178     }
    179   }
    180 
    181   return false;
    182 }
    183 
    184 unsigned ARMSubtarget::getMispredictionPenalty() const {
    185   return SchedModel->MispredictPenalty;
    186 }
    187 
    188 bool ARMSubtarget::enablePostRAScheduler(
    189            CodeGenOpt::Level OptLevel,
    190            TargetSubtargetInfo::AntiDepBreakMode& Mode,
    191            RegClassVector& CriticalPathRCs) const {
    192   Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
    193   CriticalPathRCs.clear();
    194   CriticalPathRCs.push_back(&ARM::GPRRegClass);
    195   return PostRAScheduler && OptLevel >= CodeGenOpt::Default;
    196 }
    197