| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64ELFObjectWriter.cpp | 1 //===-- AArch64ELFObjectWriter.cpp - AArch64 ELF Writer -------------------===//
62 case AArch64::fixup_a64_ld_prel:
65 case AArch64::fixup_a64_adr_prel:
68 case AArch64::fixup_a64_adr_prel_page:
71 case AArch64::fixup_a64_adr_prel_got_page:
74 case AArch64::fixup_a64_tstbr:
77 case AArch64::fixup_a64_condbr:
80 case AArch64::fixup_a64_uncondbr:
83 case AArch64::fixup_a64_call:
86 case AArch64::fixup_a64_adr_gottprel_page
[all...] |
| AArch64AsmBackend.cpp | 1 //===-- AArch64AsmBackend.cpp - AArch64 Assembler Backend -----------------===//
10 // This file contains the AArch64 implementation of the MCAsmBackend class,
69 if ((uint32_t)Fixup.getKind() == AArch64::fixup_a64_adr_prel_page ||
70 (uint32_t)Fixup.getKind() == AArch64::fixup_a64_adr_prel_got_page ||
71 (uint32_t)Fixup.getKind() == AArch64::fixup_a64_adr_gottprel_page ||
72 (uint32_t)Fixup.getKind() == AArch64::fixup_a64_tlsdesc_adr_page)
94 return AArch64::NumTargetFixupKinds;
98 const static MCFixupKindInfo Infos[AArch64::NumTargetFixupKinds] = {
256 case AArch64::fixup_a64_ld_gottprel_prel19:
259 case AArch64::fixup_a64_ld_prel
[all...] |
| AArch64MCCodeEmitter.cpp | 1 //=- AArch64/AArch64MCCodeEmitter.cpp - Convert AArch64 code to machine code =//
65 template<AArch64::Fixups fixupDesired>
155 unsigned FixupsBySize[] = { AArch64::fixup_a64_ldst8_lo12,
156 AArch64::fixup_a64_ldst16_lo12,
157 AArch64::fixup_a64_ldst32_lo12,
158 AArch64::fixup_a64_ldst64_lo12,
159 AArch64::fixup_a64_ldst128_lo12 };
166 FixupKind = AArch64::fixup_a64_ld64_got_lo12_nc;
169 unsigned FixupsBySize[] = { AArch64::fixup_a64_ldst8_dtprel_lo12
[all...] |
| AArch64MCTargetDesc.cpp | 1 //===-- AArch64MCTargetDesc.cpp - AArch64 Target Descriptions -------------===//
10 // This file provides AArch64 specific target descriptions.
56 InitAArch64MCRegisterInfo(X, AArch64::X30);
65 MachineLocation Src(AArch64::XSP, 0);
119 if (Inst.getOpcode() == AArch64::Bcc
126 if (Inst.getOpcode() == AArch64::Bcc
134 unsigned LblOperand = Inst.getOpcode() == AArch64::Bcc ? 1 : 0;
|
| AArch64FixupKinds.h | 1 //=- AArch64/AArch64FixupKinds.h - AArch64 Specific Fixup Entries -*- C++ -*-=//
10 // This file describes the LLVM fixups applied to MCInsts in the AArch64
21 namespace AArch64 {
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.cpp | 1 //===- AArch64InstrInfo.cpp - AArch64 Instruction Information -------------===//
10 // This file contains the AArch64 implementation of the TargetInstrInfo class.
14 #include "AArch64.h"
38 : AArch64GenInstrInfo(AArch64::ADJCALLSTACKDOWN, AArch64::ADJCALLSTACKUP),
47 if (DestReg == AArch64::XSP || SrcReg == AArch64::XSP) {
49 BuildMI(MBB, I, DL, get(AArch64::ADDxxi_lsl0_s), DestReg)
53 } else if (DestReg == AArch64::WSP || SrcReg == AArch64::WSP)
[all...] |
| AArch64RegisterInfo.cpp | 1 //===- AArch64RegisterInfo.cpp - AArch64 Register Information -------------===//
10 // This file contains the AArch64 implementation of the TargetRegisterInfo
34 : AArch64GenRegisterInfo(AArch64::X30), TII(tii) {
53 if (RC == &AArch64::FlagClassRegClass)
54 return &AArch64::GPR64RegClass;
66 Reserved.set(AArch64::XSP);
67 Reserved.set(AArch64::WSP);
69 Reserved.set(AArch64::XZR);
70 Reserved.set(AArch64::WZR);
73 Reserved.set(AArch64::X29)
[all...] |
| AArch64FrameLowering.cpp | 1 //===- AArch64FrameLowering.cpp - AArch64 Frame Information ---------------===//
10 // This file contains the AArch64 implementation of TargetFrameLowering class.
14 #include "AArch64.h"
89 emitSPUpdate(MBB, MBBI, DL, TII, AArch64::X16, -NumInitialBytes,
100 MachineLocation Src(AArch64::XSP, NumInitialBytes);
113 if (FPNeedsSetting && MBBI->getOpcode() == AArch64::LSPair64_STR
114 && MBBI->getOperand(0).getReg() == AArch64::X29) {
119 emitRegUpdate(MBB, MBBI, DL, TII, AArch64::X29, AArch64::XSP,
120 AArch64::X29
[all...] |
| AArch64BranchFixupPass.cpp | 1 //===-- AArch64BranchFixupPass.cpp - AArch64 branch fixup -----------------===//
10 // This file contains a pass that fixes AArch64 branches which have ended up out
15 #define DEBUG_TYPE "aarch64-branch-fixup"
16 #include "AArch64.h"
141 return "AArch64 branch fixup pass";
293 case AArch64::TBZxii:
294 case AArch64::TBZwii:
295 case AArch64::TBNZxii:
296 case AArch64::TBNZwii:
300 case AArch64::Bcc
[all...] |
| AArch64RegisterInfo.h | 1 //==- AArch64RegisterInfo.h - AArch64 Register Information Impl -*- C++ -*-===//
10 // This file contains the AArch64 implementation of the MCRegisterInfo class.
57 if (RC == &AArch64::tcGPR64RegClass)
58 return &AArch64::GPR64RegClass;
|
| Makefile | 1 ##===- lib/Target/AArch64/Makefile -------------------------*- Makefile -*-===##
12 TARGET = AArch64
|
| AArch64AsmPrinter.cpp | 1 //===-- AArch64AsmPrinter.cpp - Print machine code to an AArch64 .s file --===//
11 // of machine-dependent LLVM code to GAS-format AArch64 assembly language.
65 char Prefix = &RegClass == &AArch64::GPR32RegClass ? 'w' : 'x';
71 if (MO.getReg() == AArch64::XSP || MO.getReg() == AArch64::WSP) {
170 if (printModifiedFPRAsmOperand(MO, TRI, AArch64::VPR128RegClass, O))
203 AArch64::GPR32RegClass, O);
208 AArch64::GPR64RegClass, O);
226 AArch64::FPR8RegClass, O);
230 AArch64::FPR16RegClass, O)
[all...] |
| AArch64ISelLowering.cpp | 1 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation -----===//
10 // This file defines the interfaces that AArch64 uses to lower LLVM code into a
15 #define DEBUG_TYPE "aarch64-isel"
16 #include "AArch64.h"
53 addRegisterClass(MVT::i32, &AArch64::GPR32RegClass);
54 addRegisterClass(MVT::i64, &AArch64::GPR64RegClass);
55 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass);
56 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass);
57 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass);
58 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass)
[all...] |
| AArch64ISelDAGToDAG.cpp | 1 //===-- AArch64ISelDAGToDAG.cpp - A dag to dag inst selector for AArch64 --===//
10 // This file defines an instruction selector for the AArch64 target.
14 #define DEBUG_TYPE "aarch64-isel"
15 #include "AArch64.h"
29 /// AArch64 specific code to select AArch64 machine instructions for
51 return "AArch64 Instruction Selection";
137 default: llvm_unreachable("Unrecognised AArch64 memory constraint");
190 MOVOpcode = DestWidth == 64 ? AArch64::MOVZxii : AArch64::MOVZwii
[all...] |
| /external/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.cpp | 1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 ISA -------------===//
10 // This file contains the functions necessary to decode AArch64 instruction
18 #include "AArch64.h"
39 /// AArch64 disassembler for all AArch64 platforms.
245 uint16_t Register = getReg(Decoder, AArch64::GPR64RegClassID, RegNo);
256 uint16_t Register = getReg(Decoder, AArch64::GPR64xspRegClassID, RegNo);
267 uint16_t Register = getReg(Decoder, AArch64::GPR32RegClassID, RegNo);
278 uint16_t Register = getReg(Decoder, AArch64::GPR32wspRegClassID, RegNo);
289 uint16_t Register = getReg(Decoder, AArch64::FPR8RegClassID, RegNo)
[all...] |
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | 1 //==- AArch64AsmParser.cpp - Parse AArch64 assembly to MCInst instructions -==//
10 // This file contains the (GNU-style) assembly parser for the AArch64
146 /// Instances of this class represent a parsed AArch64 machine instruction.
[all...] |
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.h | 1 //===-- AArch64InstPrinter.h - Convert AArch64 MCInst to assembly syntax --===//
10 // This class prints an AArch64 MCInst to a .s file.
164 return RegNo == AArch64::XSP || RegNo == AArch64::WSP;
|
| AArch64InstPrinter.cpp | 1 //==-- AArch64InstPrinter.cpp - Convert AArch64 MCInst to assembly syntax --==//
10 // This class prints an AArch64 MCInst to a .s file.
334 if (Reg0 == AArch64::XSP || Reg1 == AArch64::XSP)
399 if (MI->getOpcode() == AArch64::TLSDESCCALL) {
|
| /external/llvm/projects/sample/ |
| configure | [all...] |
| /external/llvm/ |
| configure | [all...] |
