1 //===- AsmMatcherEmitter.cpp - Generate an assembly matcher ---------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This tablegen backend emits a target specifier matcher for converting parsed 11 // assembly operands in the MCInst structures. It also emits a matcher for 12 // custom operand parsing. 13 // 14 // Converting assembly operands into MCInst structures 15 // --------------------------------------------------- 16 // 17 // The input to the target specific matcher is a list of literal tokens and 18 // operands. The target specific parser should generally eliminate any syntax 19 // which is not relevant for matching; for example, comma tokens should have 20 // already been consumed and eliminated by the parser. Most instructions will 21 // end up with a single literal token (the instruction name) and some number of 22 // operands. 23 // 24 // Some example inputs, for X86: 25 // 'addl' (immediate ...) (register ...) 26 // 'add' (immediate ...) (memory ...) 27 // 'call' '*' %epc 28 // 29 // The assembly matcher is responsible for converting this input into a precise 30 // machine instruction (i.e., an instruction with a well defined encoding). This 31 // mapping has several properties which complicate matching: 32 // 33 // - It may be ambiguous; many architectures can legally encode particular 34 // variants of an instruction in different ways (for example, using a smaller 35 // encoding for small immediates). Such ambiguities should never be 36 // arbitrarily resolved by the assembler, the assembler is always responsible 37 // for choosing the "best" available instruction. 38 // 39 // - It may depend on the subtarget or the assembler context. Instructions 40 // which are invalid for the current mode, but otherwise unambiguous (e.g., 41 // an SSE instruction in a file being assembled for i486) should be accepted 42 // and rejected by the assembler front end. However, if the proper encoding 43 // for an instruction is dependent on the assembler context then the matcher 44 // is responsible for selecting the correct machine instruction for the 45 // current mode. 46 // 47 // The core matching algorithm attempts to exploit the regularity in most 48 // instruction sets to quickly determine the set of possibly matching 49 // instructions, and the simplify the generated code. Additionally, this helps 50 // to ensure that the ambiguities are intentionally resolved by the user. 51 // 52 // The matching is divided into two distinct phases: 53 // 54 // 1. Classification: Each operand is mapped to the unique set which (a) 55 // contains it, and (b) is the largest such subset for which a single 56 // instruction could match all members. 57 // 58 // For register classes, we can generate these subgroups automatically. For 59 // arbitrary operands, we expect the user to define the classes and their 60 // relations to one another (for example, 8-bit signed immediates as a 61 // subset of 32-bit immediates). 62 // 63 // By partitioning the operands in this way, we guarantee that for any 64 // tuple of classes, any single instruction must match either all or none 65 // of the sets of operands which could classify to that tuple. 66 // 67 // In addition, the subset relation amongst classes induces a partial order 68 // on such tuples, which we use to resolve ambiguities. 69 // 70 // 2. The input can now be treated as a tuple of classes (static tokens are 71 // simple singleton sets). Each such tuple should generally map to a single 72 // instruction (we currently ignore cases where this isn't true, whee!!!), 73 // which we can emit a simple matcher for. 74 // 75 // Custom Operand Parsing 76 // ---------------------- 77 // 78 // Some targets need a custom way to parse operands, some specific instructions 79 // can contain arguments that can represent processor flags and other kinds of 80 // identifiers that need to be mapped to specific values in the final encoded 81 // instructions. The target specific custom operand parsing works in the 82 // following way: 83 // 84 // 1. A operand match table is built, each entry contains a mnemonic, an 85 // operand class, a mask for all operand positions for that same 86 // class/mnemonic and target features to be checked while trying to match. 87 // 88 // 2. The operand matcher will try every possible entry with the same 89 // mnemonic and will check if the target feature for this mnemonic also 90 // matches. After that, if the operand to be matched has its index 91 // present in the mask, a successful match occurs. Otherwise, fallback 92 // to the regular operand parsing. 93 // 94 // 3. For a match success, each operand class that has a 'ParserMethod' 95 // becomes part of a switch from where the custom method is called. 96 // 97 //===----------------------------------------------------------------------===// 98 99 #include "CodeGenTarget.h" 100 #include "StringToOffsetTable.h" 101 #include "llvm/ADT/OwningPtr.h" 102 #include "llvm/ADT/PointerUnion.h" 103 #include "llvm/ADT/STLExtras.h" 104 #include "llvm/ADT/SmallPtrSet.h" 105 #include "llvm/ADT/SmallVector.h" 106 #include "llvm/ADT/StringExtras.h" 107 #include "llvm/Support/CommandLine.h" 108 #include "llvm/Support/Debug.h" 109 #include "llvm/Support/ErrorHandling.h" 110 #include "llvm/TableGen/Error.h" 111 #include "llvm/TableGen/Record.h" 112 #include "llvm/TableGen/StringMatcher.h" 113 #include "llvm/TableGen/TableGenBackend.h" 114 #include <cassert> 115 #include <map> 116 #include <set> 117 using namespace llvm; 118 119 static cl::opt<std::string> 120 MatchPrefix("match-prefix", cl::init(""), 121 cl::desc("Only match instructions with the given prefix")); 122 123 namespace { 124 class AsmMatcherInfo; 125 struct SubtargetFeatureInfo; 126 127 class AsmMatcherEmitter { 128 RecordKeeper &Records; 129 public: 130 AsmMatcherEmitter(RecordKeeper &R) : Records(R) {} 131 132 void run(raw_ostream &o); 133 }; 134 135 /// ClassInfo - Helper class for storing the information about a particular 136 /// class of operands which can be matched. 137 struct ClassInfo { 138 enum ClassInfoKind { 139 /// Invalid kind, for use as a sentinel value. 140 Invalid = 0, 141 142 /// The class for a particular token. 143 Token, 144 145 /// The (first) register class, subsequent register classes are 146 /// RegisterClass0+1, and so on. 147 RegisterClass0, 148 149 /// The (first) user defined class, subsequent user defined classes are 150 /// UserClass0+1, and so on. 151 UserClass0 = 1<<16 152 }; 153 154 /// Kind - The class kind, which is either a predefined kind, or (UserClass0 + 155 /// N) for the Nth user defined class. 156 unsigned Kind; 157 158 /// SuperClasses - The super classes of this class. Note that for simplicities 159 /// sake user operands only record their immediate super class, while register 160 /// operands include all superclasses. 161 std::vector<ClassInfo*> SuperClasses; 162 163 /// Name - The full class name, suitable for use in an enum. 164 std::string Name; 165 166 /// ClassName - The unadorned generic name for this class (e.g., Token). 167 std::string ClassName; 168 169 /// ValueName - The name of the value this class represents; for a token this 170 /// is the literal token string, for an operand it is the TableGen class (or 171 /// empty if this is a derived class). 172 std::string ValueName; 173 174 /// PredicateMethod - The name of the operand method to test whether the 175 /// operand matches this class; this is not valid for Token or register kinds. 176 std::string PredicateMethod; 177 178 /// RenderMethod - The name of the operand method to add this operand to an 179 /// MCInst; this is not valid for Token or register kinds. 180 std::string RenderMethod; 181 182 /// ParserMethod - The name of the operand method to do a target specific 183 /// parsing on the operand. 184 std::string ParserMethod; 185 186 /// For register classes, the records for all the registers in this class. 187 std::set<Record*> Registers; 188 189 /// For custom match classes, he diagnostic kind for when the predicate fails. 190 std::string DiagnosticType; 191 public: 192 /// isRegisterClass() - Check if this is a register class. 193 bool isRegisterClass() const { 194 return Kind >= RegisterClass0 && Kind < UserClass0; 195 } 196 197 /// isUserClass() - Check if this is a user defined class. 198 bool isUserClass() const { 199 return Kind >= UserClass0; 200 } 201 202 /// isRelatedTo - Check whether this class is "related" to \p RHS. Classes 203 /// are related if they are in the same class hierarchy. 204 bool isRelatedTo(const ClassInfo &RHS) const { 205 // Tokens are only related to tokens. 206 if (Kind == Token || RHS.Kind == Token) 207 return Kind == Token && RHS.Kind == Token; 208 209 // Registers classes are only related to registers classes, and only if 210 // their intersection is non-empty. 211 if (isRegisterClass() || RHS.isRegisterClass()) { 212 if (!isRegisterClass() || !RHS.isRegisterClass()) 213 return false; 214 215 std::set<Record*> Tmp; 216 std::insert_iterator< std::set<Record*> > II(Tmp, Tmp.begin()); 217 std::set_intersection(Registers.begin(), Registers.end(), 218 RHS.Registers.begin(), RHS.Registers.end(), 219 II); 220 221 return !Tmp.empty(); 222 } 223 224 // Otherwise we have two users operands; they are related if they are in the 225 // same class hierarchy. 226 // 227 // FIXME: This is an oversimplification, they should only be related if they 228 // intersect, however we don't have that information. 229 assert(isUserClass() && RHS.isUserClass() && "Unexpected class!"); 230 const ClassInfo *Root = this; 231 while (!Root->SuperClasses.empty()) 232 Root = Root->SuperClasses.front(); 233 234 const ClassInfo *RHSRoot = &RHS; 235 while (!RHSRoot->SuperClasses.empty()) 236 RHSRoot = RHSRoot->SuperClasses.front(); 237 238 return Root == RHSRoot; 239 } 240 241 /// isSubsetOf - Test whether this class is a subset of \p RHS. 242 bool isSubsetOf(const ClassInfo &RHS) const { 243 // This is a subset of RHS if it is the same class... 244 if (this == &RHS) 245 return true; 246 247 // ... or if any of its super classes are a subset of RHS. 248 for (std::vector<ClassInfo*>::const_iterator it = SuperClasses.begin(), 249 ie = SuperClasses.end(); it != ie; ++it) 250 if ((*it)->isSubsetOf(RHS)) 251 return true; 252 253 return false; 254 } 255 256 /// operator< - Compare two classes. 257 bool operator<(const ClassInfo &RHS) const { 258 if (this == &RHS) 259 return false; 260 261 // Unrelated classes can be ordered by kind. 262 if (!isRelatedTo(RHS)) 263 return Kind < RHS.Kind; 264 265 switch (Kind) { 266 case Invalid: 267 llvm_unreachable("Invalid kind!"); 268 269 default: 270 // This class precedes the RHS if it is a proper subset of the RHS. 271 if (isSubsetOf(RHS)) 272 return true; 273 if (RHS.isSubsetOf(*this)) 274 return false; 275 276 // Otherwise, order by name to ensure we have a total ordering. 277 return ValueName < RHS.ValueName; 278 } 279 } 280 }; 281 282 namespace { 283 /// Sort ClassInfo pointers independently of pointer value. 284 struct LessClassInfoPtr { 285 bool operator()(const ClassInfo *LHS, const ClassInfo *RHS) const { 286 return *LHS < *RHS; 287 } 288 }; 289 } 290 291 /// MatchableInfo - Helper class for storing the necessary information for an 292 /// instruction or alias which is capable of being matched. 293 struct MatchableInfo { 294 struct AsmOperand { 295 /// Token - This is the token that the operand came from. 296 StringRef Token; 297 298 /// The unique class instance this operand should match. 299 ClassInfo *Class; 300 301 /// The operand name this is, if anything. 302 StringRef SrcOpName; 303 304 /// The suboperand index within SrcOpName, or -1 for the entire operand. 305 int SubOpIdx; 306 307 /// Register record if this token is singleton register. 308 Record *SingletonReg; 309 310 explicit AsmOperand(StringRef T) : Token(T), Class(0), SubOpIdx(-1), 311 SingletonReg(0) {} 312 }; 313 314 /// ResOperand - This represents a single operand in the result instruction 315 /// generated by the match. In cases (like addressing modes) where a single 316 /// assembler operand expands to multiple MCOperands, this represents the 317 /// single assembler operand, not the MCOperand. 318 struct ResOperand { 319 enum { 320 /// RenderAsmOperand - This represents an operand result that is 321 /// generated by calling the render method on the assembly operand. The 322 /// corresponding AsmOperand is specified by AsmOperandNum. 323 RenderAsmOperand, 324 325 /// TiedOperand - This represents a result operand that is a duplicate of 326 /// a previous result operand. 327 TiedOperand, 328 329 /// ImmOperand - This represents an immediate value that is dumped into 330 /// the operand. 331 ImmOperand, 332 333 /// RegOperand - This represents a fixed register that is dumped in. 334 RegOperand 335 } Kind; 336 337 union { 338 /// This is the operand # in the AsmOperands list that this should be 339 /// copied from. 340 unsigned AsmOperandNum; 341 342 /// TiedOperandNum - This is the (earlier) result operand that should be 343 /// copied from. 344 unsigned TiedOperandNum; 345 346 /// ImmVal - This is the immediate value added to the instruction. 347 int64_t ImmVal; 348 349 /// Register - This is the register record. 350 Record *Register; 351 }; 352 353 /// MINumOperands - The number of MCInst operands populated by this 354 /// operand. 355 unsigned MINumOperands; 356 357 static ResOperand getRenderedOp(unsigned AsmOpNum, unsigned NumOperands) { 358 ResOperand X; 359 X.Kind = RenderAsmOperand; 360 X.AsmOperandNum = AsmOpNum; 361 X.MINumOperands = NumOperands; 362 return X; 363 } 364 365 static ResOperand getTiedOp(unsigned TiedOperandNum) { 366 ResOperand X; 367 X.Kind = TiedOperand; 368 X.TiedOperandNum = TiedOperandNum; 369 X.MINumOperands = 1; 370 return X; 371 } 372 373 static ResOperand getImmOp(int64_t Val) { 374 ResOperand X; 375 X.Kind = ImmOperand; 376 X.ImmVal = Val; 377 X.MINumOperands = 1; 378 return X; 379 } 380 381 static ResOperand getRegOp(Record *Reg) { 382 ResOperand X; 383 X.Kind = RegOperand; 384 X.Register = Reg; 385 X.MINumOperands = 1; 386 return X; 387 } 388 }; 389 390 /// AsmVariantID - Target's assembly syntax variant no. 391 int AsmVariantID; 392 393 /// TheDef - This is the definition of the instruction or InstAlias that this 394 /// matchable came from. 395 Record *const TheDef; 396 397 /// DefRec - This is the definition that it came from. 398 PointerUnion<const CodeGenInstruction*, const CodeGenInstAlias*> DefRec; 399 400 const CodeGenInstruction *getResultInst() const { 401 if (DefRec.is<const CodeGenInstruction*>()) 402 return DefRec.get<const CodeGenInstruction*>(); 403 return DefRec.get<const CodeGenInstAlias*>()->ResultInst; 404 } 405 406 /// ResOperands - This is the operand list that should be built for the result 407 /// MCInst. 408 SmallVector<ResOperand, 8> ResOperands; 409 410 /// AsmString - The assembly string for this instruction (with variants 411 /// removed), e.g. "movsx $src, $dst". 412 std::string AsmString; 413 414 /// Mnemonic - This is the first token of the matched instruction, its 415 /// mnemonic. 416 StringRef Mnemonic; 417 418 /// AsmOperands - The textual operands that this instruction matches, 419 /// annotated with a class and where in the OperandList they were defined. 420 /// This directly corresponds to the tokenized AsmString after the mnemonic is 421 /// removed. 422 SmallVector<AsmOperand, 8> AsmOperands; 423 424 /// Predicates - The required subtarget features to match this instruction. 425 SmallVector<SubtargetFeatureInfo*, 4> RequiredFeatures; 426 427 /// ConversionFnKind - The enum value which is passed to the generated 428 /// convertToMCInst to convert parsed operands into an MCInst for this 429 /// function. 430 std::string ConversionFnKind; 431 432 MatchableInfo(const CodeGenInstruction &CGI) 433 : AsmVariantID(0), TheDef(CGI.TheDef), DefRec(&CGI), 434 AsmString(CGI.AsmString) { 435 } 436 437 MatchableInfo(const CodeGenInstAlias *Alias) 438 : AsmVariantID(0), TheDef(Alias->TheDef), DefRec(Alias), 439 AsmString(Alias->AsmString) { 440 } 441 442 // Two-operand aliases clone from the main matchable, but mark the second 443 // operand as a tied operand of the first for purposes of the assembler. 444 void formTwoOperandAlias(StringRef Constraint); 445 446 void initialize(const AsmMatcherInfo &Info, 447 SmallPtrSet<Record*, 16> &SingletonRegisters, 448 int AsmVariantNo, std::string &RegisterPrefix); 449 450 /// validate - Return true if this matchable is a valid thing to match against 451 /// and perform a bunch of validity checking. 452 bool validate(StringRef CommentDelimiter, bool Hack) const; 453 454 /// extractSingletonRegisterForAsmOperand - Extract singleton register, 455 /// if present, from specified token. 456 void 457 extractSingletonRegisterForAsmOperand(unsigned i, const AsmMatcherInfo &Info, 458 std::string &RegisterPrefix); 459 460 /// findAsmOperand - Find the AsmOperand with the specified name and 461 /// suboperand index. 462 int findAsmOperand(StringRef N, int SubOpIdx) const { 463 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) 464 if (N == AsmOperands[i].SrcOpName && 465 SubOpIdx == AsmOperands[i].SubOpIdx) 466 return i; 467 return -1; 468 } 469 470 /// findAsmOperandNamed - Find the first AsmOperand with the specified name. 471 /// This does not check the suboperand index. 472 int findAsmOperandNamed(StringRef N) const { 473 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) 474 if (N == AsmOperands[i].SrcOpName) 475 return i; 476 return -1; 477 } 478 479 void buildInstructionResultOperands(); 480 void buildAliasResultOperands(); 481 482 /// operator< - Compare two matchables. 483 bool operator<(const MatchableInfo &RHS) const { 484 // The primary comparator is the instruction mnemonic. 485 if (Mnemonic != RHS.Mnemonic) 486 return Mnemonic < RHS.Mnemonic; 487 488 if (AsmOperands.size() != RHS.AsmOperands.size()) 489 return AsmOperands.size() < RHS.AsmOperands.size(); 490 491 // Compare lexicographically by operand. The matcher validates that other 492 // orderings wouldn't be ambiguous using \see couldMatchAmbiguouslyWith(). 493 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) { 494 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class) 495 return true; 496 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class) 497 return false; 498 } 499 500 // Give matches that require more features higher precedence. This is useful 501 // because we cannot define AssemblerPredicates with the negation of 502 // processor features. For example, ARM v6 "nop" may be either a HINT or 503 // MOV. With v6, we want to match HINT. The assembler has no way to 504 // predicate MOV under "NoV6", but HINT will always match first because it 505 // requires V6 while MOV does not. 506 if (RequiredFeatures.size() != RHS.RequiredFeatures.size()) 507 return RequiredFeatures.size() > RHS.RequiredFeatures.size(); 508 509 return false; 510 } 511 512 /// couldMatchAmbiguouslyWith - Check whether this matchable could 513 /// ambiguously match the same set of operands as \p RHS (without being a 514 /// strictly superior match). 515 bool couldMatchAmbiguouslyWith(const MatchableInfo &RHS) { 516 // The primary comparator is the instruction mnemonic. 517 if (Mnemonic != RHS.Mnemonic) 518 return false; 519 520 // The number of operands is unambiguous. 521 if (AsmOperands.size() != RHS.AsmOperands.size()) 522 return false; 523 524 // Otherwise, make sure the ordering of the two instructions is unambiguous 525 // by checking that either (a) a token or operand kind discriminates them, 526 // or (b) the ordering among equivalent kinds is consistent. 527 528 // Tokens and operand kinds are unambiguous (assuming a correct target 529 // specific parser). 530 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) 531 if (AsmOperands[i].Class->Kind != RHS.AsmOperands[i].Class->Kind || 532 AsmOperands[i].Class->Kind == ClassInfo::Token) 533 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class || 534 *RHS.AsmOperands[i].Class < *AsmOperands[i].Class) 535 return false; 536 537 // Otherwise, this operand could commute if all operands are equivalent, or 538 // there is a pair of operands that compare less than and a pair that 539 // compare greater than. 540 bool HasLT = false, HasGT = false; 541 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) { 542 if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class) 543 HasLT = true; 544 if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class) 545 HasGT = true; 546 } 547 548 return !(HasLT ^ HasGT); 549 } 550 551 void dump(); 552 553 private: 554 void tokenizeAsmString(const AsmMatcherInfo &Info); 555 }; 556 557 /// SubtargetFeatureInfo - Helper class for storing information on a subtarget 558 /// feature which participates in instruction matching. 559 struct SubtargetFeatureInfo { 560 /// \brief The predicate record for this feature. 561 Record *TheDef; 562 563 /// \brief An unique index assigned to represent this feature. 564 unsigned Index; 565 566 SubtargetFeatureInfo(Record *D, unsigned Idx) : TheDef(D), Index(Idx) {} 567 568 /// \brief The name of the enumerated constant identifying this feature. 569 std::string getEnumName() const { 570 return "Feature_" + TheDef->getName(); 571 } 572 }; 573 574 struct OperandMatchEntry { 575 unsigned OperandMask; 576 MatchableInfo* MI; 577 ClassInfo *CI; 578 579 static OperandMatchEntry create(MatchableInfo* mi, ClassInfo *ci, 580 unsigned opMask) { 581 OperandMatchEntry X; 582 X.OperandMask = opMask; 583 X.CI = ci; 584 X.MI = mi; 585 return X; 586 } 587 }; 588 589 590 class AsmMatcherInfo { 591 public: 592 /// Tracked Records 593 RecordKeeper &Records; 594 595 /// The tablegen AsmParser record. 596 Record *AsmParser; 597 598 /// Target - The target information. 599 CodeGenTarget &Target; 600 601 /// The classes which are needed for matching. 602 std::vector<ClassInfo*> Classes; 603 604 /// The information on the matchables to match. 605 std::vector<MatchableInfo*> Matchables; 606 607 /// Info for custom matching operands by user defined methods. 608 std::vector<OperandMatchEntry> OperandMatchInfo; 609 610 /// Map of Register records to their class information. 611 typedef std::map<Record*, ClassInfo*, LessRecordByID> RegisterClassesTy; 612 RegisterClassesTy RegisterClasses; 613 614 /// Map of Predicate records to their subtarget information. 615 std::map<Record*, SubtargetFeatureInfo*> SubtargetFeatures; 616 617 /// Map of AsmOperandClass records to their class information. 618 std::map<Record*, ClassInfo*> AsmOperandClasses; 619 620 private: 621 /// Map of token to class information which has already been constructed. 622 std::map<std::string, ClassInfo*> TokenClasses; 623 624 /// Map of RegisterClass records to their class information. 625 std::map<Record*, ClassInfo*> RegisterClassClasses; 626 627 private: 628 /// getTokenClass - Lookup or create the class for the given token. 629 ClassInfo *getTokenClass(StringRef Token); 630 631 /// getOperandClass - Lookup or create the class for the given operand. 632 ClassInfo *getOperandClass(const CGIOperandList::OperandInfo &OI, 633 int SubOpIdx); 634 ClassInfo *getOperandClass(Record *Rec, int SubOpIdx); 635 636 /// buildRegisterClasses - Build the ClassInfo* instances for register 637 /// classes. 638 void buildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters); 639 640 /// buildOperandClasses - Build the ClassInfo* instances for user defined 641 /// operand classes. 642 void buildOperandClasses(); 643 644 void buildInstructionOperandReference(MatchableInfo *II, StringRef OpName, 645 unsigned AsmOpIdx); 646 void buildAliasOperandReference(MatchableInfo *II, StringRef OpName, 647 MatchableInfo::AsmOperand &Op); 648 649 public: 650 AsmMatcherInfo(Record *AsmParser, 651 CodeGenTarget &Target, 652 RecordKeeper &Records); 653 654 /// buildInfo - Construct the various tables used during matching. 655 void buildInfo(); 656 657 /// buildOperandMatchInfo - Build the necessary information to handle user 658 /// defined operand parsing methods. 659 void buildOperandMatchInfo(); 660 661 /// getSubtargetFeature - Lookup or create the subtarget feature info for the 662 /// given operand. 663 SubtargetFeatureInfo *getSubtargetFeature(Record *Def) const { 664 assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!"); 665 std::map<Record*, SubtargetFeatureInfo*>::const_iterator I = 666 SubtargetFeatures.find(Def); 667 return I == SubtargetFeatures.end() ? 0 : I->second; 668 } 669 670 RecordKeeper &getRecords() const { 671 return Records; 672 } 673 }; 674 675 } // End anonymous namespace 676 677 void MatchableInfo::dump() { 678 errs() << TheDef->getName() << " -- " << "flattened:\"" << AsmString <<"\"\n"; 679 680 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) { 681 AsmOperand &Op = AsmOperands[i]; 682 errs() << " op[" << i << "] = " << Op.Class->ClassName << " - "; 683 errs() << '\"' << Op.Token << "\"\n"; 684 } 685 } 686 687 static std::pair<StringRef, StringRef> 688 parseTwoOperandConstraint(StringRef S, ArrayRef<SMLoc> Loc) { 689 // Split via the '='. 690 std::pair<StringRef, StringRef> Ops = S.split('='); 691 if (Ops.second == "") 692 PrintFatalError(Loc, "missing '=' in two-operand alias constraint"); 693 // Trim whitespace and the leading '$' on the operand names. 694 size_t start = Ops.first.find_first_of('$'); 695 if (start == std::string::npos) 696 PrintFatalError(Loc, "expected '$' prefix on asm operand name"); 697 Ops.first = Ops.first.slice(start + 1, std::string::npos); 698 size_t end = Ops.first.find_last_of(" \t"); 699 Ops.first = Ops.first.slice(0, end); 700 // Now the second operand. 701 start = Ops.second.find_first_of('$'); 702 if (start == std::string::npos) 703 PrintFatalError(Loc, "expected '$' prefix on asm operand name"); 704 Ops.second = Ops.second.slice(start + 1, std::string::npos); 705 end = Ops.second.find_last_of(" \t"); 706 Ops.first = Ops.first.slice(0, end); 707 return Ops; 708 } 709 710 void MatchableInfo::formTwoOperandAlias(StringRef Constraint) { 711 // Figure out which operands are aliased and mark them as tied. 712 std::pair<StringRef, StringRef> Ops = 713 parseTwoOperandConstraint(Constraint, TheDef->getLoc()); 714 715 // Find the AsmOperands that refer to the operands we're aliasing. 716 int SrcAsmOperand = findAsmOperandNamed(Ops.first); 717 int DstAsmOperand = findAsmOperandNamed(Ops.second); 718 if (SrcAsmOperand == -1) 719 PrintFatalError(TheDef->getLoc(), 720 "unknown source two-operand alias operand '" + 721 Ops.first.str() + "'."); 722 if (DstAsmOperand == -1) 723 PrintFatalError(TheDef->getLoc(), 724 "unknown destination two-operand alias operand '" + 725 Ops.second.str() + "'."); 726 727 // Find the ResOperand that refers to the operand we're aliasing away 728 // and update it to refer to the combined operand instead. 729 for (unsigned i = 0, e = ResOperands.size(); i != e; ++i) { 730 ResOperand &Op = ResOperands[i]; 731 if (Op.Kind == ResOperand::RenderAsmOperand && 732 Op.AsmOperandNum == (unsigned)SrcAsmOperand) { 733 Op.AsmOperandNum = DstAsmOperand; 734 break; 735 } 736 } 737 // Remove the AsmOperand for the alias operand. 738 AsmOperands.erase(AsmOperands.begin() + SrcAsmOperand); 739 // Adjust the ResOperand references to any AsmOperands that followed 740 // the one we just deleted. 741 for (unsigned i = 0, e = ResOperands.size(); i != e; ++i) { 742 ResOperand &Op = ResOperands[i]; 743 switch(Op.Kind) { 744 default: 745 // Nothing to do for operands that don't reference AsmOperands. 746 break; 747 case ResOperand::RenderAsmOperand: 748 if (Op.AsmOperandNum > (unsigned)SrcAsmOperand) 749 --Op.AsmOperandNum; 750 break; 751 case ResOperand::TiedOperand: 752 if (Op.TiedOperandNum > (unsigned)SrcAsmOperand) 753 --Op.TiedOperandNum; 754 break; 755 } 756 } 757 } 758 759 void MatchableInfo::initialize(const AsmMatcherInfo &Info, 760 SmallPtrSet<Record*, 16> &SingletonRegisters, 761 int AsmVariantNo, std::string &RegisterPrefix) { 762 AsmVariantID = AsmVariantNo; 763 AsmString = 764 CodeGenInstruction::FlattenAsmStringVariants(AsmString, AsmVariantNo); 765 766 tokenizeAsmString(Info); 767 768 // Compute the require features. 769 std::vector<Record*> Predicates =TheDef->getValueAsListOfDefs("Predicates"); 770 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) 771 if (SubtargetFeatureInfo *Feature = 772 Info.getSubtargetFeature(Predicates[i])) 773 RequiredFeatures.push_back(Feature); 774 775 // Collect singleton registers, if used. 776 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) { 777 extractSingletonRegisterForAsmOperand(i, Info, RegisterPrefix); 778 if (Record *Reg = AsmOperands[i].SingletonReg) 779 SingletonRegisters.insert(Reg); 780 } 781 } 782 783 /// tokenizeAsmString - Tokenize a simplified assembly string. 784 void MatchableInfo::tokenizeAsmString(const AsmMatcherInfo &Info) { 785 StringRef String = AsmString; 786 unsigned Prev = 0; 787 bool InTok = true; 788 for (unsigned i = 0, e = String.size(); i != e; ++i) { 789 switch (String[i]) { 790 case '[': 791 case ']': 792 case '*': 793 case '!': 794 case ' ': 795 case '\t': 796 case ',': 797 if (InTok) { 798 AsmOperands.push_back(AsmOperand(String.slice(Prev, i))); 799 InTok = false; 800 } 801 if (!isspace(String[i]) && String[i] != ',') 802 AsmOperands.push_back(AsmOperand(String.substr(i, 1))); 803 Prev = i + 1; 804 break; 805 806 case '\\': 807 if (InTok) { 808 AsmOperands.push_back(AsmOperand(String.slice(Prev, i))); 809 InTok = false; 810 } 811 ++i; 812 assert(i != String.size() && "Invalid quoted character"); 813 AsmOperands.push_back(AsmOperand(String.substr(i, 1))); 814 Prev = i + 1; 815 break; 816 817 case '$': { 818 if (InTok) { 819 AsmOperands.push_back(AsmOperand(String.slice(Prev, i))); 820 InTok = false; 821 } 822 823 // If this isn't "${", treat like a normal token. 824 if (i + 1 == String.size() || String[i + 1] != '{') { 825 Prev = i; 826 break; 827 } 828 829 StringRef::iterator End = std::find(String.begin() + i, String.end(),'}'); 830 assert(End != String.end() && "Missing brace in operand reference!"); 831 size_t EndPos = End - String.begin(); 832 AsmOperands.push_back(AsmOperand(String.slice(i, EndPos+1))); 833 Prev = EndPos + 1; 834 i = EndPos; 835 break; 836 } 837 838 case '.': 839 if (InTok) 840 AsmOperands.push_back(AsmOperand(String.slice(Prev, i))); 841 Prev = i; 842 InTok = true; 843 break; 844 845 default: 846 InTok = true; 847 } 848 } 849 if (InTok && Prev != String.size()) 850 AsmOperands.push_back(AsmOperand(String.substr(Prev))); 851 852 // The first token of the instruction is the mnemonic, which must be a 853 // simple string, not a $foo variable or a singleton register. 854 if (AsmOperands.empty()) 855 PrintFatalError(TheDef->getLoc(), 856 "Instruction '" + TheDef->getName() + "' has no tokens"); 857 Mnemonic = AsmOperands[0].Token; 858 if (Mnemonic.empty()) 859 PrintFatalError(TheDef->getLoc(), 860 "Missing instruction mnemonic"); 861 // FIXME : Check and raise an error if it is a register. 862 if (Mnemonic[0] == '$') 863 PrintFatalError(TheDef->getLoc(), 864 "Invalid instruction mnemonic '" + Mnemonic.str() + "'!"); 865 866 // Remove the first operand, it is tracked in the mnemonic field. 867 AsmOperands.erase(AsmOperands.begin()); 868 } 869 870 bool MatchableInfo::validate(StringRef CommentDelimiter, bool Hack) const { 871 // Reject matchables with no .s string. 872 if (AsmString.empty()) 873 PrintFatalError(TheDef->getLoc(), "instruction with empty asm string"); 874 875 // Reject any matchables with a newline in them, they should be marked 876 // isCodeGenOnly if they are pseudo instructions. 877 if (AsmString.find('\n') != std::string::npos) 878 PrintFatalError(TheDef->getLoc(), 879 "multiline instruction is not valid for the asmparser, " 880 "mark it isCodeGenOnly"); 881 882 // Remove comments from the asm string. We know that the asmstring only 883 // has one line. 884 if (!CommentDelimiter.empty() && 885 StringRef(AsmString).find(CommentDelimiter) != StringRef::npos) 886 PrintFatalError(TheDef->getLoc(), 887 "asmstring for instruction has comment character in it, " 888 "mark it isCodeGenOnly"); 889 890 // Reject matchables with operand modifiers, these aren't something we can 891 // handle, the target should be refactored to use operands instead of 892 // modifiers. 893 // 894 // Also, check for instructions which reference the operand multiple times; 895 // this implies a constraint we would not honor. 896 std::set<std::string> OperandNames; 897 for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) { 898 StringRef Tok = AsmOperands[i].Token; 899 if (Tok[0] == '$' && Tok.find(':') != StringRef::npos) 900 PrintFatalError(TheDef->getLoc(), 901 "matchable with operand modifier '" + Tok.str() + 902 "' not supported by asm matcher. Mark isCodeGenOnly!"); 903 904 // Verify that any operand is only mentioned once. 905 // We reject aliases and ignore instructions for now. 906 if (Tok[0] == '$' && !OperandNames.insert(Tok).second) { 907 if (!Hack) 908 PrintFatalError(TheDef->getLoc(), 909 "ERROR: matchable with tied operand '" + Tok.str() + 910 "' can never be matched!"); 911 // FIXME: Should reject these. The ARM backend hits this with $lane in a 912 // bunch of instructions. It is unclear what the right answer is. 913 DEBUG({ 914 errs() << "warning: '" << TheDef->getName() << "': " 915 << "ignoring instruction with tied operand '" 916 << Tok.str() << "'\n"; 917 }); 918 return false; 919 } 920 } 921 922 return true; 923 } 924 925 /// extractSingletonRegisterForAsmOperand - Extract singleton register, 926 /// if present, from specified token. 927 void MatchableInfo:: 928 extractSingletonRegisterForAsmOperand(unsigned OperandNo, 929 const AsmMatcherInfo &Info, 930 std::string &RegisterPrefix) { 931 StringRef Tok = AsmOperands[OperandNo].Token; 932 if (RegisterPrefix.empty()) { 933 std::string LoweredTok = Tok.lower(); 934 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(LoweredTok)) 935 AsmOperands[OperandNo].SingletonReg = Reg->TheDef; 936 return; 937 } 938 939 if (!Tok.startswith(RegisterPrefix)) 940 return; 941 942 StringRef RegName = Tok.substr(RegisterPrefix.size()); 943 if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(RegName)) 944 AsmOperands[OperandNo].SingletonReg = Reg->TheDef; 945 946 // If there is no register prefix (i.e. "%" in "%eax"), then this may 947 // be some random non-register token, just ignore it. 948 return; 949 } 950 951 static std::string getEnumNameForToken(StringRef Str) { 952 std::string Res; 953 954 for (StringRef::iterator it = Str.begin(), ie = Str.end(); it != ie; ++it) { 955 switch (*it) { 956 case '*': Res += "_STAR_"; break; 957 case '%': Res += "_PCT_"; break; 958 case ':': Res += "_COLON_"; break; 959 case '!': Res += "_EXCLAIM_"; break; 960 case '.': Res += "_DOT_"; break; 961 case '<': Res += "_LT_"; break; 962 case '>': Res += "_GT_"; break; 963 default: 964 if ((*it >= 'A' && *it <= 'Z') || 965 (*it >= 'a' && *it <= 'z') || 966 (*it >= '0' && *it <= '9')) 967 Res += *it; 968 else 969 Res += "_" + utostr((unsigned) *it) + "_"; 970 } 971 } 972 973 return Res; 974 } 975 976 ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) { 977 ClassInfo *&Entry = TokenClasses[Token]; 978 979 if (!Entry) { 980 Entry = new ClassInfo(); 981 Entry->Kind = ClassInfo::Token; 982 Entry->ClassName = "Token"; 983 Entry->Name = "MCK_" + getEnumNameForToken(Token); 984 Entry->ValueName = Token; 985 Entry->PredicateMethod = "<invalid>"; 986 Entry->RenderMethod = "<invalid>"; 987 Entry->ParserMethod = ""; 988 Entry->DiagnosticType = ""; 989 Classes.push_back(Entry); 990 } 991 992 return Entry; 993 } 994 995 ClassInfo * 996 AsmMatcherInfo::getOperandClass(const CGIOperandList::OperandInfo &OI, 997 int SubOpIdx) { 998 Record *Rec = OI.Rec; 999 if (SubOpIdx != -1) 1000 Rec = cast<DefInit>(OI.MIOperandInfo->getArg(SubOpIdx))->getDef(); 1001 return getOperandClass(Rec, SubOpIdx); 1002 } 1003 1004 ClassInfo * 1005 AsmMatcherInfo::getOperandClass(Record *Rec, int SubOpIdx) { 1006 if (Rec->isSubClassOf("RegisterOperand")) { 1007 // RegisterOperand may have an associated ParserMatchClass. If it does, 1008 // use it, else just fall back to the underlying register class. 1009 const RecordVal *R = Rec->getValue("ParserMatchClass"); 1010 if (R == 0 || R->getValue() == 0) 1011 PrintFatalError("Record `" + Rec->getName() + 1012 "' does not have a ParserMatchClass!\n"); 1013 1014 if (DefInit *DI= dyn_cast<DefInit>(R->getValue())) { 1015 Record *MatchClass = DI->getDef(); 1016 if (ClassInfo *CI = AsmOperandClasses[MatchClass]) 1017 return CI; 1018 } 1019 1020 // No custom match class. Just use the register class. 1021 Record *ClassRec = Rec->getValueAsDef("RegClass"); 1022 if (!ClassRec) 1023 PrintFatalError(Rec->getLoc(), "RegisterOperand `" + Rec->getName() + 1024 "' has no associated register class!\n"); 1025 if (ClassInfo *CI = RegisterClassClasses[ClassRec]) 1026 return CI; 1027 PrintFatalError(Rec->getLoc(), "register class has no class info!"); 1028 } 1029 1030 1031 if (Rec->isSubClassOf("RegisterClass")) { 1032 if (ClassInfo *CI = RegisterClassClasses[Rec]) 1033 return CI; 1034 PrintFatalError(Rec->getLoc(), "register class has no class info!"); 1035 } 1036 1037 if (!Rec->isSubClassOf("Operand")) 1038 PrintFatalError(Rec->getLoc(), "Operand `" + Rec->getName() + 1039 "' does not derive from class Operand!\n"); 1040 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass"); 1041 if (ClassInfo *CI = AsmOperandClasses[MatchClass]) 1042 return CI; 1043 1044 PrintFatalError(Rec->getLoc(), "operand has no match class!"); 1045 } 1046 1047 void AsmMatcherInfo:: 1048 buildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters) { 1049 const std::vector<CodeGenRegister*> &Registers = 1050 Target.getRegBank().getRegisters(); 1051 ArrayRef<CodeGenRegisterClass*> RegClassList = 1052 Target.getRegBank().getRegClasses(); 1053 1054 // The register sets used for matching. 1055 std::set< std::set<Record*> > RegisterSets; 1056 1057 // Gather the defined sets. 1058 for (ArrayRef<CodeGenRegisterClass*>::const_iterator it = 1059 RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it) 1060 RegisterSets.insert(std::set<Record*>( 1061 (*it)->getOrder().begin(), (*it)->getOrder().end())); 1062 1063 // Add any required singleton sets. 1064 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(), 1065 ie = SingletonRegisters.end(); it != ie; ++it) { 1066 Record *Rec = *it; 1067 RegisterSets.insert(std::set<Record*>(&Rec, &Rec + 1)); 1068 } 1069 1070 // Introduce derived sets where necessary (when a register does not determine 1071 // a unique register set class), and build the mapping of registers to the set 1072 // they should classify to. 1073 std::map<Record*, std::set<Record*> > RegisterMap; 1074 for (std::vector<CodeGenRegister*>::const_iterator it = Registers.begin(), 1075 ie = Registers.end(); it != ie; ++it) { 1076 const CodeGenRegister &CGR = **it; 1077 // Compute the intersection of all sets containing this register. 1078 std::set<Record*> ContainingSet; 1079 1080 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(), 1081 ie = RegisterSets.end(); it != ie; ++it) { 1082 if (!it->count(CGR.TheDef)) 1083 continue; 1084 1085 if (ContainingSet.empty()) { 1086 ContainingSet = *it; 1087 continue; 1088 } 1089 1090 std::set<Record*> Tmp; 1091 std::swap(Tmp, ContainingSet); 1092 std::insert_iterator< std::set<Record*> > II(ContainingSet, 1093 ContainingSet.begin()); 1094 std::set_intersection(Tmp.begin(), Tmp.end(), it->begin(), it->end(), II); 1095 } 1096 1097 if (!ContainingSet.empty()) { 1098 RegisterSets.insert(ContainingSet); 1099 RegisterMap.insert(std::make_pair(CGR.TheDef, ContainingSet)); 1100 } 1101 } 1102 1103 // Construct the register classes. 1104 std::map<std::set<Record*>, ClassInfo*> RegisterSetClasses; 1105 unsigned Index = 0; 1106 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(), 1107 ie = RegisterSets.end(); it != ie; ++it, ++Index) { 1108 ClassInfo *CI = new ClassInfo(); 1109 CI->Kind = ClassInfo::RegisterClass0 + Index; 1110 CI->ClassName = "Reg" + utostr(Index); 1111 CI->Name = "MCK_Reg" + utostr(Index); 1112 CI->ValueName = ""; 1113 CI->PredicateMethod = ""; // unused 1114 CI->RenderMethod = "addRegOperands"; 1115 CI->Registers = *it; 1116 // FIXME: diagnostic type. 1117 CI->DiagnosticType = ""; 1118 Classes.push_back(CI); 1119 RegisterSetClasses.insert(std::make_pair(*it, CI)); 1120 } 1121 1122 // Find the superclasses; we could compute only the subgroup lattice edges, 1123 // but there isn't really a point. 1124 for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(), 1125 ie = RegisterSets.end(); it != ie; ++it) { 1126 ClassInfo *CI = RegisterSetClasses[*it]; 1127 for (std::set< std::set<Record*> >::iterator it2 = RegisterSets.begin(), 1128 ie2 = RegisterSets.end(); it2 != ie2; ++it2) 1129 if (*it != *it2 && 1130 std::includes(it2->begin(), it2->end(), it->begin(), it->end())) 1131 CI->SuperClasses.push_back(RegisterSetClasses[*it2]); 1132 } 1133 1134 // Name the register classes which correspond to a user defined RegisterClass. 1135 for (ArrayRef<CodeGenRegisterClass*>::const_iterator 1136 it = RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it) { 1137 const CodeGenRegisterClass &RC = **it; 1138 // Def will be NULL for non-user defined register classes. 1139 Record *Def = RC.getDef(); 1140 if (!Def) 1141 continue; 1142 ClassInfo *CI = RegisterSetClasses[std::set<Record*>(RC.getOrder().begin(), 1143 RC.getOrder().end())]; 1144 if (CI->ValueName.empty()) { 1145 CI->ClassName = RC.getName(); 1146 CI->Name = "MCK_" + RC.getName(); 1147 CI->ValueName = RC.getName(); 1148 } else 1149 CI->ValueName = CI->ValueName + "," + RC.getName(); 1150 1151 RegisterClassClasses.insert(std::make_pair(Def, CI)); 1152 } 1153 1154 // Populate the map for individual registers. 1155 for (std::map<Record*, std::set<Record*> >::iterator it = RegisterMap.begin(), 1156 ie = RegisterMap.end(); it != ie; ++it) 1157 RegisterClasses[it->first] = RegisterSetClasses[it->second]; 1158 1159 // Name the register classes which correspond to singleton registers. 1160 for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(), 1161 ie = SingletonRegisters.end(); it != ie; ++it) { 1162 Record *Rec = *it; 1163 ClassInfo *CI = RegisterClasses[Rec]; 1164 assert(CI && "Missing singleton register class info!"); 1165 1166 if (CI->ValueName.empty()) { 1167 CI->ClassName = Rec->getName(); 1168 CI->Name = "MCK_" + Rec->getName(); 1169 CI->ValueName = Rec->getName(); 1170 } else 1171 CI->ValueName = CI->ValueName + "," + Rec->getName(); 1172 } 1173 } 1174 1175 void AsmMatcherInfo::buildOperandClasses() { 1176 std::vector<Record*> AsmOperands = 1177 Records.getAllDerivedDefinitions("AsmOperandClass"); 1178 1179 // Pre-populate AsmOperandClasses map. 1180 for (std::vector<Record*>::iterator it = AsmOperands.begin(), 1181 ie = AsmOperands.end(); it != ie; ++it) 1182 AsmOperandClasses[*it] = new ClassInfo(); 1183 1184 unsigned Index = 0; 1185 for (std::vector<Record*>::iterator it = AsmOperands.begin(), 1186 ie = AsmOperands.end(); it != ie; ++it, ++Index) { 1187 ClassInfo *CI = AsmOperandClasses[*it]; 1188 CI->Kind = ClassInfo::UserClass0 + Index; 1189 1190 ListInit *Supers = (*it)->getValueAsListInit("SuperClasses"); 1191 for (unsigned i = 0, e = Supers->getSize(); i != e; ++i) { 1192 DefInit *DI = dyn_cast<DefInit>(Supers->getElement(i)); 1193 if (!DI) { 1194 PrintError((*it)->getLoc(), "Invalid super class reference!"); 1195 continue; 1196 } 1197 1198 ClassInfo *SC = AsmOperandClasses[DI->getDef()]; 1199 if (!SC) 1200 PrintError((*it)->getLoc(), "Invalid super class reference!"); 1201 else 1202 CI->SuperClasses.push_back(SC); 1203 } 1204 CI->ClassName = (*it)->getValueAsString("Name"); 1205 CI->Name = "MCK_" + CI->ClassName; 1206 CI->ValueName = (*it)->getName(); 1207 1208 // Get or construct the predicate method name. 1209 Init *PMName = (*it)->getValueInit("PredicateMethod"); 1210 if (StringInit *SI = dyn_cast<StringInit>(PMName)) { 1211 CI->PredicateMethod = SI->getValue(); 1212 } else { 1213 assert(isa<UnsetInit>(PMName) && "Unexpected PredicateMethod field!"); 1214 CI->PredicateMethod = "is" + CI->ClassName; 1215 } 1216 1217 // Get or construct the render method name. 1218 Init *RMName = (*it)->getValueInit("RenderMethod"); 1219 if (StringInit *SI = dyn_cast<StringInit>(RMName)) { 1220 CI->RenderMethod = SI->getValue(); 1221 } else { 1222 assert(isa<UnsetInit>(RMName) && "Unexpected RenderMethod field!"); 1223 CI->RenderMethod = "add" + CI->ClassName + "Operands"; 1224 } 1225 1226 // Get the parse method name or leave it as empty. 1227 Init *PRMName = (*it)->getValueInit("ParserMethod"); 1228 if (StringInit *SI = dyn_cast<StringInit>(PRMName)) 1229 CI->ParserMethod = SI->getValue(); 1230 1231 // Get the diagnostic type or leave it as empty. 1232 // Get the parse method name or leave it as empty. 1233 Init *DiagnosticType = (*it)->getValueInit("DiagnosticType"); 1234 if (StringInit *SI = dyn_cast<StringInit>(DiagnosticType)) 1235 CI->DiagnosticType = SI->getValue(); 1236 1237 AsmOperandClasses[*it] = CI; 1238 Classes.push_back(CI); 1239 } 1240 } 1241 1242 AsmMatcherInfo::AsmMatcherInfo(Record *asmParser, 1243 CodeGenTarget &target, 1244 RecordKeeper &records) 1245 : Records(records), AsmParser(asmParser), Target(target) { 1246 } 1247 1248 /// buildOperandMatchInfo - Build the necessary information to handle user 1249 /// defined operand parsing methods. 1250 void AsmMatcherInfo::buildOperandMatchInfo() { 1251 1252 /// Map containing a mask with all operands indices that can be found for 1253 /// that class inside a instruction. 1254 typedef std::map<ClassInfo*, unsigned, LessClassInfoPtr> OpClassMaskTy; 1255 OpClassMaskTy OpClassMask; 1256 1257 for (std::vector<MatchableInfo*>::const_iterator it = 1258 Matchables.begin(), ie = Matchables.end(); 1259 it != ie; ++it) { 1260 MatchableInfo &II = **it; 1261 OpClassMask.clear(); 1262 1263 // Keep track of all operands of this instructions which belong to the 1264 // same class. 1265 for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) { 1266 MatchableInfo::AsmOperand &Op = II.AsmOperands[i]; 1267 if (Op.Class->ParserMethod.empty()) 1268 continue; 1269 unsigned &OperandMask = OpClassMask[Op.Class]; 1270 OperandMask |= (1 << i); 1271 } 1272 1273 // Generate operand match info for each mnemonic/operand class pair. 1274 for (OpClassMaskTy::iterator iit = OpClassMask.begin(), 1275 iie = OpClassMask.end(); iit != iie; ++iit) { 1276 unsigned OpMask = iit->second; 1277 ClassInfo *CI = iit->first; 1278 OperandMatchInfo.push_back(OperandMatchEntry::create(&II, CI, OpMask)); 1279 } 1280 } 1281 } 1282 1283 void AsmMatcherInfo::buildInfo() { 1284 // Build information about all of the AssemblerPredicates. 1285 std::vector<Record*> AllPredicates = 1286 Records.getAllDerivedDefinitions("Predicate"); 1287 for (unsigned i = 0, e = AllPredicates.size(); i != e; ++i) { 1288 Record *Pred = AllPredicates[i]; 1289 // Ignore predicates that are not intended for the assembler. 1290 if (!Pred->getValueAsBit("AssemblerMatcherPredicate")) 1291 continue; 1292 1293 if (Pred->getName().empty()) 1294 PrintFatalError(Pred->getLoc(), "Predicate has no name!"); 1295 1296 unsigned FeatureNo = SubtargetFeatures.size(); 1297 SubtargetFeatures[Pred] = new SubtargetFeatureInfo(Pred, FeatureNo); 1298 assert(FeatureNo < 32 && "Too many subtarget features!"); 1299 } 1300 1301 // Parse the instructions; we need to do this first so that we can gather the 1302 // singleton register classes. 1303 SmallPtrSet<Record*, 16> SingletonRegisters; 1304 unsigned VariantCount = Target.getAsmParserVariantCount(); 1305 for (unsigned VC = 0; VC != VariantCount; ++VC) { 1306 Record *AsmVariant = Target.getAsmParserVariant(VC); 1307 std::string CommentDelimiter = 1308 AsmVariant->getValueAsString("CommentDelimiter"); 1309 std::string RegisterPrefix = AsmVariant->getValueAsString("RegisterPrefix"); 1310 int AsmVariantNo = AsmVariant->getValueAsInt("Variant"); 1311 1312 for (CodeGenTarget::inst_iterator I = Target.inst_begin(), 1313 E = Target.inst_end(); I != E; ++I) { 1314 const CodeGenInstruction &CGI = **I; 1315 1316 // If the tblgen -match-prefix option is specified (for tblgen hackers), 1317 // filter the set of instructions we consider. 1318 if (!StringRef(CGI.TheDef->getName()).startswith(MatchPrefix)) 1319 continue; 1320 1321 // Ignore "codegen only" instructions. 1322 if (CGI.TheDef->getValueAsBit("isCodeGenOnly")) 1323 continue; 1324 1325 // Validate the operand list to ensure we can handle this instruction. 1326 for (unsigned i = 0, e = CGI.Operands.size(); i != e; ++i) { 1327 const CGIOperandList::OperandInfo &OI = CGI.Operands[i]; 1328 1329 // Validate tied operands. 1330 if (OI.getTiedRegister() != -1) { 1331 // If we have a tied operand that consists of multiple MCOperands, 1332 // reject it. We reject aliases and ignore instructions for now. 1333 if (OI.MINumOperands != 1) { 1334 // FIXME: Should reject these. The ARM backend hits this with $lane 1335 // in a bunch of instructions. The right answer is unclear. 1336 DEBUG({ 1337 errs() << "warning: '" << CGI.TheDef->getName() << "': " 1338 << "ignoring instruction with multi-operand tied operand '" 1339 << OI.Name << "'\n"; 1340 }); 1341 continue; 1342 } 1343 } 1344 } 1345 1346 OwningPtr<MatchableInfo> II(new MatchableInfo(CGI)); 1347 1348 II->initialize(*this, SingletonRegisters, AsmVariantNo, RegisterPrefix); 1349 1350 // Ignore instructions which shouldn't be matched and diagnose invalid 1351 // instruction definitions with an error. 1352 if (!II->validate(CommentDelimiter, true)) 1353 continue; 1354 1355 // Ignore "Int_*" and "*_Int" instructions, which are internal aliases. 1356 // 1357 // FIXME: This is a total hack. 1358 if (StringRef(II->TheDef->getName()).startswith("Int_") || 1359 StringRef(II->TheDef->getName()).endswith("_Int")) 1360 continue; 1361 1362 Matchables.push_back(II.take()); 1363 } 1364 1365 // Parse all of the InstAlias definitions and stick them in the list of 1366 // matchables. 1367 std::vector<Record*> AllInstAliases = 1368 Records.getAllDerivedDefinitions("InstAlias"); 1369 for (unsigned i = 0, e = AllInstAliases.size(); i != e; ++i) { 1370 CodeGenInstAlias *Alias = new CodeGenInstAlias(AllInstAliases[i], Target); 1371 1372 // If the tblgen -match-prefix option is specified (for tblgen hackers), 1373 // filter the set of instruction aliases we consider, based on the target 1374 // instruction. 1375 if (!StringRef(Alias->ResultInst->TheDef->getName()) 1376 .startswith( MatchPrefix)) 1377 continue; 1378 1379 OwningPtr<MatchableInfo> II(new MatchableInfo(Alias)); 1380 1381 II->initialize(*this, SingletonRegisters, AsmVariantNo, RegisterPrefix); 1382 1383 // Validate the alias definitions. 1384 II->validate(CommentDelimiter, false); 1385 1386 Matchables.push_back(II.take()); 1387 } 1388 } 1389 1390 // Build info for the register classes. 1391 buildRegisterClasses(SingletonRegisters); 1392 1393 // Build info for the user defined assembly operand classes. 1394 buildOperandClasses(); 1395 1396 // Build the information about matchables, now that we have fully formed 1397 // classes. 1398 std::vector<MatchableInfo*> NewMatchables; 1399 for (std::vector<MatchableInfo*>::iterator it = Matchables.begin(), 1400 ie = Matchables.end(); it != ie; ++it) { 1401 MatchableInfo *II = *it; 1402 1403 // Parse the tokens after the mnemonic. 1404 // Note: buildInstructionOperandReference may insert new AsmOperands, so 1405 // don't precompute the loop bound. 1406 for (unsigned i = 0; i != II->AsmOperands.size(); ++i) { 1407 MatchableInfo::AsmOperand &Op = II->AsmOperands[i]; 1408 StringRef Token = Op.Token; 1409 1410 // Check for singleton registers. 1411 if (Record *RegRecord = II->AsmOperands[i].SingletonReg) { 1412 Op.Class = RegisterClasses[RegRecord]; 1413 assert(Op.Class && Op.Class->Registers.size() == 1 && 1414 "Unexpected class for singleton register"); 1415 continue; 1416 } 1417 1418 // Check for simple tokens. 1419 if (Token[0] != '$') { 1420 Op.Class = getTokenClass(Token); 1421 continue; 1422 } 1423 1424 if (Token.size() > 1 && isdigit(Token[1])) { 1425 Op.Class = getTokenClass(Token); 1426 continue; 1427 } 1428 1429 // Otherwise this is an operand reference. 1430 StringRef OperandName; 1431 if (Token[1] == '{') 1432 OperandName = Token.substr(2, Token.size() - 3); 1433 else 1434 OperandName = Token.substr(1); 1435 1436 if (II->DefRec.is<const CodeGenInstruction*>()) 1437 buildInstructionOperandReference(II, OperandName, i); 1438 else 1439 buildAliasOperandReference(II, OperandName, Op); 1440 } 1441 1442 if (II->DefRec.is<const CodeGenInstruction*>()) { 1443 II->buildInstructionResultOperands(); 1444 // If the instruction has a two-operand alias, build up the 1445 // matchable here. We'll add them in bulk at the end to avoid 1446 // confusing this loop. 1447 std::string Constraint = 1448 II->TheDef->getValueAsString("TwoOperandAliasConstraint"); 1449 if (Constraint != "") { 1450 // Start by making a copy of the original matchable. 1451 OwningPtr<MatchableInfo> AliasII(new MatchableInfo(*II)); 1452 1453 // Adjust it to be a two-operand alias. 1454 AliasII->formTwoOperandAlias(Constraint); 1455 1456 // Add the alias to the matchables list. 1457 NewMatchables.push_back(AliasII.take()); 1458 } 1459 } else 1460 II->buildAliasResultOperands(); 1461 } 1462 if (!NewMatchables.empty()) 1463 Matchables.insert(Matchables.end(), NewMatchables.begin(), 1464 NewMatchables.end()); 1465 1466 // Process token alias definitions and set up the associated superclass 1467 // information. 1468 std::vector<Record*> AllTokenAliases = 1469 Records.getAllDerivedDefinitions("TokenAlias"); 1470 for (unsigned i = 0, e = AllTokenAliases.size(); i != e; ++i) { 1471 Record *Rec = AllTokenAliases[i]; 1472 ClassInfo *FromClass = getTokenClass(Rec->getValueAsString("FromToken")); 1473 ClassInfo *ToClass = getTokenClass(Rec->getValueAsString("ToToken")); 1474 if (FromClass == ToClass) 1475 PrintFatalError(Rec->getLoc(), 1476 "error: Destination value identical to source value."); 1477 FromClass->SuperClasses.push_back(ToClass); 1478 } 1479 1480 // Reorder classes so that classes precede super classes. 1481 std::sort(Classes.begin(), Classes.end(), less_ptr<ClassInfo>()); 1482 } 1483 1484 /// buildInstructionOperandReference - The specified operand is a reference to a 1485 /// named operand such as $src. Resolve the Class and OperandInfo pointers. 1486 void AsmMatcherInfo:: 1487 buildInstructionOperandReference(MatchableInfo *II, 1488 StringRef OperandName, 1489 unsigned AsmOpIdx) { 1490 const CodeGenInstruction &CGI = *II->DefRec.get<const CodeGenInstruction*>(); 1491 const CGIOperandList &Operands = CGI.Operands; 1492 MatchableInfo::AsmOperand *Op = &II->AsmOperands[AsmOpIdx]; 1493 1494 // Map this token to an operand. 1495 unsigned Idx; 1496 if (!Operands.hasOperandNamed(OperandName, Idx)) 1497 PrintFatalError(II->TheDef->getLoc(), "error: unable to find operand: '" + 1498 OperandName.str() + "'"); 1499 1500 // If the instruction operand has multiple suboperands, but the parser 1501 // match class for the asm operand is still the default "ImmAsmOperand", 1502 // then handle each suboperand separately. 1503 if (Op->SubOpIdx == -1 && Operands[Idx].MINumOperands > 1) { 1504 Record *Rec = Operands[Idx].Rec; 1505 assert(Rec->isSubClassOf("Operand") && "Unexpected operand!"); 1506 Record *MatchClass = Rec->getValueAsDef("ParserMatchClass"); 1507 if (MatchClass && MatchClass->getValueAsString("Name") == "Imm") { 1508 // Insert remaining suboperands after AsmOpIdx in II->AsmOperands. 1509 StringRef Token = Op->Token; // save this in case Op gets moved 1510 for (unsigned SI = 1, SE = Operands[Idx].MINumOperands; SI != SE; ++SI) { 1511 MatchableInfo::AsmOperand NewAsmOp(Token); 1512 NewAsmOp.SubOpIdx = SI; 1513 II->AsmOperands.insert(II->AsmOperands.begin()+AsmOpIdx+SI, NewAsmOp); 1514 } 1515 // Replace Op with first suboperand. 1516 Op = &II->AsmOperands[AsmOpIdx]; // update the pointer in case it moved 1517 Op->SubOpIdx = 0; 1518 } 1519 } 1520 1521 // Set up the operand class. 1522 Op->Class = getOperandClass(Operands[Idx], Op->SubOpIdx); 1523 1524 // If the named operand is tied, canonicalize it to the untied operand. 1525 // For example, something like: 1526 // (outs GPR:$dst), (ins GPR:$src) 1527 // with an asmstring of 1528 // "inc $src" 1529 // we want to canonicalize to: 1530 // "inc $dst" 1531 // so that we know how to provide the $dst operand when filling in the result. 1532 int OITied = Operands[Idx].getTiedRegister(); 1533 if (OITied != -1) { 1534 // The tied operand index is an MIOperand index, find the operand that 1535 // contains it. 1536 std::pair<unsigned, unsigned> Idx = Operands.getSubOperandNumber(OITied); 1537 OperandName = Operands[Idx.first].Name; 1538 Op->SubOpIdx = Idx.second; 1539 } 1540 1541 Op->SrcOpName = OperandName; 1542 } 1543 1544 /// buildAliasOperandReference - When parsing an operand reference out of the 1545 /// matching string (e.g. "movsx $src, $dst"), determine what the class of the 1546 /// operand reference is by looking it up in the result pattern definition. 1547 void AsmMatcherInfo::buildAliasOperandReference(MatchableInfo *II, 1548 StringRef OperandName, 1549 MatchableInfo::AsmOperand &Op) { 1550 const CodeGenInstAlias &CGA = *II->DefRec.get<const CodeGenInstAlias*>(); 1551 1552 // Set up the operand class. 1553 for (unsigned i = 0, e = CGA.ResultOperands.size(); i != e; ++i) 1554 if (CGA.ResultOperands[i].isRecord() && 1555 CGA.ResultOperands[i].getName() == OperandName) { 1556 // It's safe to go with the first one we find, because CodeGenInstAlias 1557 // validates that all operands with the same name have the same record. 1558 Op.SubOpIdx = CGA.ResultInstOperandIndex[i].second; 1559 // Use the match class from the Alias definition, not the 1560 // destination instruction, as we may have an immediate that's 1561 // being munged by the match class. 1562 Op.Class = getOperandClass(CGA.ResultOperands[i].getRecord(), 1563 Op.SubOpIdx); 1564 Op.SrcOpName = OperandName; 1565 return; 1566 } 1567 1568 PrintFatalError(II->TheDef->getLoc(), "error: unable to find operand: '" + 1569 OperandName.str() + "'"); 1570 } 1571 1572 void MatchableInfo::buildInstructionResultOperands() { 1573 const CodeGenInstruction *ResultInst = getResultInst(); 1574 1575 // Loop over all operands of the result instruction, determining how to 1576 // populate them. 1577 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) { 1578 const CGIOperandList::OperandInfo &OpInfo = ResultInst->Operands[i]; 1579 1580 // If this is a tied operand, just copy from the previously handled operand. 1581 int TiedOp = OpInfo.getTiedRegister(); 1582 if (TiedOp != -1) { 1583 ResOperands.push_back(ResOperand::getTiedOp(TiedOp)); 1584 continue; 1585 } 1586 1587 // Find out what operand from the asmparser this MCInst operand comes from. 1588 int SrcOperand = findAsmOperandNamed(OpInfo.Name); 1589 if (OpInfo.Name.empty() || SrcOperand == -1) 1590 PrintFatalError(TheDef->getLoc(), "Instruction '" + 1591 TheDef->getName() + "' has operand '" + OpInfo.Name + 1592 "' that doesn't appear in asm string!"); 1593 1594 // Check if the one AsmOperand populates the entire operand. 1595 unsigned NumOperands = OpInfo.MINumOperands; 1596 if (AsmOperands[SrcOperand].SubOpIdx == -1) { 1597 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, NumOperands)); 1598 continue; 1599 } 1600 1601 // Add a separate ResOperand for each suboperand. 1602 for (unsigned AI = 0; AI < NumOperands; ++AI) { 1603 assert(AsmOperands[SrcOperand+AI].SubOpIdx == (int)AI && 1604 AsmOperands[SrcOperand+AI].SrcOpName == OpInfo.Name && 1605 "unexpected AsmOperands for suboperands"); 1606 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand + AI, 1)); 1607 } 1608 } 1609 } 1610 1611 void MatchableInfo::buildAliasResultOperands() { 1612 const CodeGenInstAlias &CGA = *DefRec.get<const CodeGenInstAlias*>(); 1613 const CodeGenInstruction *ResultInst = getResultInst(); 1614 1615 // Loop over all operands of the result instruction, determining how to 1616 // populate them. 1617 unsigned AliasOpNo = 0; 1618 unsigned LastOpNo = CGA.ResultInstOperandIndex.size(); 1619 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) { 1620 const CGIOperandList::OperandInfo *OpInfo = &ResultInst->Operands[i]; 1621 1622 // If this is a tied operand, just copy from the previously handled operand. 1623 int TiedOp = OpInfo->getTiedRegister(); 1624 if (TiedOp != -1) { 1625 ResOperands.push_back(ResOperand::getTiedOp(TiedOp)); 1626 continue; 1627 } 1628 1629 // Handle all the suboperands for this operand. 1630 const std::string &OpName = OpInfo->Name; 1631 for ( ; AliasOpNo < LastOpNo && 1632 CGA.ResultInstOperandIndex[AliasOpNo].first == i; ++AliasOpNo) { 1633 int SubIdx = CGA.ResultInstOperandIndex[AliasOpNo].second; 1634 1635 // Find out what operand from the asmparser that this MCInst operand 1636 // comes from. 1637 switch (CGA.ResultOperands[AliasOpNo].Kind) { 1638 case CodeGenInstAlias::ResultOperand::K_Record: { 1639 StringRef Name = CGA.ResultOperands[AliasOpNo].getName(); 1640 int SrcOperand = findAsmOperand(Name, SubIdx); 1641 if (SrcOperand == -1) 1642 PrintFatalError(TheDef->getLoc(), "Instruction '" + 1643 TheDef->getName() + "' has operand '" + OpName + 1644 "' that doesn't appear in asm string!"); 1645 unsigned NumOperands = (SubIdx == -1 ? OpInfo->MINumOperands : 1); 1646 ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, 1647 NumOperands)); 1648 break; 1649 } 1650 case CodeGenInstAlias::ResultOperand::K_Imm: { 1651 int64_t ImmVal = CGA.ResultOperands[AliasOpNo].getImm(); 1652 ResOperands.push_back(ResOperand::getImmOp(ImmVal)); 1653 break; 1654 } 1655 case CodeGenInstAlias::ResultOperand::K_Reg: { 1656 Record *Reg = CGA.ResultOperands[AliasOpNo].getRegister(); 1657 ResOperands.push_back(ResOperand::getRegOp(Reg)); 1658 break; 1659 } 1660 } 1661 } 1662 } 1663 } 1664 1665 static unsigned getConverterOperandID(const std::string &Name, 1666 SetVector<std::string> &Table, 1667 bool &IsNew) { 1668 IsNew = Table.insert(Name); 1669 1670 unsigned ID = IsNew ? Table.size() - 1 : 1671 std::find(Table.begin(), Table.end(), Name) - Table.begin(); 1672 1673 assert(ID < Table.size()); 1674 1675 return ID; 1676 } 1677 1678 1679 static void emitConvertFuncs(CodeGenTarget &Target, StringRef ClassName, 1680 std::vector<MatchableInfo*> &Infos, 1681 raw_ostream &OS) { 1682 SetVector<std::string> OperandConversionKinds; 1683 SetVector<std::string> InstructionConversionKinds; 1684 std::vector<std::vector<uint8_t> > ConversionTable; 1685 size_t MaxRowLength = 2; // minimum is custom converter plus terminator. 1686 1687 // TargetOperandClass - This is the target's operand class, like X86Operand. 1688 std::string TargetOperandClass = Target.getName() + "Operand"; 1689 1690 // Write the convert function to a separate stream, so we can drop it after 1691 // the enum. We'll build up the conversion handlers for the individual 1692 // operand types opportunistically as we encounter them. 1693 std::string ConvertFnBody; 1694 raw_string_ostream CvtOS(ConvertFnBody); 1695 // Start the unified conversion function. 1696 CvtOS << "void " << Target.getName() << ClassName << "::\n" 1697 << "convertToMCInst(unsigned Kind, MCInst &Inst, " 1698 << "unsigned Opcode,\n" 1699 << " const SmallVectorImpl<MCParsedAsmOperand*" 1700 << "> &Operands) {\n" 1701 << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n" 1702 << " const uint8_t *Converter = ConversionTable[Kind];\n" 1703 << " Inst.setOpcode(Opcode);\n" 1704 << " for (const uint8_t *p = Converter; *p; p+= 2) {\n" 1705 << " switch (*p) {\n" 1706 << " default: llvm_unreachable(\"invalid conversion entry!\");\n" 1707 << " case CVT_Reg:\n" 1708 << " static_cast<" << TargetOperandClass 1709 << "*>(Operands[*(p + 1)])->addRegOperands(Inst, 1);\n" 1710 << " break;\n" 1711 << " case CVT_Tied:\n" 1712 << " Inst.addOperand(Inst.getOperand(*(p + 1)));\n" 1713 << " break;\n"; 1714 1715 std::string OperandFnBody; 1716 raw_string_ostream OpOS(OperandFnBody); 1717 // Start the operand number lookup function. 1718 OpOS << "void " << Target.getName() << ClassName << "::\n" 1719 << "convertToMapAndConstraints(unsigned Kind,\n"; 1720 OpOS.indent(27); 1721 OpOS << "const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {\n" 1722 << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n" 1723 << " unsigned NumMCOperands = 0;\n" 1724 << " const uint8_t *Converter = ConversionTable[Kind];\n" 1725 << " for (const uint8_t *p = Converter; *p; p+= 2) {\n" 1726 << " switch (*p) {\n" 1727 << " default: llvm_unreachable(\"invalid conversion entry!\");\n" 1728 << " case CVT_Reg:\n" 1729 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n" 1730 << " Operands[*(p + 1)]->setConstraint(\"r\");\n" 1731 << " ++NumMCOperands;\n" 1732 << " break;\n" 1733 << " case CVT_Tied:\n" 1734 << " ++NumMCOperands;\n" 1735 << " break;\n"; 1736 1737 // Pre-populate the operand conversion kinds with the standard always 1738 // available entries. 1739 OperandConversionKinds.insert("CVT_Done"); 1740 OperandConversionKinds.insert("CVT_Reg"); 1741 OperandConversionKinds.insert("CVT_Tied"); 1742 enum { CVT_Done, CVT_Reg, CVT_Tied }; 1743 1744 for (std::vector<MatchableInfo*>::const_iterator it = Infos.begin(), 1745 ie = Infos.end(); it != ie; ++it) { 1746 MatchableInfo &II = **it; 1747 1748 // Check if we have a custom match function. 1749 std::string AsmMatchConverter = 1750 II.getResultInst()->TheDef->getValueAsString("AsmMatchConverter"); 1751 if (!AsmMatchConverter.empty()) { 1752 std::string Signature = "ConvertCustom_" + AsmMatchConverter; 1753 II.ConversionFnKind = Signature; 1754 1755 // Check if we have already generated this signature. 1756 if (!InstructionConversionKinds.insert(Signature)) 1757 continue; 1758 1759 // Remember this converter for the kind enum. 1760 unsigned KindID = OperandConversionKinds.size(); 1761 OperandConversionKinds.insert("CVT_" + 1762 getEnumNameForToken(AsmMatchConverter)); 1763 1764 // Add the converter row for this instruction. 1765 ConversionTable.push_back(std::vector<uint8_t>()); 1766 ConversionTable.back().push_back(KindID); 1767 ConversionTable.back().push_back(CVT_Done); 1768 1769 // Add the handler to the conversion driver function. 1770 CvtOS << " case CVT_" 1771 << getEnumNameForToken(AsmMatchConverter) << ":\n" 1772 << " " << AsmMatchConverter << "(Inst, Operands);\n" 1773 << " break;\n"; 1774 1775 // FIXME: Handle the operand number lookup for custom match functions. 1776 continue; 1777 } 1778 1779 // Build the conversion function signature. 1780 std::string Signature = "Convert"; 1781 1782 std::vector<uint8_t> ConversionRow; 1783 1784 // Compute the convert enum and the case body. 1785 MaxRowLength = std::max(MaxRowLength, II.ResOperands.size()*2 + 1 ); 1786 1787 for (unsigned i = 0, e = II.ResOperands.size(); i != e; ++i) { 1788 const MatchableInfo::ResOperand &OpInfo = II.ResOperands[i]; 1789 1790 // Generate code to populate each result operand. 1791 switch (OpInfo.Kind) { 1792 case MatchableInfo::ResOperand::RenderAsmOperand: { 1793 // This comes from something we parsed. 1794 MatchableInfo::AsmOperand &Op = II.AsmOperands[OpInfo.AsmOperandNum]; 1795 1796 // Registers are always converted the same, don't duplicate the 1797 // conversion function based on them. 1798 Signature += "__"; 1799 std::string Class; 1800 Class = Op.Class->isRegisterClass() ? "Reg" : Op.Class->ClassName; 1801 Signature += Class; 1802 Signature += utostr(OpInfo.MINumOperands); 1803 Signature += "_" + itostr(OpInfo.AsmOperandNum); 1804 1805 // Add the conversion kind, if necessary, and get the associated ID 1806 // the index of its entry in the vector). 1807 std::string Name = "CVT_" + (Op.Class->isRegisterClass() ? "Reg" : 1808 Op.Class->RenderMethod); 1809 Name = getEnumNameForToken(Name); 1810 1811 bool IsNewConverter = false; 1812 unsigned ID = getConverterOperandID(Name, OperandConversionKinds, 1813 IsNewConverter); 1814 1815 // Add the operand entry to the instruction kind conversion row. 1816 ConversionRow.push_back(ID); 1817 ConversionRow.push_back(OpInfo.AsmOperandNum + 1); 1818 1819 if (!IsNewConverter) 1820 break; 1821 1822 // This is a new operand kind. Add a handler for it to the 1823 // converter driver. 1824 CvtOS << " case " << Name << ":\n" 1825 << " static_cast<" << TargetOperandClass 1826 << "*>(Operands[*(p + 1)])->" 1827 << Op.Class->RenderMethod << "(Inst, " << OpInfo.MINumOperands 1828 << ");\n" 1829 << " break;\n"; 1830 1831 // Add a handler for the operand number lookup. 1832 OpOS << " case " << Name << ":\n" 1833 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"; 1834 1835 if (Op.Class->isRegisterClass()) 1836 OpOS << " Operands[*(p + 1)]->setConstraint(\"r\");\n"; 1837 else 1838 OpOS << " Operands[*(p + 1)]->setConstraint(\"m\");\n"; 1839 OpOS << " NumMCOperands += " << OpInfo.MINumOperands << ";\n" 1840 << " break;\n"; 1841 break; 1842 } 1843 case MatchableInfo::ResOperand::TiedOperand: { 1844 // If this operand is tied to a previous one, just copy the MCInst 1845 // operand from the earlier one.We can only tie single MCOperand values. 1846 //assert(OpInfo.MINumOperands == 1 && "Not a singular MCOperand"); 1847 unsigned TiedOp = OpInfo.TiedOperandNum; 1848 assert(i > TiedOp && "Tied operand precedes its target!"); 1849 Signature += "__Tie" + utostr(TiedOp); 1850 ConversionRow.push_back(CVT_Tied); 1851 ConversionRow.push_back(TiedOp); 1852 // FIXME: Handle the operand number lookup for tied operands. 1853 break; 1854 } 1855 case MatchableInfo::ResOperand::ImmOperand: { 1856 int64_t Val = OpInfo.ImmVal; 1857 std::string Ty = "imm_" + itostr(Val); 1858 Signature += "__" + Ty; 1859 1860 std::string Name = "CVT_" + Ty; 1861 bool IsNewConverter = false; 1862 unsigned ID = getConverterOperandID(Name, OperandConversionKinds, 1863 IsNewConverter); 1864 // Add the operand entry to the instruction kind conversion row. 1865 ConversionRow.push_back(ID); 1866 ConversionRow.push_back(0); 1867 1868 if (!IsNewConverter) 1869 break; 1870 1871 CvtOS << " case " << Name << ":\n" 1872 << " Inst.addOperand(MCOperand::CreateImm(" << Val << "));\n" 1873 << " break;\n"; 1874 1875 OpOS << " case " << Name << ":\n" 1876 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n" 1877 << " Operands[*(p + 1)]->setConstraint(\"\");\n" 1878 << " ++NumMCOperands;\n" 1879 << " break;\n"; 1880 break; 1881 } 1882 case MatchableInfo::ResOperand::RegOperand: { 1883 std::string Reg, Name; 1884 if (OpInfo.Register == 0) { 1885 Name = "reg0"; 1886 Reg = "0"; 1887 } else { 1888 Reg = getQualifiedName(OpInfo.Register); 1889 Name = "reg" + OpInfo.Register->getName(); 1890 } 1891 Signature += "__" + Name; 1892 Name = "CVT_" + Name; 1893 bool IsNewConverter = false; 1894 unsigned ID = getConverterOperandID(Name, OperandConversionKinds, 1895 IsNewConverter); 1896 // Add the operand entry to the instruction kind conversion row. 1897 ConversionRow.push_back(ID); 1898 ConversionRow.push_back(0); 1899 1900 if (!IsNewConverter) 1901 break; 1902 CvtOS << " case " << Name << ":\n" 1903 << " Inst.addOperand(MCOperand::CreateReg(" << Reg << "));\n" 1904 << " break;\n"; 1905 1906 OpOS << " case " << Name << ":\n" 1907 << " Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n" 1908 << " Operands[*(p + 1)]->setConstraint(\"m\");\n" 1909 << " ++NumMCOperands;\n" 1910 << " break;\n"; 1911 } 1912 } 1913 } 1914 1915 // If there were no operands, add to the signature to that effect 1916 if (Signature == "Convert") 1917 Signature += "_NoOperands"; 1918 1919 II.ConversionFnKind = Signature; 1920 1921 // Save the signature. If we already have it, don't add a new row 1922 // to the table. 1923 if (!InstructionConversionKinds.insert(Signature)) 1924 continue; 1925 1926 // Add the row to the table. 1927 ConversionTable.push_back(ConversionRow); 1928 } 1929 1930 // Finish up the converter driver function. 1931 CvtOS << " }\n }\n}\n\n"; 1932 1933 // Finish up the operand number lookup function. 1934 OpOS << " }\n }\n}\n\n"; 1935 1936 OS << "namespace {\n"; 1937 1938 // Output the operand conversion kind enum. 1939 OS << "enum OperatorConversionKind {\n"; 1940 for (unsigned i = 0, e = OperandConversionKinds.size(); i != e; ++i) 1941 OS << " " << OperandConversionKinds[i] << ",\n"; 1942 OS << " CVT_NUM_CONVERTERS\n"; 1943 OS << "};\n\n"; 1944 1945 // Output the instruction conversion kind enum. 1946 OS << "enum InstructionConversionKind {\n"; 1947 for (SetVector<std::string>::const_iterator 1948 i = InstructionConversionKinds.begin(), 1949 e = InstructionConversionKinds.end(); i != e; ++i) 1950 OS << " " << *i << ",\n"; 1951 OS << " CVT_NUM_SIGNATURES\n"; 1952 OS << "};\n\n"; 1953 1954 1955 OS << "} // end anonymous namespace\n\n"; 1956 1957 // Output the conversion table. 1958 OS << "static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][" 1959 << MaxRowLength << "] = {\n"; 1960 1961 for (unsigned Row = 0, ERow = ConversionTable.size(); Row != ERow; ++Row) { 1962 assert(ConversionTable[Row].size() % 2 == 0 && "bad conversion row!"); 1963 OS << " // " << InstructionConversionKinds[Row] << "\n"; 1964 OS << " { "; 1965 for (unsigned i = 0, e = ConversionTable[Row].size(); i != e; i += 2) 1966 OS << OperandConversionKinds[ConversionTable[Row][i]] << ", " 1967 << (unsigned)(ConversionTable[Row][i + 1]) << ", "; 1968 OS << "CVT_Done },\n"; 1969 } 1970 1971 OS << "};\n\n"; 1972 1973 // Spit out the conversion driver function. 1974 OS << CvtOS.str(); 1975 1976 // Spit out the operand number lookup function. 1977 OS << OpOS.str(); 1978 } 1979 1980 /// emitMatchClassEnumeration - Emit the enumeration for match class kinds. 1981 static void emitMatchClassEnumeration(CodeGenTarget &Target, 1982 std::vector<ClassInfo*> &Infos, 1983 raw_ostream &OS) { 1984 OS << "namespace {\n\n"; 1985 1986 OS << "/// MatchClassKind - The kinds of classes which participate in\n" 1987 << "/// instruction matching.\n"; 1988 OS << "enum MatchClassKind {\n"; 1989 OS << " InvalidMatchClass = 0,\n"; 1990 for (std::vector<ClassInfo*>::iterator it = Infos.begin(), 1991 ie = Infos.end(); it != ie; ++it) { 1992 ClassInfo &CI = **it; 1993 OS << " " << CI.Name << ", // "; 1994 if (CI.Kind == ClassInfo::Token) { 1995 OS << "'" << CI.ValueName << "'\n"; 1996 } else if (CI.isRegisterClass()) { 1997 if (!CI.ValueName.empty()) 1998 OS << "register class '" << CI.ValueName << "'\n"; 1999 else 2000 OS << "derived register class\n"; 2001 } else { 2002 OS << "user defined class '" << CI.ValueName << "'\n"; 2003 } 2004 } 2005 OS << " NumMatchClassKinds\n"; 2006 OS << "};\n\n"; 2007 2008 OS << "}\n\n"; 2009 } 2010 2011 /// emitValidateOperandClass - Emit the function to validate an operand class. 2012 static void emitValidateOperandClass(AsmMatcherInfo &Info, 2013 raw_ostream &OS) { 2014 OS << "static unsigned validateOperandClass(MCParsedAsmOperand *GOp, " 2015 << "MatchClassKind Kind) {\n"; 2016 OS << " " << Info.Target.getName() << "Operand &Operand = *(" 2017 << Info.Target.getName() << "Operand*)GOp;\n"; 2018 2019 // The InvalidMatchClass is not to match any operand. 2020 OS << " if (Kind == InvalidMatchClass)\n"; 2021 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n\n"; 2022 2023 // Check for Token operands first. 2024 // FIXME: Use a more specific diagnostic type. 2025 OS << " if (Operand.isToken())\n"; 2026 OS << " return isSubclass(matchTokenString(Operand.getToken()), Kind) ?\n" 2027 << " MCTargetAsmParser::Match_Success :\n" 2028 << " MCTargetAsmParser::Match_InvalidOperand;\n\n"; 2029 2030 // Check the user classes. We don't care what order since we're only 2031 // actually matching against one of them. 2032 for (std::vector<ClassInfo*>::iterator it = Info.Classes.begin(), 2033 ie = Info.Classes.end(); it != ie; ++it) { 2034 ClassInfo &CI = **it; 2035 2036 if (!CI.isUserClass()) 2037 continue; 2038 2039 OS << " // '" << CI.ClassName << "' class\n"; 2040 OS << " if (Kind == " << CI.Name << ") {\n"; 2041 OS << " if (Operand." << CI.PredicateMethod << "())\n"; 2042 OS << " return MCTargetAsmParser::Match_Success;\n"; 2043 if (!CI.DiagnosticType.empty()) 2044 OS << " return " << Info.Target.getName() << "AsmParser::Match_" 2045 << CI.DiagnosticType << ";\n"; 2046 OS << " }\n\n"; 2047 } 2048 2049 // Check for register operands, including sub-classes. 2050 OS << " if (Operand.isReg()) {\n"; 2051 OS << " MatchClassKind OpKind;\n"; 2052 OS << " switch (Operand.getReg()) {\n"; 2053 OS << " default: OpKind = InvalidMatchClass; break;\n"; 2054 for (AsmMatcherInfo::RegisterClassesTy::iterator 2055 it = Info.RegisterClasses.begin(), ie = Info.RegisterClasses.end(); 2056 it != ie; ++it) 2057 OS << " case " << Info.Target.getName() << "::" 2058 << it->first->getName() << ": OpKind = " << it->second->Name 2059 << "; break;\n"; 2060 OS << " }\n"; 2061 OS << " return isSubclass(OpKind, Kind) ? " 2062 << "MCTargetAsmParser::Match_Success :\n " 2063 << " MCTargetAsmParser::Match_InvalidOperand;\n }\n\n"; 2064 2065 // Generic fallthrough match failure case for operands that don't have 2066 // specialized diagnostic types. 2067 OS << " return MCTargetAsmParser::Match_InvalidOperand;\n"; 2068 OS << "}\n\n"; 2069 } 2070 2071 /// emitIsSubclass - Emit the subclass predicate function. 2072 static void emitIsSubclass(CodeGenTarget &Target, 2073 std::vector<ClassInfo*> &Infos, 2074 raw_ostream &OS) { 2075 OS << "/// isSubclass - Compute whether \\p A is a subclass of \\p B.\n"; 2076 OS << "static bool isSubclass(MatchClassKind A, MatchClassKind B) {\n"; 2077 OS << " if (A == B)\n"; 2078 OS << " return true;\n\n"; 2079 2080 OS << " switch (A) {\n"; 2081 OS << " default:\n"; 2082 OS << " return false;\n"; 2083 for (std::vector<ClassInfo*>::iterator it = Infos.begin(), 2084 ie = Infos.end(); it != ie; ++it) { 2085 ClassInfo &A = **it; 2086 2087 std::vector<StringRef> SuperClasses; 2088 for (std::vector<ClassInfo*>::iterator it = Infos.begin(), 2089 ie = Infos.end(); it != ie; ++it) { 2090 ClassInfo &B = **it; 2091 2092 if (&A != &B && A.isSubsetOf(B)) 2093 SuperClasses.push_back(B.Name); 2094 } 2095 2096 if (SuperClasses.empty()) 2097 continue; 2098 2099 OS << "\n case " << A.Name << ":\n"; 2100 2101 if (SuperClasses.size() == 1) { 2102 OS << " return B == " << SuperClasses.back() << ";\n"; 2103 continue; 2104 } 2105 2106 OS << " switch (B) {\n"; 2107 OS << " default: return false;\n"; 2108 for (unsigned i = 0, e = SuperClasses.size(); i != e; ++i) 2109 OS << " case " << SuperClasses[i] << ": return true;\n"; 2110 OS << " }\n"; 2111 } 2112 OS << " }\n"; 2113 OS << "}\n\n"; 2114 } 2115 2116 /// emitMatchTokenString - Emit the function to match a token string to the 2117 /// appropriate match class value. 2118 static void emitMatchTokenString(CodeGenTarget &Target, 2119 std::vector<ClassInfo*> &Infos, 2120 raw_ostream &OS) { 2121 // Construct the match list. 2122 std::vector<StringMatcher::StringPair> Matches; 2123 for (std::vector<ClassInfo*>::iterator it = Infos.begin(), 2124 ie = Infos.end(); it != ie; ++it) { 2125 ClassInfo &CI = **it; 2126 2127 if (CI.Kind == ClassInfo::Token) 2128 Matches.push_back(StringMatcher::StringPair(CI.ValueName, 2129 "return " + CI.Name + ";")); 2130 } 2131 2132 OS << "static MatchClassKind matchTokenString(StringRef Name) {\n"; 2133 2134 StringMatcher("Name", Matches, OS).Emit(); 2135 2136 OS << " return InvalidMatchClass;\n"; 2137 OS << "}\n\n"; 2138 } 2139 2140 /// emitMatchRegisterName - Emit the function to match a string to the target 2141 /// specific register enum. 2142 static void emitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser, 2143 raw_ostream &OS) { 2144 // Construct the match list. 2145 std::vector<StringMatcher::StringPair> Matches; 2146 const std::vector<CodeGenRegister*> &Regs = 2147 Target.getRegBank().getRegisters(); 2148 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 2149 const CodeGenRegister *Reg = Regs[i]; 2150 if (Reg->TheDef->getValueAsString("AsmName").empty()) 2151 continue; 2152 2153 Matches.push_back(StringMatcher::StringPair( 2154 Reg->TheDef->getValueAsString("AsmName"), 2155 "return " + utostr(Reg->EnumValue) + ";")); 2156 } 2157 2158 OS << "static unsigned MatchRegisterName(StringRef Name) {\n"; 2159 2160 StringMatcher("Name", Matches, OS).Emit(); 2161 2162 OS << " return 0;\n"; 2163 OS << "}\n\n"; 2164 } 2165 2166 /// emitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag 2167 /// definitions. 2168 static void emitSubtargetFeatureFlagEnumeration(AsmMatcherInfo &Info, 2169 raw_ostream &OS) { 2170 OS << "// Flags for subtarget features that participate in " 2171 << "instruction matching.\n"; 2172 OS << "enum SubtargetFeatureFlag {\n"; 2173 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator 2174 it = Info.SubtargetFeatures.begin(), 2175 ie = Info.SubtargetFeatures.end(); it != ie; ++it) { 2176 SubtargetFeatureInfo &SFI = *it->second; 2177 OS << " " << SFI.getEnumName() << " = (1 << " << SFI.Index << "),\n"; 2178 } 2179 OS << " Feature_None = 0\n"; 2180 OS << "};\n\n"; 2181 } 2182 2183 /// emitOperandDiagnosticTypes - Emit the operand matching diagnostic types. 2184 static void emitOperandDiagnosticTypes(AsmMatcherInfo &Info, raw_ostream &OS) { 2185 // Get the set of diagnostic types from all of the operand classes. 2186 std::set<StringRef> Types; 2187 for (std::map<Record*, ClassInfo*>::const_iterator 2188 I = Info.AsmOperandClasses.begin(), 2189 E = Info.AsmOperandClasses.end(); I != E; ++I) { 2190 if (!I->second->DiagnosticType.empty()) 2191 Types.insert(I->second->DiagnosticType); 2192 } 2193 2194 if (Types.empty()) return; 2195 2196 // Now emit the enum entries. 2197 for (std::set<StringRef>::const_iterator I = Types.begin(), E = Types.end(); 2198 I != E; ++I) 2199 OS << " Match_" << *I << ",\n"; 2200 OS << " END_OPERAND_DIAGNOSTIC_TYPES\n"; 2201 } 2202 2203 /// emitGetSubtargetFeatureName - Emit the helper function to get the 2204 /// user-level name for a subtarget feature. 2205 static void emitGetSubtargetFeatureName(AsmMatcherInfo &Info, raw_ostream &OS) { 2206 OS << "// User-level names for subtarget features that participate in\n" 2207 << "// instruction matching.\n" 2208 << "static const char *getSubtargetFeatureName(unsigned Val) {\n" 2209 << " switch(Val) {\n"; 2210 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator 2211 it = Info.SubtargetFeatures.begin(), 2212 ie = Info.SubtargetFeatures.end(); it != ie; ++it) { 2213 SubtargetFeatureInfo &SFI = *it->second; 2214 // FIXME: Totally just a placeholder name to get the algorithm working. 2215 OS << " case " << SFI.getEnumName() << ": return \"" 2216 << SFI.TheDef->getValueAsString("PredicateName") << "\";\n"; 2217 } 2218 OS << " default: return \"(unknown)\";\n"; 2219 OS << " }\n}\n\n"; 2220 } 2221 2222 /// emitComputeAvailableFeatures - Emit the function to compute the list of 2223 /// available features given a subtarget. 2224 static void emitComputeAvailableFeatures(AsmMatcherInfo &Info, 2225 raw_ostream &OS) { 2226 std::string ClassName = 2227 Info.AsmParser->getValueAsString("AsmParserClassName"); 2228 2229 OS << "unsigned " << Info.Target.getName() << ClassName << "::\n" 2230 << "ComputeAvailableFeatures(uint64_t FB) const {\n"; 2231 OS << " unsigned Features = 0;\n"; 2232 for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator 2233 it = Info.SubtargetFeatures.begin(), 2234 ie = Info.SubtargetFeatures.end(); it != ie; ++it) { 2235 SubtargetFeatureInfo &SFI = *it->second; 2236 2237 OS << " if ("; 2238 std::string CondStorage = 2239 SFI.TheDef->getValueAsString("AssemblerCondString"); 2240 StringRef Conds = CondStorage; 2241 std::pair<StringRef,StringRef> Comma = Conds.split(','); 2242 bool First = true; 2243 do { 2244 if (!First) 2245 OS << " && "; 2246 2247 bool Neg = false; 2248 StringRef Cond = Comma.first; 2249 if (Cond[0] == '!') { 2250 Neg = true; 2251 Cond = Cond.substr(1); 2252 } 2253 2254 OS << "((FB & " << Info.Target.getName() << "::" << Cond << ")"; 2255 if (Neg) 2256 OS << " == 0"; 2257 else 2258 OS << " != 0"; 2259 OS << ")"; 2260 2261 if (Comma.second.empty()) 2262 break; 2263 2264 First = false; 2265 Comma = Comma.second.split(','); 2266 } while (true); 2267 2268 OS << ")\n"; 2269 OS << " Features |= " << SFI.getEnumName() << ";\n"; 2270 } 2271 OS << " return Features;\n"; 2272 OS << "}\n\n"; 2273 } 2274 2275 static std::string GetAliasRequiredFeatures(Record *R, 2276 const AsmMatcherInfo &Info) { 2277 std::vector<Record*> ReqFeatures = R->getValueAsListOfDefs("Predicates"); 2278 std::string Result; 2279 unsigned NumFeatures = 0; 2280 for (unsigned i = 0, e = ReqFeatures.size(); i != e; ++i) { 2281 SubtargetFeatureInfo *F = Info.getSubtargetFeature(ReqFeatures[i]); 2282 2283 if (F == 0) 2284 PrintFatalError(R->getLoc(), "Predicate '" + ReqFeatures[i]->getName() + 2285 "' is not marked as an AssemblerPredicate!"); 2286 2287 if (NumFeatures) 2288 Result += '|'; 2289 2290 Result += F->getEnumName(); 2291 ++NumFeatures; 2292 } 2293 2294 if (NumFeatures > 1) 2295 Result = '(' + Result + ')'; 2296 return Result; 2297 } 2298 2299 /// emitMnemonicAliases - If the target has any MnemonicAlias<> definitions, 2300 /// emit a function for them and return true, otherwise return false. 2301 static bool emitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info) { 2302 // Ignore aliases when match-prefix is set. 2303 if (!MatchPrefix.empty()) 2304 return false; 2305 2306 std::vector<Record*> Aliases = 2307 Info.getRecords().getAllDerivedDefinitions("MnemonicAlias"); 2308 if (Aliases.empty()) return false; 2309 2310 OS << "static void applyMnemonicAliases(StringRef &Mnemonic, " 2311 "unsigned Features) {\n"; 2312 2313 // Keep track of all the aliases from a mnemonic. Use an std::map so that the 2314 // iteration order of the map is stable. 2315 std::map<std::string, std::vector<Record*> > AliasesFromMnemonic; 2316 2317 for (unsigned i = 0, e = Aliases.size(); i != e; ++i) { 2318 Record *R = Aliases[i]; 2319 AliasesFromMnemonic[R->getValueAsString("FromMnemonic")].push_back(R); 2320 } 2321 2322 // Process each alias a "from" mnemonic at a time, building the code executed 2323 // by the string remapper. 2324 std::vector<StringMatcher::StringPair> Cases; 2325 for (std::map<std::string, std::vector<Record*> >::iterator 2326 I = AliasesFromMnemonic.begin(), E = AliasesFromMnemonic.end(); 2327 I != E; ++I) { 2328 const std::vector<Record*> &ToVec = I->second; 2329 2330 // Loop through each alias and emit code that handles each case. If there 2331 // are two instructions without predicates, emit an error. If there is one, 2332 // emit it last. 2333 std::string MatchCode; 2334 int AliasWithNoPredicate = -1; 2335 2336 for (unsigned i = 0, e = ToVec.size(); i != e; ++i) { 2337 Record *R = ToVec[i]; 2338 std::string FeatureMask = GetAliasRequiredFeatures(R, Info); 2339 2340 // If this unconditionally matches, remember it for later and diagnose 2341 // duplicates. 2342 if (FeatureMask.empty()) { 2343 if (AliasWithNoPredicate != -1) { 2344 // We can't have two aliases from the same mnemonic with no predicate. 2345 PrintError(ToVec[AliasWithNoPredicate]->getLoc(), 2346 "two MnemonicAliases with the same 'from' mnemonic!"); 2347 PrintFatalError(R->getLoc(), "this is the other MnemonicAlias."); 2348 } 2349 2350 AliasWithNoPredicate = i; 2351 continue; 2352 } 2353 if (R->getValueAsString("ToMnemonic") == I->first) 2354 PrintFatalError(R->getLoc(), "MnemonicAlias to the same string"); 2355 2356 if (!MatchCode.empty()) 2357 MatchCode += "else "; 2358 MatchCode += "if ((Features & " + FeatureMask + ") == "+FeatureMask+")\n"; 2359 MatchCode += " Mnemonic = \"" +R->getValueAsString("ToMnemonic")+"\";\n"; 2360 } 2361 2362 if (AliasWithNoPredicate != -1) { 2363 Record *R = ToVec[AliasWithNoPredicate]; 2364 if (!MatchCode.empty()) 2365 MatchCode += "else\n "; 2366 MatchCode += "Mnemonic = \"" + R->getValueAsString("ToMnemonic")+"\";\n"; 2367 } 2368 2369 MatchCode += "return;"; 2370 2371 Cases.push_back(std::make_pair(I->first, MatchCode)); 2372 } 2373 2374 StringMatcher("Mnemonic", Cases, OS).Emit(); 2375 OS << "}\n\n"; 2376 2377 return true; 2378 } 2379 2380 static const char *getMinimalTypeForRange(uint64_t Range) { 2381 assert(Range < 0xFFFFFFFFULL && "Enum too large"); 2382 if (Range > 0xFFFF) 2383 return "uint32_t"; 2384 if (Range > 0xFF) 2385 return "uint16_t"; 2386 return "uint8_t"; 2387 } 2388 2389 static void emitCustomOperandParsing(raw_ostream &OS, CodeGenTarget &Target, 2390 const AsmMatcherInfo &Info, StringRef ClassName, 2391 StringToOffsetTable &StringTable, 2392 unsigned MaxMnemonicIndex) { 2393 unsigned MaxMask = 0; 2394 for (std::vector<OperandMatchEntry>::const_iterator it = 2395 Info.OperandMatchInfo.begin(), ie = Info.OperandMatchInfo.end(); 2396 it != ie; ++it) { 2397 MaxMask |= it->OperandMask; 2398 } 2399 2400 // Emit the static custom operand parsing table; 2401 OS << "namespace {\n"; 2402 OS << " struct OperandMatchEntry {\n"; 2403 OS << " " << getMinimalTypeForRange(1ULL << Info.SubtargetFeatures.size()) 2404 << " RequiredFeatures;\n"; 2405 OS << " " << getMinimalTypeForRange(MaxMnemonicIndex) 2406 << " Mnemonic;\n"; 2407 OS << " " << getMinimalTypeForRange(Info.Classes.size()) 2408 << " Class;\n"; 2409 OS << " " << getMinimalTypeForRange(MaxMask) 2410 << " OperandMask;\n\n"; 2411 OS << " StringRef getMnemonic() const {\n"; 2412 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n"; 2413 OS << " MnemonicTable[Mnemonic]);\n"; 2414 OS << " }\n"; 2415 OS << " };\n\n"; 2416 2417 OS << " // Predicate for searching for an opcode.\n"; 2418 OS << " struct LessOpcodeOperand {\n"; 2419 OS << " bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {\n"; 2420 OS << " return LHS.getMnemonic() < RHS;\n"; 2421 OS << " }\n"; 2422 OS << " bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {\n"; 2423 OS << " return LHS < RHS.getMnemonic();\n"; 2424 OS << " }\n"; 2425 OS << " bool operator()(const OperandMatchEntry &LHS,"; 2426 OS << " const OperandMatchEntry &RHS) {\n"; 2427 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n"; 2428 OS << " }\n"; 2429 OS << " };\n"; 2430 2431 OS << "} // end anonymous namespace.\n\n"; 2432 2433 OS << "static const OperandMatchEntry OperandMatchTable[" 2434 << Info.OperandMatchInfo.size() << "] = {\n"; 2435 2436 OS << " /* Operand List Mask, Mnemonic, Operand Class, Features */\n"; 2437 for (std::vector<OperandMatchEntry>::const_iterator it = 2438 Info.OperandMatchInfo.begin(), ie = Info.OperandMatchInfo.end(); 2439 it != ie; ++it) { 2440 const OperandMatchEntry &OMI = *it; 2441 const MatchableInfo &II = *OMI.MI; 2442 2443 OS << " { "; 2444 2445 // Write the required features mask. 2446 if (!II.RequiredFeatures.empty()) { 2447 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) { 2448 if (i) OS << "|"; 2449 OS << II.RequiredFeatures[i]->getEnumName(); 2450 } 2451 } else 2452 OS << "0"; 2453 2454 // Store a pascal-style length byte in the mnemonic. 2455 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str(); 2456 OS << ", " << StringTable.GetOrAddStringOffset(LenMnemonic, false) 2457 << " /* " << II.Mnemonic << " */, "; 2458 2459 OS << OMI.CI->Name; 2460 2461 OS << ", " << OMI.OperandMask; 2462 OS << " /* "; 2463 bool printComma = false; 2464 for (int i = 0, e = 31; i !=e; ++i) 2465 if (OMI.OperandMask & (1 << i)) { 2466 if (printComma) 2467 OS << ", "; 2468 OS << i; 2469 printComma = true; 2470 } 2471 OS << " */"; 2472 2473 OS << " },\n"; 2474 } 2475 OS << "};\n\n"; 2476 2477 // Emit the operand class switch to call the correct custom parser for 2478 // the found operand class. 2479 OS << Target.getName() << ClassName << "::OperandMatchResultTy " 2480 << Target.getName() << ClassName << "::\n" 2481 << "tryCustomParseOperand(SmallVectorImpl<MCParsedAsmOperand*>" 2482 << " &Operands,\n unsigned MCK) {\n\n" 2483 << " switch(MCK) {\n"; 2484 2485 for (std::vector<ClassInfo*>::const_iterator it = Info.Classes.begin(), 2486 ie = Info.Classes.end(); it != ie; ++it) { 2487 ClassInfo *CI = *it; 2488 if (CI->ParserMethod.empty()) 2489 continue; 2490 OS << " case " << CI->Name << ":\n" 2491 << " return " << CI->ParserMethod << "(Operands);\n"; 2492 } 2493 2494 OS << " default:\n"; 2495 OS << " return MatchOperand_NoMatch;\n"; 2496 OS << " }\n"; 2497 OS << " return MatchOperand_NoMatch;\n"; 2498 OS << "}\n\n"; 2499 2500 // Emit the static custom operand parser. This code is very similar with 2501 // the other matcher. Also use MatchResultTy here just in case we go for 2502 // a better error handling. 2503 OS << Target.getName() << ClassName << "::OperandMatchResultTy " 2504 << Target.getName() << ClassName << "::\n" 2505 << "MatchOperandParserImpl(SmallVectorImpl<MCParsedAsmOperand*>" 2506 << " &Operands,\n StringRef Mnemonic) {\n"; 2507 2508 // Emit code to get the available features. 2509 OS << " // Get the current feature set.\n"; 2510 OS << " unsigned AvailableFeatures = getAvailableFeatures();\n\n"; 2511 2512 OS << " // Get the next operand index.\n"; 2513 OS << " unsigned NextOpNum = Operands.size()-1;\n"; 2514 2515 // Emit code to search the table. 2516 OS << " // Search the table.\n"; 2517 OS << " std::pair<const OperandMatchEntry*, const OperandMatchEntry*>"; 2518 OS << " MnemonicRange =\n"; 2519 OS << " std::equal_range(OperandMatchTable, OperandMatchTable+" 2520 << Info.OperandMatchInfo.size() << ", Mnemonic,\n" 2521 << " LessOpcodeOperand());\n\n"; 2522 2523 OS << " if (MnemonicRange.first == MnemonicRange.second)\n"; 2524 OS << " return MatchOperand_NoMatch;\n\n"; 2525 2526 OS << " for (const OperandMatchEntry *it = MnemonicRange.first,\n" 2527 << " *ie = MnemonicRange.second; it != ie; ++it) {\n"; 2528 2529 OS << " // equal_range guarantees that instruction mnemonic matches.\n"; 2530 OS << " assert(Mnemonic == it->getMnemonic());\n\n"; 2531 2532 // Emit check that the required features are available. 2533 OS << " // check if the available features match\n"; 2534 OS << " if ((AvailableFeatures & it->RequiredFeatures) " 2535 << "!= it->RequiredFeatures) {\n"; 2536 OS << " continue;\n"; 2537 OS << " }\n\n"; 2538 2539 // Emit check to ensure the operand number matches. 2540 OS << " // check if the operand in question has a custom parser.\n"; 2541 OS << " if (!(it->OperandMask & (1 << NextOpNum)))\n"; 2542 OS << " continue;\n\n"; 2543 2544 // Emit call to the custom parser method 2545 OS << " // call custom parse method to handle the operand\n"; 2546 OS << " OperandMatchResultTy Result = "; 2547 OS << "tryCustomParseOperand(Operands, it->Class);\n"; 2548 OS << " if (Result != MatchOperand_NoMatch)\n"; 2549 OS << " return Result;\n"; 2550 OS << " }\n\n"; 2551 2552 OS << " // Okay, we had no match.\n"; 2553 OS << " return MatchOperand_NoMatch;\n"; 2554 OS << "}\n\n"; 2555 } 2556 2557 void AsmMatcherEmitter::run(raw_ostream &OS) { 2558 CodeGenTarget Target(Records); 2559 Record *AsmParser = Target.getAsmParser(); 2560 std::string ClassName = AsmParser->getValueAsString("AsmParserClassName"); 2561 2562 // Compute the information on the instructions to match. 2563 AsmMatcherInfo Info(AsmParser, Target, Records); 2564 Info.buildInfo(); 2565 2566 // Sort the instruction table using the partial order on classes. We use 2567 // stable_sort to ensure that ambiguous instructions are still 2568 // deterministically ordered. 2569 std::stable_sort(Info.Matchables.begin(), Info.Matchables.end(), 2570 less_ptr<MatchableInfo>()); 2571 2572 DEBUG_WITH_TYPE("instruction_info", { 2573 for (std::vector<MatchableInfo*>::iterator 2574 it = Info.Matchables.begin(), ie = Info.Matchables.end(); 2575 it != ie; ++it) 2576 (*it)->dump(); 2577 }); 2578 2579 // Check for ambiguous matchables. 2580 DEBUG_WITH_TYPE("ambiguous_instrs", { 2581 unsigned NumAmbiguous = 0; 2582 for (unsigned i = 0, e = Info.Matchables.size(); i != e; ++i) { 2583 for (unsigned j = i + 1; j != e; ++j) { 2584 MatchableInfo &A = *Info.Matchables[i]; 2585 MatchableInfo &B = *Info.Matchables[j]; 2586 2587 if (A.couldMatchAmbiguouslyWith(B)) { 2588 errs() << "warning: ambiguous matchables:\n"; 2589 A.dump(); 2590 errs() << "\nis incomparable with:\n"; 2591 B.dump(); 2592 errs() << "\n\n"; 2593 ++NumAmbiguous; 2594 } 2595 } 2596 } 2597 if (NumAmbiguous) 2598 errs() << "warning: " << NumAmbiguous 2599 << " ambiguous matchables!\n"; 2600 }); 2601 2602 // Compute the information on the custom operand parsing. 2603 Info.buildOperandMatchInfo(); 2604 2605 // Write the output. 2606 2607 // Information for the class declaration. 2608 OS << "\n#ifdef GET_ASSEMBLER_HEADER\n"; 2609 OS << "#undef GET_ASSEMBLER_HEADER\n"; 2610 OS << " // This should be included into the middle of the declaration of\n"; 2611 OS << " // your subclasses implementation of MCTargetAsmParser.\n"; 2612 OS << " unsigned ComputeAvailableFeatures(uint64_t FeatureBits) const;\n"; 2613 OS << " void convertToMCInst(unsigned Kind, MCInst &Inst, " 2614 << "unsigned Opcode,\n" 2615 << " const SmallVectorImpl<MCParsedAsmOperand*> " 2616 << "&Operands);\n"; 2617 OS << " void convertToMapAndConstraints(unsigned Kind,\n "; 2618 OS << " const SmallVectorImpl<MCParsedAsmOperand*> &Operands);\n"; 2619 OS << " bool mnemonicIsValid(StringRef Mnemonic);\n"; 2620 OS << " unsigned MatchInstructionImpl(\n"; 2621 OS.indent(27); 2622 OS << "const SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n" 2623 << " MCInst &Inst,\n" 2624 << " unsigned &ErrorInfo," 2625 << " bool matchingInlineAsm,\n" 2626 << " unsigned VariantID = 0);\n"; 2627 2628 if (Info.OperandMatchInfo.size()) { 2629 OS << "\n enum OperandMatchResultTy {\n"; 2630 OS << " MatchOperand_Success, // operand matched successfully\n"; 2631 OS << " MatchOperand_NoMatch, // operand did not match\n"; 2632 OS << " MatchOperand_ParseFail // operand matched but had errors\n"; 2633 OS << " };\n"; 2634 OS << " OperandMatchResultTy MatchOperandParserImpl(\n"; 2635 OS << " SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n"; 2636 OS << " StringRef Mnemonic);\n"; 2637 2638 OS << " OperandMatchResultTy tryCustomParseOperand(\n"; 2639 OS << " SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n"; 2640 OS << " unsigned MCK);\n\n"; 2641 } 2642 2643 OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n"; 2644 2645 // Emit the operand match diagnostic enum names. 2646 OS << "\n#ifdef GET_OPERAND_DIAGNOSTIC_TYPES\n"; 2647 OS << "#undef GET_OPERAND_DIAGNOSTIC_TYPES\n\n"; 2648 emitOperandDiagnosticTypes(Info, OS); 2649 OS << "#endif // GET_OPERAND_DIAGNOSTIC_TYPES\n\n"; 2650 2651 2652 OS << "\n#ifdef GET_REGISTER_MATCHER\n"; 2653 OS << "#undef GET_REGISTER_MATCHER\n\n"; 2654 2655 // Emit the subtarget feature enumeration. 2656 emitSubtargetFeatureFlagEnumeration(Info, OS); 2657 2658 // Emit the function to match a register name to number. 2659 // This should be omitted for Mips target 2660 if (AsmParser->getValueAsBit("ShouldEmitMatchRegisterName")) 2661 emitMatchRegisterName(Target, AsmParser, OS); 2662 2663 OS << "#endif // GET_REGISTER_MATCHER\n\n"; 2664 2665 OS << "\n#ifdef GET_SUBTARGET_FEATURE_NAME\n"; 2666 OS << "#undef GET_SUBTARGET_FEATURE_NAME\n\n"; 2667 2668 // Generate the helper function to get the names for subtarget features. 2669 emitGetSubtargetFeatureName(Info, OS); 2670 2671 OS << "#endif // GET_SUBTARGET_FEATURE_NAME\n\n"; 2672 2673 OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n"; 2674 OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n"; 2675 2676 // Generate the function that remaps for mnemonic aliases. 2677 bool HasMnemonicAliases = emitMnemonicAliases(OS, Info); 2678 2679 // Generate the convertToMCInst function to convert operands into an MCInst. 2680 // Also, generate the convertToMapAndConstraints function for MS-style inline 2681 // assembly. The latter doesn't actually generate a MCInst. 2682 emitConvertFuncs(Target, ClassName, Info.Matchables, OS); 2683 2684 // Emit the enumeration for classes which participate in matching. 2685 emitMatchClassEnumeration(Target, Info.Classes, OS); 2686 2687 // Emit the routine to match token strings to their match class. 2688 emitMatchTokenString(Target, Info.Classes, OS); 2689 2690 // Emit the subclass predicate routine. 2691 emitIsSubclass(Target, Info.Classes, OS); 2692 2693 // Emit the routine to validate an operand against a match class. 2694 emitValidateOperandClass(Info, OS); 2695 2696 // Emit the available features compute function. 2697 emitComputeAvailableFeatures(Info, OS); 2698 2699 2700 StringToOffsetTable StringTable; 2701 2702 size_t MaxNumOperands = 0; 2703 unsigned MaxMnemonicIndex = 0; 2704 for (std::vector<MatchableInfo*>::const_iterator it = 2705 Info.Matchables.begin(), ie = Info.Matchables.end(); 2706 it != ie; ++it) { 2707 MatchableInfo &II = **it; 2708 MaxNumOperands = std::max(MaxNumOperands, II.AsmOperands.size()); 2709 2710 // Store a pascal-style length byte in the mnemonic. 2711 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str(); 2712 MaxMnemonicIndex = std::max(MaxMnemonicIndex, 2713 StringTable.GetOrAddStringOffset(LenMnemonic, false)); 2714 } 2715 2716 OS << "static const char *const MnemonicTable =\n"; 2717 StringTable.EmitString(OS); 2718 OS << ";\n\n"; 2719 2720 // Emit the static match table; unused classes get initalized to 0 which is 2721 // guaranteed to be InvalidMatchClass. 2722 // 2723 // FIXME: We can reduce the size of this table very easily. First, we change 2724 // it so that store the kinds in separate bit-fields for each index, which 2725 // only needs to be the max width used for classes at that index (we also need 2726 // to reject based on this during classification). If we then make sure to 2727 // order the match kinds appropriately (putting mnemonics last), then we 2728 // should only end up using a few bits for each class, especially the ones 2729 // following the mnemonic. 2730 OS << "namespace {\n"; 2731 OS << " struct MatchEntry {\n"; 2732 OS << " " << getMinimalTypeForRange(MaxMnemonicIndex) 2733 << " Mnemonic;\n"; 2734 OS << " uint16_t Opcode;\n"; 2735 OS << " " << getMinimalTypeForRange(Info.Matchables.size()) 2736 << " ConvertFn;\n"; 2737 OS << " " << getMinimalTypeForRange(1ULL << Info.SubtargetFeatures.size()) 2738 << " RequiredFeatures;\n"; 2739 OS << " " << getMinimalTypeForRange(Info.Classes.size()) 2740 << " Classes[" << MaxNumOperands << "];\n"; 2741 OS << " uint8_t AsmVariantID;\n\n"; 2742 OS << " StringRef getMnemonic() const {\n"; 2743 OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n"; 2744 OS << " MnemonicTable[Mnemonic]);\n"; 2745 OS << " }\n"; 2746 OS << " };\n\n"; 2747 2748 OS << " // Predicate for searching for an opcode.\n"; 2749 OS << " struct LessOpcode {\n"; 2750 OS << " bool operator()(const MatchEntry &LHS, StringRef RHS) {\n"; 2751 OS << " return LHS.getMnemonic() < RHS;\n"; 2752 OS << " }\n"; 2753 OS << " bool operator()(StringRef LHS, const MatchEntry &RHS) {\n"; 2754 OS << " return LHS < RHS.getMnemonic();\n"; 2755 OS << " }\n"; 2756 OS << " bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {\n"; 2757 OS << " return LHS.getMnemonic() < RHS.getMnemonic();\n"; 2758 OS << " }\n"; 2759 OS << " };\n"; 2760 2761 OS << "} // end anonymous namespace.\n\n"; 2762 2763 OS << "static const MatchEntry MatchTable[" 2764 << Info.Matchables.size() << "] = {\n"; 2765 2766 for (std::vector<MatchableInfo*>::const_iterator it = 2767 Info.Matchables.begin(), ie = Info.Matchables.end(); 2768 it != ie; ++it) { 2769 MatchableInfo &II = **it; 2770 2771 // Store a pascal-style length byte in the mnemonic. 2772 std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str(); 2773 OS << " { " << StringTable.GetOrAddStringOffset(LenMnemonic, false) 2774 << " /* " << II.Mnemonic << " */, " 2775 << Target.getName() << "::" 2776 << II.getResultInst()->TheDef->getName() << ", " 2777 << II.ConversionFnKind << ", "; 2778 2779 // Write the required features mask. 2780 if (!II.RequiredFeatures.empty()) { 2781 for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) { 2782 if (i) OS << "|"; 2783 OS << II.RequiredFeatures[i]->getEnumName(); 2784 } 2785 } else 2786 OS << "0"; 2787 2788 OS << ", { "; 2789 for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) { 2790 MatchableInfo::AsmOperand &Op = II.AsmOperands[i]; 2791 2792 if (i) OS << ", "; 2793 OS << Op.Class->Name; 2794 } 2795 OS << " }, " << II.AsmVariantID; 2796 OS << "},\n"; 2797 } 2798 2799 OS << "};\n\n"; 2800 2801 // A method to determine if a mnemonic is in the list. 2802 OS << "bool " << Target.getName() << ClassName << "::\n" 2803 << "mnemonicIsValid(StringRef Mnemonic) {\n"; 2804 OS << " // Search the table.\n"; 2805 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n"; 2806 OS << " std::equal_range(MatchTable, MatchTable+" 2807 << Info.Matchables.size() << ", Mnemonic, LessOpcode());\n"; 2808 OS << " return MnemonicRange.first != MnemonicRange.second;\n"; 2809 OS << "}\n\n"; 2810 2811 // Finally, build the match function. 2812 OS << "unsigned " 2813 << Target.getName() << ClassName << "::\n" 2814 << "MatchInstructionImpl(const SmallVectorImpl<MCParsedAsmOperand*>" 2815 << " &Operands,\n"; 2816 OS << " MCInst &Inst,\n" 2817 << "unsigned &ErrorInfo, bool matchingInlineAsm, unsigned VariantID) {\n"; 2818 2819 OS << " // Eliminate obvious mismatches.\n"; 2820 OS << " if (Operands.size() > " << (MaxNumOperands+1) << ") {\n"; 2821 OS << " ErrorInfo = " << (MaxNumOperands+1) << ";\n"; 2822 OS << " return Match_InvalidOperand;\n"; 2823 OS << " }\n\n"; 2824 2825 // Emit code to get the available features. 2826 OS << " // Get the current feature set.\n"; 2827 OS << " unsigned AvailableFeatures = getAvailableFeatures();\n\n"; 2828 2829 OS << " // Get the instruction mnemonic, which is the first token.\n"; 2830 OS << " StringRef Mnemonic = ((" << Target.getName() 2831 << "Operand*)Operands[0])->getToken();\n\n"; 2832 2833 if (HasMnemonicAliases) { 2834 OS << " // Process all MnemonicAliases to remap the mnemonic.\n"; 2835 OS << " // FIXME : Add an entry in AsmParserVariant to check this.\n"; 2836 OS << " if (!VariantID)\n"; 2837 OS << " applyMnemonicAliases(Mnemonic, AvailableFeatures);\n\n"; 2838 } 2839 2840 // Emit code to compute the class list for this operand vector. 2841 OS << " // Some state to try to produce better error messages.\n"; 2842 OS << " bool HadMatchOtherThanFeatures = false;\n"; 2843 OS << " bool HadMatchOtherThanPredicate = false;\n"; 2844 OS << " unsigned RetCode = Match_InvalidOperand;\n"; 2845 OS << " unsigned MissingFeatures = ~0U;\n"; 2846 OS << " // Set ErrorInfo to the operand that mismatches if it is\n"; 2847 OS << " // wrong for all instances of the instruction.\n"; 2848 OS << " ErrorInfo = ~0U;\n"; 2849 2850 // Emit code to search the table. 2851 OS << " // Search the table.\n"; 2852 OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n"; 2853 OS << " std::equal_range(MatchTable, MatchTable+" 2854 << Info.Matchables.size() << ", Mnemonic, LessOpcode());\n\n"; 2855 2856 OS << " // Return a more specific error code if no mnemonics match.\n"; 2857 OS << " if (MnemonicRange.first == MnemonicRange.second)\n"; 2858 OS << " return Match_MnemonicFail;\n\n"; 2859 2860 OS << " for (const MatchEntry *it = MnemonicRange.first, " 2861 << "*ie = MnemonicRange.second;\n"; 2862 OS << " it != ie; ++it) {\n"; 2863 2864 OS << " // equal_range guarantees that instruction mnemonic matches.\n"; 2865 OS << " assert(Mnemonic == it->getMnemonic());\n"; 2866 2867 // Emit check that the subclasses match. 2868 OS << " if (VariantID != it->AsmVariantID) continue;\n"; 2869 OS << " bool OperandsValid = true;\n"; 2870 OS << " for (unsigned i = 0; i != " << MaxNumOperands << "; ++i) {\n"; 2871 OS << " if (i + 1 >= Operands.size()) {\n"; 2872 OS << " OperandsValid = (it->Classes[i] == " <<"InvalidMatchClass);\n"; 2873 OS << " if (!OperandsValid) ErrorInfo = i + 1;\n"; 2874 OS << " break;\n"; 2875 OS << " }\n"; 2876 OS << " unsigned Diag = validateOperandClass(Operands[i+1],\n"; 2877 OS.indent(43); 2878 OS << "(MatchClassKind)it->Classes[i]);\n"; 2879 OS << " if (Diag == Match_Success)\n"; 2880 OS << " continue;\n"; 2881 OS << " // If the generic handler indicates an invalid operand\n"; 2882 OS << " // failure, check for a special case.\n"; 2883 OS << " if (Diag == Match_InvalidOperand) {\n"; 2884 OS << " Diag = validateTargetOperandClass(Operands[i+1],\n"; 2885 OS.indent(43); 2886 OS << "(MatchClassKind)it->Classes[i]);\n"; 2887 OS << " if (Diag == Match_Success)\n"; 2888 OS << " continue;\n"; 2889 OS << " }\n"; 2890 OS << " // If this operand is broken for all of the instances of this\n"; 2891 OS << " // mnemonic, keep track of it so we can report loc info.\n"; 2892 OS << " // If we already had a match that only failed due to a\n"; 2893 OS << " // target predicate, that diagnostic is preferred.\n"; 2894 OS << " if (!HadMatchOtherThanPredicate &&\n"; 2895 OS << " (it == MnemonicRange.first || ErrorInfo <= i+1)) {\n"; 2896 OS << " ErrorInfo = i+1;\n"; 2897 OS << " // InvalidOperand is the default. Prefer specificity.\n"; 2898 OS << " if (Diag != Match_InvalidOperand)\n"; 2899 OS << " RetCode = Diag;\n"; 2900 OS << " }\n"; 2901 OS << " // Otherwise, just reject this instance of the mnemonic.\n"; 2902 OS << " OperandsValid = false;\n"; 2903 OS << " break;\n"; 2904 OS << " }\n\n"; 2905 2906 OS << " if (!OperandsValid) continue;\n"; 2907 2908 // Emit check that the required features are available. 2909 OS << " if ((AvailableFeatures & it->RequiredFeatures) " 2910 << "!= it->RequiredFeatures) {\n"; 2911 OS << " HadMatchOtherThanFeatures = true;\n"; 2912 OS << " unsigned NewMissingFeatures = it->RequiredFeatures & " 2913 "~AvailableFeatures;\n"; 2914 OS << " if (CountPopulation_32(NewMissingFeatures) <=\n" 2915 " CountPopulation_32(MissingFeatures))\n"; 2916 OS << " MissingFeatures = NewMissingFeatures;\n"; 2917 OS << " continue;\n"; 2918 OS << " }\n"; 2919 OS << "\n"; 2920 OS << " if (matchingInlineAsm) {\n"; 2921 OS << " Inst.setOpcode(it->Opcode);\n"; 2922 OS << " convertToMapAndConstraints(it->ConvertFn, Operands);\n"; 2923 OS << " return Match_Success;\n"; 2924 OS << " }\n\n"; 2925 OS << " // We have selected a definite instruction, convert the parsed\n" 2926 << " // operands into the appropriate MCInst.\n"; 2927 OS << " convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n"; 2928 OS << "\n"; 2929 2930 // Verify the instruction with the target-specific match predicate function. 2931 OS << " // We have a potential match. Check the target predicate to\n" 2932 << " // handle any context sensitive constraints.\n" 2933 << " unsigned MatchResult;\n" 2934 << " if ((MatchResult = checkTargetMatchPredicate(Inst)) !=" 2935 << " Match_Success) {\n" 2936 << " Inst.clear();\n" 2937 << " RetCode = MatchResult;\n" 2938 << " HadMatchOtherThanPredicate = true;\n" 2939 << " continue;\n" 2940 << " }\n\n"; 2941 2942 // Call the post-processing function, if used. 2943 std::string InsnCleanupFn = 2944 AsmParser->getValueAsString("AsmParserInstCleanup"); 2945 if (!InsnCleanupFn.empty()) 2946 OS << " " << InsnCleanupFn << "(Inst);\n"; 2947 2948 OS << " return Match_Success;\n"; 2949 OS << " }\n\n"; 2950 2951 OS << " // Okay, we had no match. Try to return a useful error code.\n"; 2952 OS << " if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)\n"; 2953 OS << " return RetCode;\n\n"; 2954 OS << " // Missing feature matches return which features were missing\n"; 2955 OS << " ErrorInfo = MissingFeatures;\n"; 2956 OS << " return Match_MissingFeature;\n"; 2957 OS << "}\n\n"; 2958 2959 if (Info.OperandMatchInfo.size()) 2960 emitCustomOperandParsing(OS, Target, Info, ClassName, StringTable, 2961 MaxMnemonicIndex); 2962 2963 OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n"; 2964 } 2965 2966 namespace llvm { 2967 2968 void EmitAsmMatcher(RecordKeeper &RK, raw_ostream &OS) { 2969 emitSourceFileHeader("Assembly Matcher Source Fragment", OS); 2970 AsmMatcherEmitter(RK).run(OS); 2971 } 2972 2973 } // End llvm namespace 2974