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      1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file defines the interfaces that X86 uses to lower LLVM code into a
     11 // selection DAG.
     12 //
     13 //===----------------------------------------------------------------------===//
     14 
     15 #ifndef X86ISELLOWERING_H
     16 #define X86ISELLOWERING_H
     17 
     18 #include "X86MachineFunctionInfo.h"
     19 #include "X86RegisterInfo.h"
     20 #include "X86Subtarget.h"
     21 #include "llvm/CodeGen/CallingConvLower.h"
     22 #include "llvm/CodeGen/FastISel.h"
     23 #include "llvm/CodeGen/SelectionDAG.h"
     24 #include "llvm/Target/TargetLowering.h"
     25 #include "llvm/Target/TargetOptions.h"
     26 
     27 namespace llvm {
     28   namespace X86ISD {
     29     // X86 Specific DAG Nodes
     30     enum NodeType {
     31       // Start the numbering where the builtin ops leave off.
     32       FIRST_NUMBER = ISD::BUILTIN_OP_END,
     33 
     34       /// BSF - Bit scan forward.
     35       /// BSR - Bit scan reverse.
     36       BSF,
     37       BSR,
     38 
     39       /// SHLD, SHRD - Double shift instructions. These correspond to
     40       /// X86::SHLDxx and X86::SHRDxx instructions.
     41       SHLD,
     42       SHRD,
     43 
     44       /// FAND - Bitwise logical AND of floating point values. This corresponds
     45       /// to X86::ANDPS or X86::ANDPD.
     46       FAND,
     47 
     48       /// FOR - Bitwise logical OR of floating point values. This corresponds
     49       /// to X86::ORPS or X86::ORPD.
     50       FOR,
     51 
     52       /// FXOR - Bitwise logical XOR of floating point values. This corresponds
     53       /// to X86::XORPS or X86::XORPD.
     54       FXOR,
     55 
     56       /// FSRL - Bitwise logical right shift of floating point values. These
     57       /// corresponds to X86::PSRLDQ.
     58       FSRL,
     59 
     60       /// CALL - These operations represent an abstract X86 call
     61       /// instruction, which includes a bunch of information.  In particular the
     62       /// operands of these node are:
     63       ///
     64       ///     #0 - The incoming token chain
     65       ///     #1 - The callee
     66       ///     #2 - The number of arg bytes the caller pushes on the stack.
     67       ///     #3 - The number of arg bytes the callee pops off the stack.
     68       ///     #4 - The value to pass in AL/AX/EAX (optional)
     69       ///     #5 - The value to pass in DL/DX/EDX (optional)
     70       ///
     71       /// The result values of these nodes are:
     72       ///
     73       ///     #0 - The outgoing token chain
     74       ///     #1 - The first register result value (optional)
     75       ///     #2 - The second register result value (optional)
     76       ///
     77       CALL,
     78 
     79       /// RDTSC_DAG - This operation implements the lowering for
     80       /// readcyclecounter
     81       RDTSC_DAG,
     82 
     83       /// X86 compare and logical compare instructions.
     84       CMP, COMI, UCOMI,
     85 
     86       /// X86 bit-test instructions.
     87       BT,
     88 
     89       /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
     90       /// operand, usually produced by a CMP instruction.
     91       SETCC,
     92 
     93       // Same as SETCC except it's materialized with a sbb and the value is all
     94       // one's or all zero's.
     95       SETCC_CARRY,  // R = carry_bit ? ~0 : 0
     96 
     97       /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
     98       /// Operands are two FP values to compare; result is a mask of
     99       /// 0s or 1s.  Generally DTRT for C/C++ with NaNs.
    100       FSETCCss, FSETCCsd,
    101 
    102       /// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values,
    103       /// result in an integer GPR.  Needs masking for scalar result.
    104       FGETSIGNx86,
    105 
    106       /// X86 conditional moves. Operand 0 and operand 1 are the two values
    107       /// to select from. Operand 2 is the condition code, and operand 3 is the
    108       /// flag operand produced by a CMP or TEST instruction. It also writes a
    109       /// flag result.
    110       CMOV,
    111 
    112       /// X86 conditional branches. Operand 0 is the chain operand, operand 1
    113       /// is the block to branch if condition is true, operand 2 is the
    114       /// condition code, and operand 3 is the flag operand produced by a CMP
    115       /// or TEST instruction.
    116       BRCOND,
    117 
    118       /// Return with a flag operand. Operand 0 is the chain operand, operand
    119       /// 1 is the number of bytes of stack to pop.
    120       RET_FLAG,
    121 
    122       /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
    123       REP_STOS,
    124 
    125       /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
    126       REP_MOVS,
    127 
    128       /// GlobalBaseReg - On Darwin, this node represents the result of the popl
    129       /// at function entry, used for PIC code.
    130       GlobalBaseReg,
    131 
    132       /// Wrapper - A wrapper node for TargetConstantPool,
    133       /// TargetExternalSymbol, and TargetGlobalAddress.
    134       Wrapper,
    135 
    136       /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP
    137       /// relative displacements.
    138       WrapperRIP,
    139 
    140       /// MOVDQ2Q - Copies a 64-bit value from the low word of an XMM vector
    141       /// to an MMX vector.  If you think this is too close to the previous
    142       /// mnemonic, so do I; blame Intel.
    143       MOVDQ2Q,
    144 
    145       /// MMX_MOVD2W - Copies a 32-bit value from the low word of a MMX
    146       /// vector to a GPR.
    147       MMX_MOVD2W,
    148 
    149       /// PEXTRB - Extract an 8-bit value from a vector and zero extend it to
    150       /// i32, corresponds to X86::PEXTRB.
    151       PEXTRB,
    152 
    153       /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
    154       /// i32, corresponds to X86::PEXTRW.
    155       PEXTRW,
    156 
    157       /// INSERTPS - Insert any element of a 4 x float vector into any element
    158       /// of a destination 4 x floatvector.
    159       INSERTPS,
    160 
    161       /// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector,
    162       /// corresponds to X86::PINSRB.
    163       PINSRB,
    164 
    165       /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
    166       /// corresponds to X86::PINSRW.
    167       PINSRW, MMX_PINSRW,
    168 
    169       /// PSHUFB - Shuffle 16 8-bit values within a vector.
    170       PSHUFB,
    171 
    172       /// ANDNP - Bitwise Logical AND NOT of Packed FP values.
    173       ANDNP,
    174 
    175       /// PSIGN - Copy integer sign.
    176       PSIGN,
    177 
    178       /// BLENDV - Blend where the selector is a register.
    179       BLENDV,
    180 
    181       /// BLENDI - Blend where the selector is an immediate.
    182       BLENDI,
    183 
    184       // SUBUS - Integer sub with unsigned saturation.
    185       SUBUS,
    186 
    187       /// HADD - Integer horizontal add.
    188       HADD,
    189 
    190       /// HSUB - Integer horizontal sub.
    191       HSUB,
    192 
    193       /// FHADD - Floating point horizontal add.
    194       FHADD,
    195 
    196       /// FHSUB - Floating point horizontal sub.
    197       FHSUB,
    198 
    199       /// UMAX, UMIN - Unsigned integer max and min.
    200       UMAX, UMIN,
    201 
    202       /// SMAX, SMIN - Signed integer max and min.
    203       SMAX, SMIN,
    204 
    205       /// FMAX, FMIN - Floating point max and min.
    206       ///
    207       FMAX, FMIN,
    208 
    209       /// FMAXC, FMINC - Commutative FMIN and FMAX.
    210       FMAXC, FMINC,
    211 
    212       /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal
    213       /// approximation.  Note that these typically require refinement
    214       /// in order to obtain suitable precision.
    215       FRSQRT, FRCP,
    216 
    217       // TLSADDR - Thread Local Storage.
    218       TLSADDR,
    219 
    220       // TLSBASEADDR - Thread Local Storage. A call to get the start address
    221       // of the TLS block for the current module.
    222       TLSBASEADDR,
    223 
    224       // TLSCALL - Thread Local Storage.  When calling to an OS provided
    225       // thunk at the address from an earlier relocation.
    226       TLSCALL,
    227 
    228       // EH_RETURN - Exception Handling helpers.
    229       EH_RETURN,
    230 
    231       // EH_SJLJ_SETJMP - SjLj exception handling setjmp.
    232       EH_SJLJ_SETJMP,
    233 
    234       // EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
    235       EH_SJLJ_LONGJMP,
    236 
    237       /// TC_RETURN - Tail call return. See X86TargetLowering::LowerCall for
    238       /// the list of operands.
    239       TC_RETURN,
    240 
    241       // VZEXT_MOVL - Vector move low and zero extend.
    242       VZEXT_MOVL,
    243 
    244       // VSEXT_MOVL - Vector move low and sign extend.
    245       VSEXT_MOVL,
    246 
    247       // VZEXT - Vector integer zero-extend.
    248       VZEXT,
    249 
    250       // VSEXT - Vector integer signed-extend.
    251       VSEXT,
    252 
    253       // VFPEXT - Vector FP extend.
    254       VFPEXT,
    255 
    256       // VFPROUND - Vector FP round.
    257       VFPROUND,
    258 
    259       // VSHL, VSRL - 128-bit vector logical left / right shift
    260       VSHLDQ, VSRLDQ,
    261 
    262       // VSHL, VSRL, VSRA - Vector shift elements
    263       VSHL, VSRL, VSRA,
    264 
    265       // VSHLI, VSRLI, VSRAI - Vector shift elements by immediate
    266       VSHLI, VSRLI, VSRAI,
    267 
    268       // CMPP - Vector packed double/float comparison.
    269       CMPP,
    270 
    271       // PCMP* - Vector integer comparisons.
    272       PCMPEQ, PCMPGT,
    273 
    274       // ADD, SUB, SMUL, etc. - Arithmetic operations with FLAGS results.
    275       ADD, SUB, ADC, SBB, SMUL,
    276       INC, DEC, OR, XOR, AND,
    277 
    278       BLSI,   // BLSI - Extract lowest set isolated bit
    279       BLSMSK, // BLSMSK - Get mask up to lowest set bit
    280       BLSR,   // BLSR - Reset lowest set bit
    281 
    282       UMUL, // LOW, HI, FLAGS = umul LHS, RHS
    283 
    284       // MUL_IMM - X86 specific multiply by immediate.
    285       MUL_IMM,
    286 
    287       // PTEST - Vector bitwise comparisons
    288       PTEST,
    289 
    290       // TESTP - Vector packed fp sign bitwise comparisons
    291       TESTP,
    292 
    293       // Several flavors of instructions with vector shuffle behaviors.
    294       PALIGNR,
    295       PSHUFD,
    296       PSHUFHW,
    297       PSHUFLW,
    298       SHUFP,
    299       MOVDDUP,
    300       MOVSHDUP,
    301       MOVSLDUP,
    302       MOVLHPS,
    303       MOVLHPD,
    304       MOVHLPS,
    305       MOVLPS,
    306       MOVLPD,
    307       MOVSD,
    308       MOVSS,
    309       UNPCKL,
    310       UNPCKH,
    311       VPERMILP,
    312       VPERMV,
    313       VPERMI,
    314       VPERM2X128,
    315       VBROADCAST,
    316 
    317       // PMULUDQ - Vector multiply packed unsigned doubleword integers
    318       PMULUDQ,
    319 
    320       // FMA nodes
    321       FMADD,
    322       FNMADD,
    323       FMSUB,
    324       FNMSUB,
    325       FMADDSUB,
    326       FMSUBADD,
    327 
    328       // VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack,
    329       // according to %al. An operator is needed so that this can be expanded
    330       // with control flow.
    331       VASTART_SAVE_XMM_REGS,
    332 
    333       // WIN_ALLOCA - Windows's _chkstk call to do stack probing.
    334       WIN_ALLOCA,
    335 
    336       // SEG_ALLOCA - For allocating variable amounts of stack space when using
    337       // segmented stacks. Check if the current stacklet has enough space, and
    338       // falls back to heap allocation if not.
    339       SEG_ALLOCA,
    340 
    341       // WIN_FTOL - Windows's _ftol2 runtime routine to do fptoui.
    342       WIN_FTOL,
    343 
    344       // Memory barrier
    345       MEMBARRIER,
    346       MFENCE,
    347       SFENCE,
    348       LFENCE,
    349 
    350       // FNSTSW16r - Store FP status word into i16 register.
    351       FNSTSW16r,
    352 
    353       // SAHF - Store contents of %ah into %eflags.
    354       SAHF,
    355 
    356       // RDRAND - Get a random integer and indicate whether it is valid in CF.
    357       RDRAND,
    358 
    359       // PCMP*STRI
    360       PCMPISTRI,
    361       PCMPESTRI,
    362 
    363       // ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG,
    364       // ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG -
    365       // Atomic 64-bit binary operations.
    366       ATOMADD64_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
    367       ATOMSUB64_DAG,
    368       ATOMOR64_DAG,
    369       ATOMXOR64_DAG,
    370       ATOMAND64_DAG,
    371       ATOMNAND64_DAG,
    372       ATOMMAX64_DAG,
    373       ATOMMIN64_DAG,
    374       ATOMUMAX64_DAG,
    375       ATOMUMIN64_DAG,
    376       ATOMSWAP64_DAG,
    377 
    378       // LCMPXCHG_DAG, LCMPXCHG8_DAG, LCMPXCHG16_DAG - Compare and swap.
    379       LCMPXCHG_DAG,
    380       LCMPXCHG8_DAG,
    381       LCMPXCHG16_DAG,
    382 
    383       // VZEXT_LOAD - Load, scalar_to_vector, and zero extend.
    384       VZEXT_LOAD,
    385 
    386       // FNSTCW16m - Store FP control world into i16 memory.
    387       FNSTCW16m,
    388 
    389       /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
    390       /// integer destination in memory and a FP reg source.  This corresponds
    391       /// to the X86::FIST*m instructions and the rounding mode change stuff. It
    392       /// has two inputs (token chain and address) and two outputs (int value
    393       /// and token chain).
    394       FP_TO_INT16_IN_MEM,
    395       FP_TO_INT32_IN_MEM,
    396       FP_TO_INT64_IN_MEM,
    397 
    398       /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
    399       /// integer source in memory and FP reg result.  This corresponds to the
    400       /// X86::FILD*m instructions. It has three inputs (token chain, address,
    401       /// and source type) and two outputs (FP value and token chain). FILD_FLAG
    402       /// also produces a flag).
    403       FILD,
    404       FILD_FLAG,
    405 
    406       /// FLD - This instruction implements an extending load to FP stack slots.
    407       /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
    408       /// operand, ptr to load from, and a ValueType node indicating the type
    409       /// to load to.
    410       FLD,
    411 
    412       /// FST - This instruction implements a truncating store to FP stack
    413       /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
    414       /// chain operand, value to store, address, and a ValueType to store it
    415       /// as.
    416       FST,
    417 
    418       /// VAARG_64 - This instruction grabs the address of the next argument
    419       /// from a va_list. (reads and modifies the va_list in memory)
    420       VAARG_64
    421 
    422       // WARNING: Do not add anything in the end unless you want the node to
    423       // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be
    424       // thought as target memory ops!
    425     };
    426   }
    427 
    428   /// Define some predicates that are used for node matching.
    429   namespace X86 {
    430     /// isVEXTRACTF128Index - Return true if the specified
    431     /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
    432     /// suitable for input to VEXTRACTF128.
    433     bool isVEXTRACTF128Index(SDNode *N);
    434 
    435     /// isVINSERTF128Index - Return true if the specified
    436     /// INSERT_SUBVECTOR operand specifies a subvector insert that is
    437     /// suitable for input to VINSERTF128.
    438     bool isVINSERTF128Index(SDNode *N);
    439 
    440     /// getExtractVEXTRACTF128Immediate - Return the appropriate
    441     /// immediate to extract the specified EXTRACT_SUBVECTOR index
    442     /// with VEXTRACTF128 instructions.
    443     unsigned getExtractVEXTRACTF128Immediate(SDNode *N);
    444 
    445     /// getInsertVINSERTF128Immediate - Return the appropriate
    446     /// immediate to insert at the specified INSERT_SUBVECTOR index
    447     /// with VINSERTF128 instructions.
    448     unsigned getInsertVINSERTF128Immediate(SDNode *N);
    449 
    450     /// isZeroNode - Returns true if Elt is a constant zero or a floating point
    451     /// constant +0.0.
    452     bool isZeroNode(SDValue Elt);
    453 
    454     /// isOffsetSuitableForCodeModel - Returns true of the given offset can be
    455     /// fit into displacement field of the instruction.
    456     bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
    457                                       bool hasSymbolicDisplacement = true);
    458 
    459 
    460     /// isCalleePop - Determines whether the callee is required to pop its
    461     /// own arguments. Callee pop is necessary to support tail calls.
    462     bool isCalleePop(CallingConv::ID CallingConv,
    463                      bool is64Bit, bool IsVarArg, bool TailCallOpt);
    464   }
    465 
    466   //===--------------------------------------------------------------------===//
    467   //  X86TargetLowering - X86 Implementation of the TargetLowering interface
    468   class X86TargetLowering : public TargetLowering {
    469   public:
    470     explicit X86TargetLowering(X86TargetMachine &TM);
    471 
    472     virtual unsigned getJumpTableEncoding() const;
    473 
    474     virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i8; }
    475 
    476     virtual const MCExpr *
    477     LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
    478                               const MachineBasicBlock *MBB, unsigned uid,
    479                               MCContext &Ctx) const;
    480 
    481     /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
    482     /// jumptable.
    483     virtual SDValue getPICJumpTableRelocBase(SDValue Table,
    484                                              SelectionDAG &DAG) const;
    485     virtual const MCExpr *
    486     getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
    487                                  unsigned JTI, MCContext &Ctx) const;
    488 
    489     /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
    490     /// function arguments in the caller parameter area. For X86, aggregates
    491     /// that contains are placed at 16-byte boundaries while the rest are at
    492     /// 4-byte boundaries.
    493     virtual unsigned getByValTypeAlignment(Type *Ty) const;
    494 
    495     /// getOptimalMemOpType - Returns the target specific optimal type for load
    496     /// and store operations as a result of memset, memcpy, and memmove
    497     /// lowering. If DstAlign is zero that means it's safe to destination
    498     /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
    499     /// means there isn't a need to check it against alignment requirement,
    500     /// probably because the source does not need to be loaded. If 'IsMemset' is
    501     /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
    502     /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
    503     /// source is constant so it does not need to be loaded.
    504     /// It returns EVT::Other if the type should be determined using generic
    505     /// target-independent logic.
    506     virtual EVT
    507     getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
    508                         bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
    509                         MachineFunction &MF) const;
    510 
    511     /// isSafeMemOpType - Returns true if it's safe to use load / store of the
    512     /// specified type to expand memcpy / memset inline. This is mostly true
    513     /// for all types except for some special cases. For example, on X86
    514     /// targets without SSE2 f64 load / store are done with fldl / fstpl which
    515     /// also does type conversion. Note the specified type doesn't have to be
    516     /// legal as the hook is used before type legalization.
    517     virtual bool isSafeMemOpType(MVT VT) const;
    518 
    519     /// allowsUnalignedMemoryAccesses - Returns true if the target allows
    520     /// unaligned memory accesses. of the specified type. Returns whether it
    521     /// is "fast" by reference in the second argument.
    522     virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const;
    523 
    524     /// LowerOperation - Provide custom lowering hooks for some operations.
    525     ///
    526     virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
    527 
    528     /// ReplaceNodeResults - Replace the results of node with an illegal result
    529     /// type with new values built out of custom code.
    530     ///
    531     virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
    532                                     SelectionDAG &DAG) const;
    533 
    534 
    535     virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
    536 
    537     /// isTypeDesirableForOp - Return true if the target has native support for
    538     /// the specified value type and it is 'desirable' to use the type for the
    539     /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
    540     /// instruction encodings are longer and some i16 instructions are slow.
    541     virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const;
    542 
    543     /// isTypeDesirable - Return true if the target has native support for the
    544     /// specified value type and it is 'desirable' to use the type. e.g. On x86
    545     /// i16 is legal, but undesirable since i16 instruction encodings are longer
    546     /// and some i16 instructions are slow.
    547     virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const;
    548 
    549     virtual MachineBasicBlock *
    550       EmitInstrWithCustomInserter(MachineInstr *MI,
    551                                   MachineBasicBlock *MBB) const;
    552 
    553 
    554     /// getTargetNodeName - This method returns the name of a target specific
    555     /// DAG node.
    556     virtual const char *getTargetNodeName(unsigned Opcode) const;
    557 
    558     /// getSetCCResultType - Return the value type to use for ISD::SETCC.
    559     virtual EVT getSetCCResultType(EVT VT) const;
    560 
    561     /// computeMaskedBitsForTargetNode - Determine which of the bits specified
    562     /// in Mask are known to be either zero or one and return them in the
    563     /// KnownZero/KnownOne bitsets.
    564     virtual void computeMaskedBitsForTargetNode(const SDValue Op,
    565                                                 APInt &KnownZero,
    566                                                 APInt &KnownOne,
    567                                                 const SelectionDAG &DAG,
    568                                                 unsigned Depth = 0) const;
    569 
    570     // ComputeNumSignBitsForTargetNode - Determine the number of bits in the
    571     // operation that are sign bits.
    572     virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
    573                                                      unsigned Depth) const;
    574 
    575     virtual bool
    576     isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
    577 
    578     SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
    579 
    580     virtual bool ExpandInlineAsm(CallInst *CI) const;
    581 
    582     ConstraintType getConstraintType(const std::string &Constraint) const;
    583 
    584     /// Examine constraint string and operand type and determine a weight value.
    585     /// The operand object must already have been set up with the operand type.
    586     virtual ConstraintWeight getSingleConstraintMatchWeight(
    587       AsmOperandInfo &info, const char *constraint) const;
    588 
    589     virtual const char *LowerXConstraint(EVT ConstraintVT) const;
    590 
    591     /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
    592     /// vector.  If it is invalid, don't add anything to Ops. If hasMemory is
    593     /// true it means one of the asm constraint of the inline asm instruction
    594     /// being processed is 'm'.
    595     virtual void LowerAsmOperandForConstraint(SDValue Op,
    596                                               std::string &Constraint,
    597                                               std::vector<SDValue> &Ops,
    598                                               SelectionDAG &DAG) const;
    599 
    600     /// getRegForInlineAsmConstraint - Given a physical register constraint
    601     /// (e.g. {edx}), return the register number and the register class for the
    602     /// register.  This should only be used for C_Register constraints.  On
    603     /// error, this returns a register number of 0.
    604     std::pair<unsigned, const TargetRegisterClass*>
    605       getRegForInlineAsmConstraint(const std::string &Constraint,
    606                                    EVT VT) const;
    607 
    608     /// isLegalAddressingMode - Return true if the addressing mode represented
    609     /// by AM is legal for this target, for a load/store of the specified type.
    610     virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
    611 
    612     /// isLegalICmpImmediate - Return true if the specified immediate is legal
    613     /// icmp immediate, that is the target has icmp instructions which can
    614     /// compare a register against the immediate without having to materialize
    615     /// the immediate into a register.
    616     virtual bool isLegalICmpImmediate(int64_t Imm) const;
    617 
    618     /// isLegalAddImmediate - Return true if the specified immediate is legal
    619     /// add immediate, that is the target has add instructions which can
    620     /// add a register and the immediate without having to materialize
    621     /// the immediate into a register.
    622     virtual bool isLegalAddImmediate(int64_t Imm) const;
    623 
    624     /// isTruncateFree - Return true if it's free to truncate a value of
    625     /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
    626     /// register EAX to i16 by referencing its sub-register AX.
    627     virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const;
    628     virtual bool isTruncateFree(EVT VT1, EVT VT2) const;
    629 
    630     /// isZExtFree - Return true if any actual instruction that defines a
    631     /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
    632     /// register. This does not necessarily include registers defined in
    633     /// unknown ways, such as incoming arguments, or copies from unknown
    634     /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
    635     /// does not necessarily apply to truncate instructions. e.g. on x86-64,
    636     /// all instructions that define 32-bit values implicit zero-extend the
    637     /// result out to 64 bits.
    638     virtual bool isZExtFree(Type *Ty1, Type *Ty2) const;
    639     virtual bool isZExtFree(EVT VT1, EVT VT2) const;
    640     virtual bool isZExtFree(SDValue Val, EVT VT2) const;
    641 
    642     /// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than
    643     /// a pair of mul and add instructions. fmuladd intrinsics will be expanded to
    644     /// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd
    645     /// is expanded to mul + add.
    646     virtual bool isFMAFasterThanMulAndAdd(EVT) const { return true; }
    647 
    648     /// isNarrowingProfitable - Return true if it's profitable to narrow
    649     /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
    650     /// from i32 to i8 but not from i32 to i16.
    651     virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const;
    652 
    653     /// isFPImmLegal - Returns true if the target can instruction select the
    654     /// specified FP immediate natively. If false, the legalizer will
    655     /// materialize the FP immediate as a load from a constant pool.
    656     virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
    657 
    658     /// isShuffleMaskLegal - Targets can use this to indicate that they only
    659     /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
    660     /// By default, if a target supports the VECTOR_SHUFFLE node, all mask
    661     /// values are assumed to be legal.
    662     virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
    663                                     EVT VT) const;
    664 
    665     /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
    666     /// used by Targets can use this to indicate if there is a suitable
    667     /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
    668     /// pool entry.
    669     virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
    670                                         EVT VT) const;
    671 
    672     /// ShouldShrinkFPConstant - If true, then instruction selection should
    673     /// seek to shrink the FP constant of the specified type to a smaller type
    674     /// in order to save space and / or reduce runtime.
    675     virtual bool ShouldShrinkFPConstant(EVT VT) const {
    676       // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
    677       // expensive than a straight movsd. On the other hand, it's important to
    678       // shrink long double fp constant since fldt is very slow.
    679       return !X86ScalarSSEf64 || VT == MVT::f80;
    680     }
    681 
    682     const X86Subtarget* getSubtarget() const {
    683       return Subtarget;
    684     }
    685 
    686     /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
    687     /// computed in an SSE register, not on the X87 floating point stack.
    688     bool isScalarFPTypeInSSEReg(EVT VT) const {
    689       return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
    690       (VT == MVT::f32 && X86ScalarSSEf32);   // f32 is when SSE1
    691     }
    692 
    693     /// isTargetFTOL - Return true if the target uses the MSVC _ftol2 routine
    694     /// for fptoui.
    695     bool isTargetFTOL() const {
    696       return Subtarget->isTargetWindows() && !Subtarget->is64Bit();
    697     }
    698 
    699     /// isIntegerTypeFTOL - Return true if the MSVC _ftol2 routine should be
    700     /// used for fptoui to the given type.
    701     bool isIntegerTypeFTOL(EVT VT) const {
    702       return isTargetFTOL() && VT == MVT::i64;
    703     }
    704 
    705     /// createFastISel - This method returns a target specific FastISel object,
    706     /// or null if the target does not support "fast" ISel.
    707     virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
    708                                      const TargetLibraryInfo *libInfo) const;
    709 
    710     /// getStackCookieLocation - Return true if the target stores stack
    711     /// protector cookies at a fixed offset in some non-standard address
    712     /// space, and populates the address space and offset as
    713     /// appropriate.
    714     virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const;
    715 
    716     SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
    717                       SelectionDAG &DAG) const;
    718 
    719   protected:
    720     std::pair<const TargetRegisterClass*, uint8_t>
    721     findRepresentativeClass(MVT VT) const;
    722 
    723   private:
    724     /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
    725     /// make the right decision when generating code for different targets.
    726     const X86Subtarget *Subtarget;
    727     const X86RegisterInfo *RegInfo;
    728     const DataLayout *TD;
    729 
    730     /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
    731     /// floating point ops.
    732     /// When SSE is available, use it for f32 operations.
    733     /// When SSE2 is available, use it for f64 operations.
    734     bool X86ScalarSSEf32;
    735     bool X86ScalarSSEf64;
    736 
    737     /// LegalFPImmediates - A list of legal fp immediates.
    738     std::vector<APFloat> LegalFPImmediates;
    739 
    740     /// addLegalFPImmediate - Indicate that this x86 target can instruction
    741     /// select the specified FP immediate natively.
    742     void addLegalFPImmediate(const APFloat& Imm) {
    743       LegalFPImmediates.push_back(Imm);
    744     }
    745 
    746     SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
    747                             CallingConv::ID CallConv, bool isVarArg,
    748                             const SmallVectorImpl<ISD::InputArg> &Ins,
    749                             DebugLoc dl, SelectionDAG &DAG,
    750                             SmallVectorImpl<SDValue> &InVals) const;
    751     SDValue LowerMemArgument(SDValue Chain,
    752                              CallingConv::ID CallConv,
    753                              const SmallVectorImpl<ISD::InputArg> &ArgInfo,
    754                              DebugLoc dl, SelectionDAG &DAG,
    755                              const CCValAssign &VA,  MachineFrameInfo *MFI,
    756                               unsigned i) const;
    757     SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
    758                              DebugLoc dl, SelectionDAG &DAG,
    759                              const CCValAssign &VA,
    760                              ISD::ArgFlagsTy Flags) const;
    761 
    762     // Call lowering helpers.
    763 
    764     /// IsEligibleForTailCallOptimization - Check whether the call is eligible
    765     /// for tail call optimization. Targets which want to do tail call
    766     /// optimization should implement this function.
    767     bool IsEligibleForTailCallOptimization(SDValue Callee,
    768                                            CallingConv::ID CalleeCC,
    769                                            bool isVarArg,
    770                                            bool isCalleeStructRet,
    771                                            bool isCallerStructRet,
    772                                            Type *RetTy,
    773                                     const SmallVectorImpl<ISD::OutputArg> &Outs,
    774                                     const SmallVectorImpl<SDValue> &OutVals,
    775                                     const SmallVectorImpl<ISD::InputArg> &Ins,
    776                                            SelectionDAG& DAG) const;
    777     bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const;
    778     SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
    779                                 SDValue Chain, bool IsTailCall, bool Is64Bit,
    780                                 int FPDiff, DebugLoc dl) const;
    781 
    782     unsigned GetAlignedArgumentStackSize(unsigned StackSize,
    783                                          SelectionDAG &DAG) const;
    784 
    785     std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
    786                                                bool isSigned,
    787                                                bool isReplace) const;
    788 
    789     SDValue LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
    790                                    SelectionDAG &DAG) const;
    791     SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
    792     SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
    793     SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
    794     SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
    795     SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
    796     SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
    797     SDValue LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
    798                                int64_t Offset, SelectionDAG &DAG) const;
    799     SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
    800     SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
    801     SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
    802     SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) const;
    803     SDValue LowerBITCAST(SDValue op, SelectionDAG &DAG) const;
    804     SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
    805     SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
    806     SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const;
    807     SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const;
    808     SDValue lowerUINT_TO_FP_vec(SDValue Op, SelectionDAG &DAG) const;
    809     SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
    810     SDValue LowerZERO_EXTEND(SDValue Op, SelectionDAG &DAG) const;
    811     SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const;
    812     SDValue LowerANY_EXTEND(SDValue Op, SelectionDAG &DAG) const;
    813     SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
    814     SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
    815     SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
    816     SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) const;
    817     SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
    818     SDValue LowerToBT(SDValue And, ISD::CondCode CC,
    819                       DebugLoc dl, SelectionDAG &DAG) const;
    820     SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
    821     SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
    822     SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
    823     SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const;
    824     SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
    825     SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
    826     SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
    827     SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
    828     SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
    829     SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
    830     SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
    831     SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
    832     SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
    833     SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
    834     SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
    835     SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
    836     SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const;
    837     SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) const;
    838     SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
    839     SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
    840 
    841     // Utility functions to help LowerVECTOR_SHUFFLE & LowerBUILD_VECTOR
    842     SDValue LowerVectorBroadcast(SDValue Op, SelectionDAG &DAG) const;
    843     SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const;
    844     SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) const;
    845 
    846     SDValue LowerVectorAllZeroTest(SDValue Op, SelectionDAG &DAG) const;
    847 
    848     SDValue LowerVectorIntExtend(SDValue Op, SelectionDAG &DAG) const;
    849 
    850     virtual SDValue
    851       LowerFormalArguments(SDValue Chain,
    852                            CallingConv::ID CallConv, bool isVarArg,
    853                            const SmallVectorImpl<ISD::InputArg> &Ins,
    854                            DebugLoc dl, SelectionDAG &DAG,
    855                            SmallVectorImpl<SDValue> &InVals) const;
    856     virtual SDValue
    857       LowerCall(CallLoweringInfo &CLI,
    858                 SmallVectorImpl<SDValue> &InVals) const;
    859 
    860     virtual SDValue
    861       LowerReturn(SDValue Chain,
    862                   CallingConv::ID CallConv, bool isVarArg,
    863                   const SmallVectorImpl<ISD::OutputArg> &Outs,
    864                   const SmallVectorImpl<SDValue> &OutVals,
    865                   DebugLoc dl, SelectionDAG &DAG) const;
    866 
    867     virtual bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const;
    868 
    869     virtual bool mayBeEmittedAsTailCall(CallInst *CI) const;
    870 
    871     virtual MVT
    872     getTypeForExtArgOrReturn(MVT VT, ISD::NodeType ExtendKind) const;
    873 
    874     virtual bool
    875     CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
    876                    bool isVarArg,
    877                    const SmallVectorImpl<ISD::OutputArg> &Outs,
    878                    LLVMContext &Context) const;
    879 
    880     /// Utility function to emit atomic-load-arith operations (and, or, xor,
    881     /// nand, max, min, umax, umin). It takes the corresponding instruction to
    882     /// expand, the associated machine basic block, and the associated X86
    883     /// opcodes for reg/reg.
    884     MachineBasicBlock *EmitAtomicLoadArith(MachineInstr *MI,
    885                                            MachineBasicBlock *MBB) const;
    886 
    887     /// Utility function to emit atomic-load-arith operations (and, or, xor,
    888     /// nand, add, sub, swap) for 64-bit operands on 32-bit target.
    889     MachineBasicBlock *EmitAtomicLoadArith6432(MachineInstr *MI,
    890                                                MachineBasicBlock *MBB) const;
    891 
    892     // Utility function to emit the low-level va_arg code for X86-64.
    893     MachineBasicBlock *EmitVAARG64WithCustomInserter(
    894                        MachineInstr *MI,
    895                        MachineBasicBlock *MBB) const;
    896 
    897     /// Utility function to emit the xmm reg save portion of va_start.
    898     MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter(
    899                                                    MachineInstr *BInstr,
    900                                                    MachineBasicBlock *BB) const;
    901 
    902     MachineBasicBlock *EmitLoweredSelect(MachineInstr *I,
    903                                          MachineBasicBlock *BB) const;
    904 
    905     MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *MI,
    906                                               MachineBasicBlock *BB) const;
    907 
    908     MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr *MI,
    909                                             MachineBasicBlock *BB,
    910                                             bool Is64Bit) const;
    911 
    912     MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI,
    913                                           MachineBasicBlock *BB) const;
    914 
    915     MachineBasicBlock *emitLoweredTLSAddr(MachineInstr *MI,
    916                                           MachineBasicBlock *BB) const;
    917 
    918     MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI,
    919                                         MachineBasicBlock *MBB) const;
    920 
    921     MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
    922                                          MachineBasicBlock *MBB) const;
    923 
    924     /// Emit nodes that will be selected as "test Op0,Op0", or something
    925     /// equivalent, for use with the given x86 condition code.
    926     SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG) const;
    927 
    928     /// Emit nodes that will be selected as "cmp Op0,Op1", or something
    929     /// equivalent, for use with the given x86 condition code.
    930     SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
    931                     SelectionDAG &DAG) const;
    932 
    933     /// Convert a comparison if required by the subtarget.
    934     SDValue ConvertCmpIfNecessary(SDValue Cmp, SelectionDAG &DAG) const;
    935   };
    936 
    937   namespace X86 {
    938     FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
    939                              const TargetLibraryInfo *libInfo);
    940   }
    941 }
    942 
    943 #endif    // X86ISELLOWERING_H
    944