| /external/llvm/include/llvm/CodeGen/ |
| MachineInstrBuilder.h | 29 namespace RegState {
69 flags & RegState::Define,
70 flags & RegState::Implicit,
71 flags & RegState::Kill,
72 flags & RegState::Dead,
73 flags & RegState::Undef,
74 flags & RegState::EarlyClobber,
76 flags & RegState::Debug,
77 flags & RegState::InternalRead));
237 .addReg(DestReg, RegState::Define)
[all...] |
| /external/llvm/lib/Target/R600/ |
| AMDGPUIndirectAddressing.cpp | 120 MOV.addReg(DstReg, RegState::Define | RegState::Implicit);
271 .addReg(Reg, RegState::Implicit);
308 Mov.addReg(IndirectReg, RegState::Implicit | RegState::Kill);
309 Mov.addReg(LiveAddressRegisterMap[Address], RegState::Implicit);
|
| SIInstrInfo.cpp | 137 Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
155 MIB.addReg(DstReg, RegState::Define);
|
| R600InstrInfo.cpp | 60 RegState::Define | RegState::Implicit);
79 MIB.addReg(DstReg, RegState::Define);
328 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
338 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
516 MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
621 .addReg(AMDGPU::AR_X, RegState::Implicit);
638 .addReg(AMDGPU::AR_X, RegState::Implicit);
|
| SILowerControlFlow.cpp | 384 .addReg(AMDGPU::M0, RegState::Implicit)
385 .addReg(Vec, RegState::Implicit);
401 .addReg(TRI->getSubReg(Dst, AMDGPU::sub0) + Off, RegState::Define)
403 .addReg(AMDGPU::M0, RegState::Implicit)
404 .addReg(Dst, RegState::Implicit);
|
| R600ISelLowering.cpp | 192 .addReg(T0, RegState::Implicit)
193 .addReg(T1, RegState::Implicit);
217 .addReg(T0, RegState::Implicit)
218 .addReg(T1, RegState::Implicit);
237 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
251 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
295 MIB.addReg(MFI->LiveOuts[i], RegState::Implicit);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FastISel.cpp | 646 .addReg(Reg, RegState::Debug).addImm(Offset)
680 .addReg(Reg, RegState::Debug).addImm(DI->getOffset())
[all...] |
| InstrEmitter.cpp | 226 MIB.addReg(VRBase, RegState::Define);
241 MIB.addReg(VRBase, RegState::Define);
253 MIB.addReg(VRBase, RegState::Define);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSERegisterInfo.cpp | 116 .addReg(Reg, RegState::Kill);
|
| Mips16InstrInfo.cpp | 94 MIB.addReg(DestReg, RegState::Define);
281 MIB2.addReg(Mips::SP, RegState::Kill);
284 MIB3.addReg(Reg2, RegState::Kill);
287 MIB4.addReg(Reg1, RegState::Kill);
373 .addReg(Reg, RegState::Kill);
|
| MipsSEInstrInfo.cpp | 145 MIB.addReg(DestReg, RegState::Define);
268 BuildMI(MBB, I, DL, get(ADDu), SP).addReg(SP).addReg(Reg, RegState::Kill);
307 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill)
|
| /external/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.cpp | 173 .addReg(ScratchReg, RegState::Kill);
179 .addReg(ScratchReg, RegState::Kill);
184 .addReg(ScratchReg, RegState::Kill);
|
| /external/llvm/lib/Target/ARM/ |
| Thumb1RegisterInfo.cpp | 123 .addReg(LdReg, RegState::Kill).setMIFlags(MIFlags);
135 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
137 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
245 AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal));
248 .addReg(BaseReg, RegState::Kill))
293 .addReg(DestReg, RegState::Kill)
321 .addReg(DestReg, RegState::Kill));
518 .addReg(ARM::R12, RegState::Define)
519 .addReg(Reg, RegState::Kill));
548 addReg(Reg, RegState::Define).addReg(ARM::R12, RegState::Kill))
[all...] |
| ARMExpandPseudoInsts.cpp | 391 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
393 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
395 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
397 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
428 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
522 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
524 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
526 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
528 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
570 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead))
[all...] |
| ARMBaseInstrInfo.cpp | [all...] |
| ARMFrameLowering.cpp | 299 .addReg(ARM::SP, RegState::Kill)
309 .addReg(ARM::SP, RegState::Kill));
312 .addReg(ARM::R4, RegState::Kill)
315 .addReg(ARM::R4, RegState::Kill));
462 addReg(JumpTarget.getReg(), RegState::Kill);
710 .addReg(ARM::SP, RegState::Define)
783 .addReg(ARM::R4, RegState::Kill)
809 .addReg(ARM::R4, RegState::Kill).addImm(16)
811 .addReg(SupReg, RegState::ImplicitKill));
[all...] |
| Thumb2InstrInfo.cpp | 209 .addReg(BaseReg, RegState::Kill)
210 .addReg(DestReg, RegState::Kill)
215 .addReg(DestReg, RegState::Kill)
216 .addReg(BaseReg, RegState::Kill)
281 .addReg(BaseReg, RegState::Kill)
|
| ARMFastISel.cpp | 310 .addReg(Op0, Op0IsKill * RegState::Kill));
313 .addReg(Op0, Op0IsKill * RegState::Kill));
330 .addReg(Op0, Op0IsKill * RegState::Kill)
331 .addReg(Op1, Op1IsKill * RegState::Kill));
334 .addReg(Op0, Op0IsKill * RegState::Kill)
335 .addReg(Op1, Op1IsKill * RegState::Kill));
353 .addReg(Op0, Op0IsKill * RegState::Kill)
354 .addReg(Op1, Op1IsKill * RegState::Kill)
355 .addReg(Op2, Op2IsKill * RegState::Kill));
358 .addReg(Op0, Op0IsKill * RegState::Kill
[all...] |
| Thumb1FrameLowering.cpp | 314 .addReg(ARM::R3, RegState::Define);
320 .addReg(ARM::R3, RegState::Kill);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 156 .addReg(SrcReg, RegState::Kill)
165 .addReg(SrcReg, RegState::Kill)
174 .addReg(SrcReg, RegState::Kill)
178 .addReg(DstReg, RegState::Kill)
415 .addReg(PPC::R0, RegState::Kill)
418 .addReg(PPC::R1, RegState::Kill)
430 .addReg(PPC::R0, RegState::Kill)
433 .addReg(PPC::R1, RegState::Kill)
451 .addReg(PPC::X1, RegState::Kill)
463 .addReg(PPC::X0, RegState::Kill
[all...] |
| PPCRegisterInfo.cpp | 230 .addReg(Reg, RegState::Kill)
242 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill);
245 .addReg(Reg, RegState::Kill)
258 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill);
302 .addReg(Reg, RegState::Kill)
506 .addReg(SReg, RegState::Kill)
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64FrameLowering.cpp | 229 MIB.addReg(JumpTarget.getReg(), RegState::Kill);
470 StLow = RegState::Define;
471 StHigh = RegState::Define;
485 State = RegState::Define;
|
| AArch64InstrInfo.cpp | 104 .addReg(AArch64::XSP, RegState::Define)
657 .addReg(SrcReg, RegState::Kill)
658 .addReg(ScratchReg, RegState::Kill)
683 .addReg(SrcReg, RegState::Kill)
693 .addReg(SrcReg, RegState::Kill)
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430FrameLowering.cpp | 67 .addReg(MSP430::FPW, RegState::Kill);
200 .addReg(Reg, RegState::Kill);
|
| /external/llvm/lib/Target/X86/ |
| X86FloatingPoint.cpp | [all...] |
