/external/llvm/lib/Target/X86/ |
X86InstrBuilder.h | 93 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0); 99 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0); 109 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); 117 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) 118 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); 127 MIB.addReg(AM.Base.Reg) [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonExpandPredSpillCode.cpp | 95 .addReg(FP).addReg(HEXAGON_RESERVED_REG_1); 97 HEXAGON_RESERVED_REG_2).addReg(SrcReg); 100 .addReg(HEXAGON_RESERVED_REG_1) 101 .addImm(0).addReg(HEXAGON_RESERVED_REG_2); 104 HEXAGON_RESERVED_REG_1).addReg(FP).addImm(Offset); 106 HEXAGON_RESERVED_REG_2).addReg(SrcReg); 109 .addReg(HEXAGON_RESERVED_REG_1) 111 .addReg(HEXAGON_RESERVED_REG_2); 115 HEXAGON_RESERVED_REG_2).addReg(SrcReg) [all...] |
HexagonSplitTFRCondSets.cpp | 108 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg1); 112 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg2); 128 addReg(MI->getOperand(1).getReg()).addReg(SrcReg1); 133 addReg(MI->getOperand(1).getReg()). 138 addReg(MI->getOperand(1).getReg()). 154 addReg(MI->getOperand(1).getReg()). 159 addReg(MI->getOperand(1).getReg()) [all...] |
HexagonRegisterInfo.cpp | 180 dstReg).addReg(FrameReg).addReg(dstReg); 184 dstReg).addReg(FrameReg).addImm(Offset); 209 resReg).addReg(FrameReg).addReg(resReg); 213 resReg).addReg(FrameReg).addImm(Offset); 229 resReg).addReg(FrameReg).addReg(resReg); 236 resReg).addReg(FrameReg).addImm(Offset); 247 dstReg).addReg(FrameReg).addReg(dstReg) [all...] |
/external/llvm/lib/Target/NVPTX/ |
NVPTXFrameLowering.cpp | 47 NVPTX::VRFrame).addReg(NVPTX::VRFrameLocal); 50 .addReg(NVPTX::VRDepot); 54 NVPTX::VRFrame).addReg(NVPTX::VRFrameLocal); 57 .addReg(NVPTX::VRDepot); 65 .addReg(NVPTX::VRDepot); 69 .addReg(NVPTX::VRDepot);
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NVPTXInstrInfo.cpp | 43 .addReg(SrcReg, getKillRegState(KillSrc)); 47 .addReg(SrcReg, getKillRegState(KillSrc)); 51 .addReg(SrcReg, getKillRegState(KillSrc)); 55 .addReg(SrcReg, getKillRegState(KillSrc)); 59 .addReg(SrcReg, getKillRegState(KillSrc)); 63 .addReg(SrcReg, getKillRegState(KillSrc)); 67 .addReg(SrcReg, getKillRegState(KillSrc)); 277 .addReg(Cond[0].getReg()).addMBB(TBB); 283 .addReg(Cond[0].getReg()).addMBB(TBB);
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/external/llvm/lib/Target/ARM/ |
ARMAsmPrinter.cpp | [all...] |
Thumb2RegisterInfo.cpp | 49 .addReg(DestReg, getDefRegState(true), SubIdx) 50 .addConstantPoolIndex(Idx).addImm((int64_t)ARMCC::AL).addReg(0)
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ARMExpandPseudoInsts.cpp | 391 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); 393 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 395 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); 397 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); 428 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 466 MIB.addReg(D0, getUndefRegState(SrcIsUndef)); 468 MIB.addReg(D1, getUndefRegState(SrcIsUndef)); 470 MIB.addReg(D2, getUndefRegState(SrcIsUndef)); 472 MIB.addReg(D3, getUndefRegState(SrcIsUndef)); 522 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)) [all...] |
Thumb2InstrInfo.cpp | 121 .addReg(SrcReg, getKillRegState(KillSrc))); 143 .addReg(SrcReg, getKillRegState(isKill)) 195 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); 200 .addReg(DestReg) 202 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); 209 .addReg(BaseReg, RegState::Kill) 210 .addReg(DestReg, RegState::Kill) 211 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) 215 .addReg(DestReg, RegState::Kill [all...] |
ARMFrameLowering.cpp | 299 .addReg(ARM::SP, RegState::Kill) 309 .addReg(ARM::SP, RegState::Kill)); 312 .addReg(ARM::R4, RegState::Kill) 315 .addReg(ARM::R4, RegState::Kill)); 330 .addReg(ARM::SP) 331 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); 335 .addReg(ARM::SP)); 410 .addReg(ARM::R4)); 416 .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0) [all...] |
/external/llvm/lib/Target/R600/ |
SILowerControlFlow.cpp | 141 .addReg(AMDGPU::EXEC); 158 .addReg(AMDGPU::EXEC); 167 .addReg(AMDGPU::VGPR0) 168 .addReg(AMDGPU::VGPR0) 169 .addReg(AMDGPU::VGPR0) 170 .addReg(AMDGPU::VGPR0); 183 .addReg(Vcc); 186 .addReg(AMDGPU::EXEC) 187 .addReg(Reg); 201 .addReg(Src); // Saved EXE [all...] |
AMDGPUIndirectAddressing.cpp | 120 MOV.addReg(DstReg, RegState::Define | RegState::Implicit); 198 Phi.addReg(Reg); 263 .addReg(Reg); 270 .addReg(AddrReg) 271 .addReg(Reg, RegState::Implicit); 298 Sequence.addReg(LiveAddressRegisterMap[Addr]); 308 Mov.addReg(IndirectReg, RegState::Implicit | RegState::Kill); 309 Mov.addReg(LiveAddressRegisterMap[Address], RegState::Implicit);
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SIInstrInfo.cpp | 71 .addReg(SrcReg, getKillRegState(KillSrc)); 77 .addReg(SrcReg, getKillRegState(KillSrc)); 99 .addReg(SrcReg, getKillRegState(KillSrc)); 134 Builder.addReg(RI.getSubReg(SrcReg, SubIdx), getKillRegState(KillSrc)); 137 Builder.addReg(DestReg, RegState::Define | RegState::Implicit); 155 MIB.addReg(DstReg, RegState::Define);
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/external/llvm/lib/Target/Sparc/ |
SparcFrameLowering.cpp | 56 .addReg(SP::O6).addImm(NumBytes); 64 .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1)); 66 .addReg(SP::O6).addReg(SP::G1); 81 BuildMI(MBB, I, dl, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size); 94 BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0) 95 .addReg(SP::G0);
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/external/llvm/lib/Target/XCore/ |
XCoreRegisterInfo.cpp | 172 .addReg(FrameReg) 173 .addReg(ScratchReg, RegState::Kill); 177 .addReg(Reg, getKillRegState(isKill)) 178 .addReg(FrameReg) 179 .addReg(ScratchReg, RegState::Kill); 183 .addReg(FrameReg) 184 .addReg(ScratchReg, RegState::Kill); 193 .addReg(FrameReg) 198 .addReg(Reg, getKillRegState(isKill)) 199 .addReg(FrameReg [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCFrameLowering.cpp | 152 .addReg(SrcReg) 156 .addReg(SrcReg, RegState::Kill) 161 .addReg(SrcReg) 165 .addReg(SrcReg, RegState::Kill) 170 .addReg(SrcReg) 174 .addReg(SrcReg, RegState::Kill) 178 .addReg(DstReg, RegState::Kill) 365 .addReg(PPC::X31) 367 .addReg(PPC::X1); 371 .addReg(PPC::X0 [all...] |
PPCRegisterInfo.cpp | 214 .addReg(PPC::R31) 219 .addReg(PPC::X1); 223 .addReg(PPC::R1); 230 .addReg(Reg, RegState::Kill) 231 .addReg(PPC::X1) 232 .addReg(MI.getOperand(1).getReg()); 235 .addReg(PPC::X1) 240 .addReg(PPC::X1) 242 .addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill); 245 .addReg(Reg, RegState::Kill [all...] |
/external/llvm/lib/Target/Mips/ |
MipsLongBranch.cpp | 233 MIB.addReg(MO.getReg()); 284 .addReg(Mips::SP).addImm(-8); 285 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA) 286 .addReg(Mips::SP).addImm(0); 295 .addReg(Mips::AT).addImm(Lo); 297 .addReg(Mips::RA).addReg(Mips::AT); 299 .addReg(Mips::SP).addImm(0); 302 .append(BuildMI(*MF, DL, TII->get(Mips::JR)).addReg(Mips::AT)) 304 .addReg(Mips::SP).addImm(8)) [all...] |
Mips16InstrInfo.cpp | 94 MIB.addReg(DestReg, RegState::Define); 97 MIB.addReg(SrcReg, getKillRegState(KillSrc)); 112 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)) 201 MIB1.addReg(Mips::SP); 205 MIB2.addReg(Mips::SP); 209 MIB3.addReg(Mips::SP); 241 MIB1.addReg(Mips::SP); 245 MIB0.addReg(Mips::A0); 248 MIB2.addReg(Mips::SP); 252 MIB3.addReg(Mips::SP) [all...] |
MipsSEInstrInfo.cpp | 145 MIB.addReg(DestReg, RegState::Define); 148 MIB.addReg(SrcReg, getKillRegState(KillSrc)); 151 MIB.addReg(ZeroReg); 177 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)) 265 BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount); 268 BuildMI(MBB, I, DL, get(ADDu), SP).addReg(SP).addReg(Reg, RegState::Kill); 302 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg) 307 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill) 329 BuildMI(MBB, I, I->getDebugLoc(), get(Opc)).addReg(Mips::RA) [all...] |
MipsSERegisterInfo.cpp | 115 BuildMI(MBB, II, DL, TII.get(ADDu), Reg).addReg(FrameReg) 116 .addReg(Reg, RegState::Kill);
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/external/llvm/include/llvm/MC/ |
MCInstBuilder.h | 32 MCInstBuilder &addReg(unsigned Reg) {
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/external/llvm/lib/Target/MSP430/ |
MSP430FrameLowering.cpp | 67 .addReg(MSP430::FPW, RegState::Kill); 71 .addReg(MSP430::SPW); 99 .addReg(MSP430::SPW).addImm(NumBytes); 157 TII.get(MSP430::MOV16rr), MSP430::SPW).addReg(MSP430::FPW); 162 .addReg(MSP430::SPW).addImm(CSSize); 171 .addReg(MSP430::SPW).addImm(NumBytes); 200 .addReg(Reg, RegState::Kill); 249 .addReg(MSP430::SPW).addImm(Amount); 258 .addReg(MSP430::SPW).addImm(Amount); 276 MSP430::SPW).addReg(MSP430::SPW).addImm(CalleeAmt) [all...] |
/external/llvm/lib/Target/MBlaze/ |
MBlazeFrameLowering.cpp | 273 .addReg(MBlaze::RMSR); 280 .addReg(MBlaze::R11); 367 .addReg(MBlaze::R1).addImm(-StackSize); 372 .addReg(MBlaze::R15).addReg(MBlaze::R1).addImm(RAOffset); 378 .addReg(MBlaze::R19).addReg(MBlaze::R1).addImm(FPOffset); 382 .addReg(MBlaze::R1).addReg(MBlaze::R0); 406 .addReg(MBlaze::R19).addReg(MBlaze::R0) [all...] |