| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 66 setTargetDAGCombine(ISD::ATOMIC_FENCE);
67 setTargetDAGCombine(ISD::ATOMIC_STORE);
70 setTargetDAGCombine(ISD::OR);
72 setTargetDAGCombine(ISD::AND);
73 setTargetDAGCombine(ISD::SRA);
76 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
77 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
78 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
81 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
82 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand)
[all...] |
| /external/llvm/lib/Target/R600/ |
| R600ISelLowering.cpp | 31 setOperationAction(ISD::MUL, MVT::i64, Expand);
38 setOperationAction(ISD::FADD, MVT::v4f32, Expand);
39 setOperationAction(ISD::FMUL, MVT::v4f32, Expand);
40 setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
41 setOperationAction(ISD::FSUB, MVT::v4f32, Expand);
43 setOperationAction(ISD::ADD, MVT::v4i32, Expand);
44 setOperationAction(ISD::AND, MVT::v4i32, Expand);
45 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Expand);
46 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Expand);
47 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Expand)
[all...] |
| SIISelLowering.cpp | 61 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand);
62 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand);
63 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand);
64 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand);
66 setOperationAction(ISD::ADD, MVT::i64, Legal);
67 setOperationAction(ISD::ADD, MVT::i32, Legal);
69 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
70 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
72 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
73 setTargetDAGCombine(ISD::SELECT_CC)
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeFloatTypes.cpp | 60 case ISD::MERGE_VALUES:R = SoftenFloatRes_MERGE_VALUES(N, ResNo); break;
61 case ISD::BITCAST: R = SoftenFloatRes_BITCAST(N); break;
62 case ISD::BUILD_PAIR: R = SoftenFloatRes_BUILD_PAIR(N); break;
63 case ISD::ConstantFP:
66 case ISD::EXTRACT_VECTOR_ELT:
68 case ISD::FABS: R = SoftenFloatRes_FABS(N); break;
69 case ISD::FADD: R = SoftenFloatRes_FADD(N); break;
70 case ISD::FCEIL: R = SoftenFloatRes_FCEIL(N); break;
71 case ISD::FCOPYSIGN: R = SoftenFloatRes_FCOPYSIGN(N); break;
72 case ISD::FCOS: R = SoftenFloatRes_FCOS(N); break
[all...] |
| SelectionDAGBuilder.cpp | 97 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
98 /// (ISD::AssertSext).
103 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
134 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
135 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
141 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
155 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
156 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
159 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo)
[all...] |
| LegalizeTypesGeneric.cpp | 54 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
55 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
61 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
62 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
68 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
69 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
74 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
75 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
82 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
84 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonCallingConvLower.h | 38 ISD::ArgFlagsTy ArgFlags, Hexagon_CCState &State,
78 /// AnalyzeFormalArguments - Analyze an ISD::FORMAL_ARGUMENTS node,
80 void AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
83 /// AnalyzeReturn - Analyze the returned values of an ISD::RET node,
85 void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
88 /// AnalyzeCallOperands - Analyze an ISD::CALL node, incorporating info
90 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
97 SmallVectorImpl<ISD::ArgFlagsTy> &Flags,
100 /// AnalyzeCallResult - Analyze the return values of an ISD::CALL node,
102 void AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins
[all...] |
| HexagonCallingConvLower.cpp | 44 ISD::ArgFlagsTy ArgFlags) {
63 /// AnalyzeFormalArguments - Analyze an ISD::FORMAL_ARGUMENTS node,
66 Hexagon_CCState::AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg>
82 ISD::ArgFlagsTy ArgFlags = Ins[i].Flags;
91 /// AnalyzeReturn - Analyze the returned values of an ISD::RET node,
94 Hexagon_CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
118 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
128 /// AnalyzeCallOperands - Analyze an ISD::CALL node, incorporating info
131 Hexagon_CCState::AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg>
148 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags
[all...] |
| HexagonISelLowering.h | 26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
89 SmallVectorImpl<ISD::OutputArg> &Outs,
91 const SmallVectorImpl<ISD::InputArg> &Ins,
106 const SmallVectorImpl<ISD::InputArg> &Ins,
117 const SmallVectorImpl<ISD::InputArg> &Ins,
131 const SmallVectorImpl<ISD::OutputArg> &Outs,
147 ISD::MemIndexedMode &AM,
|
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 103 return DAG.getNode(ISD::ADD, DL, Ty,
120 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
139 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
211 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
212 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
213 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
216 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
223 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
226 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
227 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom)
[all...] |
| Mips16ISelDAGToDAG.cpp | 123 case ISD::LOAD: {
134 case ISD::STORE: {
173 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
174 Addr.getOpcode() == ISD::TargetGlobalAddress))
196 if (Addr.getOpcode() == ISD::ADD) {
245 case ISD::SUBE:
246 case ISD::ADDE: {
249 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
250 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 87 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
88 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
89 setOperationAction(ISD::ADDC, MVT::i32, Expand);
90 setOperationAction(ISD::ADDE, MVT::i32, Expand);
91 setOperationAction(ISD::SUBC, MVT::i32, Expand);
92 setOperationAction(ISD::SUBE, MVT::i32, Expand);
95 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
98 setOperationAction(ISD::ADD, MVT::i64, Custom);
99 setOperationAction(ISD::SUB, MVT::i64, Custom);
100 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 96 setOperationAction(ISD::LOAD, VT, Promote);
97 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
99 setOperationAction(ISD::STORE, VT, Promote);
100 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
105 setOperationAction(ISD::SETCC, VT, Custom);
106 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
107 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
109 setOperationAction(ISD::SINT_TO_FP, VT, Custom);
110 setOperationAction(ISD::UINT_TO_FP, VT, Custom);
111 setOperationAction(ISD::FP_TO_SINT, VT, Custom)
[all...] |
| ARMSelectionDAGInfo.cpp | 67 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
74 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
79 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
85 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
106 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
115 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
129 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
136 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
171 Src = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src);
173 Src = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Src)
[all...] |
| /external/llvm/lib/CodeGen/ |
| CallingConvLower.cpp | 45 ISD::ArgFlagsTy ArgFlags) {
67 CCState::AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
73 ISD::ArgFlagsTy ArgFlags = Ins[i].Flags;
86 bool CCState::CheckReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
91 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
100 void CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
105 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
118 void CCState::AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
123 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
137 SmallVectorImpl<ISD::ArgFlagsTy> &Flags
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 80 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
81 Addr.getOpcode() == ISD::TargetGlobalAddress)
84 if (Addr.getOpcode() == ISD::ADD) {
115 if (Addr.getOpcode() == ISD::FrameIndex) return false;
116 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
117 Addr.getOpcode() == ISD::TargetGlobalAddress)
120 if (Addr.getOpcode() == ISD::ADD) {
147 case ISD::SDIV:
148 case ISD::UDIV: {
155 if (N->getOpcode() == ISD::SDIV)
[all...] |
| SparcISelLowering.h | 24 FIRST_NUMBER = ISD::BUILTIN_OP_END,
74 const SmallVectorImpl<ISD::InputArg> &Ins,
85 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 41 ISD::ArgFlagsTy &ArgFlags,
46 ISD::ArgFlagsTy &ArgFlags,
51 ISD::ArgFlagsTy &ArgFlags,
91 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
92 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
97 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
98 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
99 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
100 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
101 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal)
[all...] |
| PPCISelLowering.h | 27 FIRST_NUMBER = ISD::BUILTIN_OP_END,
247 STD_32 = ISD::FIRST_TARGET_MEMORY_OPCODE,
334 /// getSetCCResultType - Return the ISD::SETCC ValueType
342 ISD::MemIndexedMode &AM,
470 const SmallVectorImpl<ISD::InputArg> &Ins,
514 const SmallVectorImpl<ISD::InputArg> &Ins,
525 const SmallVectorImpl<ISD::InputArg> &Ins,
531 const SmallVectorImpl<ISD::InputArg> &Ins,
542 const SmallVectorImpl<ISD::OutputArg> &Outs,
548 const SmallVectorImpl<ISD::OutputArg> &Outs
[all...] |
| PPCTargetTransformInfo.cpp | 197 int ISD = TLI->InstructionOpcodeToISD(Opcode);
198 assert(ISD && "Invalid opcode");
210 if (ISD == ISD::EXTRACT_VECTOR_ELT ||
211 ISD == ISD::INSERT_VECTOR_ELT)
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 25 FIRST_NUMBER = ISD::BUILTIN_OP_END,
130 const SmallVectorImpl<ISD::OutputArg> &Outs,
132 const SmallVectorImpl<ISD::InputArg> &Ins,
139 const SmallVectorImpl<ISD::InputArg> &Ins,
146 const SmallVectorImpl<ISD::InputArg> &Ins,
153 const SmallVectorImpl<ISD::InputArg> &Ins,
163 const SmallVectorImpl<ISD::OutputArg> &Outs,
170 ISD::MemIndexedMode &AM,
|
| MSP430ISelDAGToDAG.cpp | 189 case ISD::Constant: {
200 case ISD::FrameIndex:
209 case ISD::ADD: {
223 case ISD::OR:
303 ISD::MemIndexedMode AM = LD->getAddressingMode();
304 if (AM != ISD::POST_INC || LD->getExtensionType() != ISD::NON_EXTLOAD)
356 if (N1.getOpcode() == ISD::LOAD &&
403 case ISD::FrameIndex: {
413 case ISD::LOAD
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelDAGToDAG.cpp | 102 if (Opc != ISD::Constant)
122 if (N.getOpcode() == ISD::FrameIndex) return false;
123 if (N.getOpcode() == ISD::TargetExternalSymbol ||
124 N.getOpcode() == ISD::TargetGlobalAddress)
128 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::OR) {
132 if (N.getOperand(0).getOpcode() == ISD::TargetJumpTable ||
133 N.getOperand(1).getOpcode() == ISD::TargetJumpTable)
153 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::OR)
[all...] |
| MBlazeISelLowering.h | 63 // Start the numbering from where ISD NodeType finishes.
64 FIRST_NUMBER = ISD::BUILTIN_OP_END,
104 /// getSetCCResultType - get the ISD::SETCC result ValueType
115 const SmallVectorImpl<ISD::InputArg> &Ins,
130 const SmallVectorImpl<ISD::InputArg> &Ins,
141 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /external/llvm/include/llvm/CodeGen/ |
| CallingConvLower.h | 137 ISD::ArgFlagsTy ArgFlags, CCState &State);
144 ISD::ArgFlagsTy &ArgFlags, CCState &State);
197 void AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
202 void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
208 bool CheckReturn(const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
213 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
219 SmallVectorImpl<ISD::ArgFlagsTy> &Flags,
224 void AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
307 int MinSize, int MinAlign, ISD::ArgFlagsTy ArgFlags);
|
