| /external/llvm/examples/Kaleidoscope/MCJIT/lazy/ |
| toy-jit.cpp | 137 char Opcode;
140 UnaryExprAST(char opcode, ExprAST *operand)
141 : Opcode(opcode), Operand(operand) {}
643 Function *F = TheHelper->getFunction(MakeLegalFunctionName(std::string("unary")+Opcode));
645 Function *F = TheModule->getFunction(std::string("unary")+Opcode);
[all...] |
| toy.cpp | 137 char Opcode;
140 UnaryExprAST(char opcode, ExprAST *operand)
141 : Opcode(opcode), Operand(operand) {}
929 Function *F = TheHelper->getFunction(MakeLegalFunctionName(std::string("unary")+Opcode));
[all...] |
| /external/llvm/lib/Analysis/ |
| InstructionSimplify.cpp | 124 /// it into "(A op B) op' (A op C)". Here "op" is given by Opcode and "op'" is
128 static Value *ExpandBinOp(unsigned Opcode, Value *LHS, Value *RHS,
142 if (Value *L = SimplifyBinOp(Opcode, A, C, Q, MaxRecurse))
143 if (Value *R = SimplifyBinOp(Opcode, B, C, Q, MaxRecurse)) {
165 if (Value *L = SimplifyBinOp(Opcode, A, B, Q, MaxRecurse))
166 if (Value *R = SimplifyBinOp(Opcode, A, C, Q, MaxRecurse)) {
185 /// FactorizeBinOp - Simplify "LHS Opcode RHS" by factorizing out a common term
186 /// using the operation OpCodeToExtract. For example, when Opcode is Add and
189 static Value *FactorizeBinOp(unsigned Opcode, Value *LHS, Value *RHS,
215 if (Value *V = SimplifyBinOp(Opcode, B, DD, Q, MaxRecurse))
[all...] |
| ValueTracking.cpp | 667 unsigned Opcode = LU->getOpcode();
671 if (Opcode == Instruction::Add ||
672 Opcode == Instruction::Sub ||
673 Opcode == Instruction::And ||
674 Opcode == Instruction::Or ||
675 Opcode == Instruction::Mul) {
[all...] |
| /external/llvm/lib/CodeGen/ |
| MachineLICM.cpp | 102 // For each opcode, keep a list of potential CSE instructions.
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGRRList.cpp | 273 /// opcode to determine what register class is being generated.
296 unsigned Opcode = Node->getMachineOpcode();
297 if (Opcode == TargetOpcode::REG_SEQUENCE) {
306 const MCInstrDesc Desc = TII->get(Opcode);
[all...] |
| /external/llvm/lib/MC/ |
| MCDwarf.cpp | 37 // First special line opcode - leave room for the standard opcodes.
42 // Minimum line offset in a special line info. opcode. This value
46 // Range of line offsets in a special line info. opcode.
280 // Standard opcode lengths
367 uint64_t Temp, Opcode;
392 // If the line increment is out of range of a special opcode, we must encode
403 // Use DW_LNS_copy instead of a "line +0, addr +0" special opcode.
409 // Bias the opcode by the special opcode base.
414 // Try using a special opcode
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMAsmPrinter.cpp | [all...] |
| ARMCodeEmitter.cpp | 284 unsigned Reloc = (MCID.Opcode == ARM::MOVi16 ?
364 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
433 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
875 unsigned Opcode = MI.getDesc().Opcode;
[all...] |
| ARMConstantIslandPass.cpp | 232 /// opcode.
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelDAGToDAG.cpp | 95 SDNode *SelectIndexedLoadZeroExtend64(LoadSDNode *LD, unsigned Opcode,
97 SDNode *SelectIndexedLoadSignExtend64(LoadSDNode *LD, unsigned Opcode,
389 unsigned Opcode = 0;
405 // Figure out base + offset opcode
406 if (LoadedVT == MVT::i64) Opcode = Hexagon::LDrid_indexed;
407 else if (LoadedVT == MVT::i32) Opcode = Hexagon::LDriw_indexed;
408 else if (LoadedVT == MVT::i16) Opcode = Hexagon::LDrih_indexed;
409 else if (LoadedVT == MVT::i8) Opcode = Hexagon::LDrib_indexed;
414 SDNode* Result = CurDAG->getMachineNode(Opcode, dl,
433 unsigned Opcode,
[all...] |
| /external/llvm/lib/Target/PowerPC/AsmParser/ |
| PPCAsmParser.cpp | 203 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
571 int Opcode = Inst.getOpcode();
572 switch (Opcode) {
627 TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
641 TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
655 TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
670 TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
684 TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
697 TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
710 TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 97 /// rotate and mask opcode and mask operation.
165 /// Reg in an asm, because the load or store opcode would have to change.
325 // opcode and that it has a immediate integer right operand.
366 unsigned Opcode = N->getOpcode();
371 if (Opcode == ISD::SHL) {
376 } else if (Opcode == ISD::SRL) {
383 } else if (Opcode == ISD::ROTL) {
[all...] |
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | 405 static SDNode *findUser(SDValue Value, unsigned Opcode) {
414 if (I->getOpcode() == Opcode)
786 int Opcode = Node->getMachineOpcode();
789 const MCInstrDesc *Desc = &TII->get(Opcode);
794 // Commuted opcode if available
795 int OpcodeRev = Desc->isCommutable() ? TII->commuteOpcode(Opcode) : -1;
802 int OpcodeE64 = AMDGPU::getVOPe64(Opcode);
917 if (Desc->Opcode == Opcode && !isNodeChanged(Node, Ops)) {
922 return DAG.getMachineNode(Desc->Opcode, SDLoc(Node), Node->getVTList(), Ops)
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelDAGToDAG.cpp | 101 // given by Opcode. The operands are: Input (R2), Start (I3), End (I4) and
113 : Opcode(Op), BitSize(N.getValueType().getSizeInBits()),
117 unsigned Opcode;
265 // Try to use RISBG or Opcode to implement OR or XOR node N.
267 SDNode *tryRxSBG(SDNode *N, unsigned Opcode);
271 // (Opcode UpperVal LowerVal)
275 // (Opcode (Opcode Op0 UpperVal) LowerVal)
276 SDNode *splitLargeImmediate(unsigned Opcode, SDNode *Node, SDValue Op0,
383 unsigned Opcode = N.getOpcode()
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineAddSub.cpp | 355 unsigned Opcode = I->getOpcode();
357 if (Opcode == Instruction::FAdd || Opcode == Instruction::FSub) {
380 if (Opcode == Instruction::FSub)
[all...] |
| /external/llvm/utils/TableGen/ |
| DAGISelMatcher.h | 60 CheckOpcode, // Fail if not opcode.
61 SwitchOpcode, // Dispatch based on opcode.
446 /// specified opcode, if not it fails to match.
448 const SDNodeInfo &Opcode;
450 CheckOpcodeMatcher(const SDNodeInfo &opcode)
451 : Matcher(CheckOpcode), Opcode(opcode) {}
453 const SDNodeInfo &getOpcode() const { return Opcode; }
468 /// SwitchOpcodeMatcher - Switch based on the current node's opcode, dispatching
469 /// to one matcher per opcode. If the opcode doesn't match any of the cases
[all...] |
| /sdk/emulator/qtools/ |
| opcode.h | 9 // the opflags[] array in opcode.cpp.
10 enum Opcode {
113 // Define bit flags for the opcode categories
132 inline bool isALU(Opcode op) { return (opcode_flags[op] & kCatAlu) != 0; }
133 inline bool isBranch(Opcode op) { return (opcode_flags[op] & kCatBranch) != 0; }
134 inline bool isBranchLink(Opcode op) {
137 inline bool isBranchExch(Opcode op) {
140 inline bool isLoad(Opcode op) { return (opcode_flags[op] & kCatLoad) != 0; }
141 inline bool isLoadMultiple(Opcode op) {
144 inline bool isStoreMultiple(Opcode op)
[all...] |
| /art/compiler/utils/arm/ |
| constants_arm.h | 129 enum Opcode {
279 inline Opcode OpcodeField() const {
280 return static_cast<Opcode>(Bits(kOpcodeShift, kOpcodeBits));
|
| /external/chromium_org/third_party/mesa/src/src/mesa/program/ |
| prog_instruction.h | 340 gl_inst_opcode Opcode;
439 _mesa_num_inst_src_regs(gl_inst_opcode opcode);
442 _mesa_num_inst_dst_regs(gl_inst_opcode opcode);
445 _mesa_is_tex_instruction(gl_inst_opcode opcode);
451 _mesa_opcode_string(gl_inst_opcode opcode);
|
| /external/javassist/src/main/javassist/bytecode/ |
| Opcode.java | 26 public interface Opcode {
440 0, // wide, 196 depends on the following opcode
|
| /external/llvm/examples/Kaleidoscope/MCJIT/cached/ |
| toy.cpp | 158 char Opcode;
161 UnaryExprAST(char opcode, ExprAST *operand)
162 : Opcode(opcode), Operand(operand) {}
1031 Function *F = TheHelper->getFunction(MakeLegalFunctionName(std::string("unary")+Opcode));
[all...] |
| /external/llvm/examples/Kaleidoscope/MCJIT/complete/ |
| toy.cpp | 182 char Opcode;
185 UnaryExprAST(char opcode, ExprAST *operand)
186 : Opcode(opcode), Operand(operand) {}
[all...] |
| /external/llvm/examples/Kaleidoscope/MCJIT/initial/ |
| toy.cpp | 135 char Opcode;
138 UnaryExprAST(char opcode, ExprAST *operand)
139 : Opcode(opcode), Operand(operand) {}
889 Function *F = TheHelper->getFunction(MakeLegalFunctionName(std::string("unary")+Opcode));
[all...] |
| /external/llvm/include/llvm/MC/ |
| MCExpr.h | 305 enum Opcode {
313 Opcode Op;
316 MCUnaryExpr(Opcode _Op, const MCExpr *_Expr)
323 static const MCUnaryExpr *Create(Opcode Op, const MCExpr *Expr,
343 Opcode getOpcode() const { return Op; }
358 enum Opcode {
384 Opcode Op;
387 MCBinaryExpr(Opcode _Op, const MCExpr *_LHS, const MCExpr *_RHS)
394 static const MCBinaryExpr *Create(Opcode Op, const MCExpr *LHS,
474 Opcode getOpcode() const { return Op;
[all...] |
