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  /external/valgrind/main/exp-bbv/tests/
Makefile.am 20 SUBDIRS += arm-linux
23 DIST_SUBDIRS = x86 x86-linux amd64-linux ppc32-linux arm-linux .
  /external/valgrind/main/exp-sgcheck/tests/
is_arch_supported 4 # and ARM are not supported and will fail these tests as follows:
13 ppc*|arm*|s390x) exit 1;;
  /ndk/tests/build/stlport-src-suffix/jni/
Android.mk 10 LOCAL_SRC_FILES := test_stlport.cpp.arm
22 LOCAL_SRC_FILES := test_stlport.cpp.arm.neon
  /external/llvm/lib/Target/ARM/
ARMLoadStoreOptimizer.cpp 1 //===-- ARMLoadStoreOptimizer.cpp - ARM load / store opt. pass ------------===//
15 #define DEBUG_TYPE "arm-ldst-opt"
16 #include "ARM.h"
75 return "ARM load / store optimization pass";
140 case ARM::LDRi12:
144 case ARM_AM::ia: return ARM::LDMIA;
145 case ARM_AM::da: return ARM::LDMDA;
146 case ARM_AM::db: return ARM::LDMDB;
147 case ARM_AM::ib: return ARM::LDMIB;
149 case ARM::STRi12
    [all...]
Thumb1RegisterInfo.cpp 16 #include "ARM.h"
50 if (ARM::tGPRRegClass.hasSubClassEq(RC))
51 return &ARM::tGPRRegClass;
58 return &ARM::tGPRRegClass;
78 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRpci))
111 if (DestReg == ARM::SP) {
112 assert(BaseReg == ARM::SP && "Unexpected!");
113 LdReg = MF.getRegInfo().createVirtualRegister(&ARM::tGPRRegClass);
117 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
120 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg)
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Thumb1FrameLowering.cpp 27 // stack frame. ARM (especially Thumb) has small immediate offset to
42 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
70 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
73 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
123 case ARM::R4:
124 case ARM::R5:
125 case ARM::R6
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ARMISelDAGToDAG.cpp 1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
10 // This file defines an instruction selector for the ARM target.
14 #define DEBUG_TYPE "arm-isel"
15 #include "ARM.h"
52 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
77 return "ARM Instruction Selection";
201 /// ARM.
239 /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM.
242 /// SelectCMOVOp - Select CMOV instructions for ARM
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  /prebuilts/ndk/9/sources/cxx-stl/EH/gabi++/libs/armeabi/
libgabi++_static.a 29 ????????? ???? ??F????N10__cxxabiv117__array_type_infoEGCC: (GNU) 4.6 20120106 (prerelease)A,aeabi"5TE ,.symtab.strtab.shstrtab.text.data.bss.ARM.extab.text._ZNK10__cxxabiv117__array_type_info9can_catchEPKNS_16__shim_type_infoERPv.rel.ARM.exidx.text._ZNK10__cxxabiv117__array_type_info9can_catchEPKNS_16__shim_type_infoERPv.rel.text._ZN10__cxxabiv117__array_type_infoD2Ev.ARM.extab.text._ZN10__cxxabiv117__array_type_infoD2Ev.rel.ARM.exidx.text._ZN10__cxxabiv117__array_type_infoD2Ev.rel.text._ZN10__cxxabiv117__array_type_infoD0Ev.ARM.extab.text._ZN10__cxxabiv117__array_type_infoD0Ev.rel.ARM.exidx.text._ZN10__cxxabiv117__array_type_infoD0Ev.rodata._ZTSN10__cxxabiv117__array_type_infoE.rel.data.rel.ro._ZTVN10__cxxabiv117__array_type_infoE.rel.data.rel.ro._ZTIN10__cxxabiv117__array_type_infoE.comment.note.GNU-stack.ARM.attributes4!4'464,8?p?8?  @? XPp?XL 0  ?`? @  ?t?p?t ? P *|$\?X ` ?? ? ? ?0?&???p?-??? 0 ???
60 ????GCC: (GNU) 4.6 20120106 (prerelease)A,aeabi"5TE ,.symtab.strtab.shstrtab.text.data.bss.rel.text.__cxa_bad_cast.ARM.extab.text.__cxa_bad_cast.rel.ARM.exidx.text.__cxa_bad_cast.rel.text.__cxa_bad_typeid.ARM.extab.text.__cxa_bad_typeid.rel.ARM.exidx.text.__cxa_bad_typeid.comment.note.GNU-stack.ARM.att (…)
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  /prebuilts/ndk/9/sources/cxx-stl/EH/gabi++/libs/armeabi-v7a/
libgabi++_static.a 23 ,.symtab.strtab.shstrtab.text.data.bss.ARM.extab.text._ZNK10__cxxabiv117__array_type_info9can_catchEPKNS_16__shim_type_infoERPv.rel.ARM.exidx.text._ZNK10__cxxabiv117__array_type_info9can_catchEPKNS_16__shim_type_infoERPv.rel.text._ZN10__cxxabiv117__array_type_infoD2Ev.ARM.extab.text._ZN10__cxxabiv117__array_type_infoD2Ev.rel.ARM.exidx.text._ZN10__cxxabiv117__array_type_infoD2Ev.rel.text._ZN10__cxxabiv117__array_type_infoD0Ev.ARM.extab.text._ZN10__cxxabiv117__array_type_infoD0Ev.rel.ARM.exidx.text._ZN10__cxxabiv117__array_type_infoD0Ev.rodata._ZTSN10__cxxabiv117__array_type_infoE.rel.data.rel.ro._ZTVN10__cxxabiv117__array_type_infoE.rel.data.rel.ro._ZTIN10__cxxabiv117__array_type_infoE.comment.note.GNU-stack.ARM.attributes4!4'464,8?p?8?  @? $ XPp?XL 4  ?`? D  ?t?p?t ? T *|$\?X d ?? ? ? ?0?&???p?3??? 4 ???
52 ,.symtab.strtab.shstrtab.text.data.bss.rel.text.__cxa_bad_cast.ARM.extab.text.__cxa_bad_cast.rel.ARM.exidx.text.__cxa_bad_cast.rel.text.__cxa_bad_typeid.ARM.extab.text.__cxa_bad_typeid.rel.ARM.exidx.text.__cxa_bad_typeid.comment.note.GNU-stack.ARM.att (…)
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  /external/llvm/test/CodeGen/ARM/
vst1.ll 1 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
8 call void @llvm.arm.neon.vst1.v8i8(i8* %A, <8 x i8> %tmp1, i32 16)
17 call void @llvm.arm.neon.vst1.v4i16(i8* %tmp0, <4 x i16> %tmp1, i32 1)
26 call void @llvm.arm.neon.vst1.v2i32(i8* %tmp0, <2 x i32> %tmp1, i32 1)
35 call void @llvm.arm.neon.vst1.v2f32(i8* %tmp0, <2 x float> %tmp1, i32 1)
46 call void @llvm.arm.neon.vst1.v2f32(i8* %tmp0, <2 x float> %tmp1, i32 1)
57 call void @llvm.arm.neon.vst1.v1i64(i8* %tmp0, <1 x i64> %tmp1, i32 1)
66 call void @llvm.arm.neon.vst1.v16i8(i8* %A, <16 x i8> %tmp1, i32 8)
76 call void @llvm.arm.neon.vst1.v8i16(i8* %tmp0, <8 x i16> %tmp1, i32 32)
87 call void @llvm.arm.neon.vst1.v8i16(i8* %tmp0, <8 x i16> %tmp1, i32 8
    [all...]
vst2.ll 1 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
8 call void @llvm.arm.neon.vst2.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 8)
18 call void @llvm.arm.neon.vst2.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 4)
30 call void @llvm.arm.neon.vst2.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 32)
39 call void @llvm.arm.neon.vst2.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1)
48 call void @llvm.arm.neon.vst2.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, i32 1)
58 call void @llvm.arm.neon.vst2.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 32)
69 call void @llvm.arm.neon.vst2.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 8)
80 call void @llvm.arm.neon.vst2.v16i8(i8* %A, <16 x i8> %tmp1, <16 x i8> %tmp1, i32 8)
90 call void @llvm.arm.neon.vst2.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 16
    [all...]
vpminmax.ll 1 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
8 %tmp3 = call <8 x i8> @llvm.arm.neon.vpmins.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
17 %tmp3 = call <4 x i16> @llvm.arm.neon.vpmins.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
26 %tmp3 = call <2 x i32> @llvm.arm.neon.vpmins.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
35 %tmp3 = call <8 x i8> @llvm.arm.neon.vpminu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
44 %tmp3 = call <4 x i16> @llvm.arm.neon.vpminu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
53 %tmp3 = call <2 x i32> @llvm.arm.neon.vpminu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
62 %tmp3 = call <2 x float> @llvm.arm.neon.vpmins.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
66 declare <8 x i8> @llvm.arm.neon.vpmins.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
67 declare <4 x i16> @llvm.arm.neon.vpmins.v4i16(<4 x i16>, <4 x i16>) nounwind readnon
    [all...]
vst3.ll 1 ; RUN: llc < %s -march=arm -mattr=+neon -fast-isel=0 -O0 | FileCheck %s
9 call void @llvm.arm.neon.vst3.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 32)
18 call void @llvm.arm.neon.vst3.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1)
27 call void @llvm.arm.neon.vst3.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1)
38 call void @llvm.arm.neon.vst3.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1)
49 call void @llvm.arm.neon.vst3.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1)
60 call void @llvm.arm.neon.vst3.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 16)
71 call void @llvm.arm.neon.vst3.v16i8(i8* %A, <16 x i8> %tmp1, <16 x i8> %tmp1, <16 x i8> %tmp1, i32 32)
81 call void @llvm.arm.neon.vst3.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1)
93 call void @llvm.arm.neon.vst3.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1
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  /external/clang/test/Preprocessor/
stdint.c 1 // RUN: %clang_cc1 -E -ffreestanding -triple=arm-none-none %s | FileCheck -check-prefix ARM %s
3 // ARM:typedef signed long long int int64_t;
4 // ARM:typedef unsigned long long int uint64_t;
5 // ARM:typedef int64_t int_least64_t;
6 // ARM:typedef uint64_t uint_least64_t;
7 // ARM:typedef int64_t int_fast64_t;
8 // ARM:typedef uint64_t uint_fast64_t;
10 // ARM:typedef signed int int32_t;
11 // ARM:typedef unsigned int uint32_t
    [all...]
  /external/pixman/pixman/
Makefile.am 55 # arm simd code
57 noinst_LTLIBRARIES += libpixman-arm-simd.la
59 pixman-arm-simd.c \
60 pixman-arm-common.h \
61 pixman-arm-simd-asm.S \
62 pixman-arm-simd-asm-scaled.S \
63 pixman-arm-simd-asm.h
64 libpixman_1_la_LIBADD += libpixman-arm-simd.la
69 # arm neon code
71 noinst_LTLIBRARIES += libpixman-arm-neon.l
    [all...]
  /external/llvm/lib/Target/ARM/AsmParser/
ARMAsmParser.cpp 1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
147 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
150 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
153 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
156 return STI.getFeatureBits() & ARM::HasV4TOps;
159 return STI.getFeatureBits() & ARM::HasV6Ops;
162 return STI.getFeatureBits() & ARM::HasV7Ops;
165 return STI.getFeatureBits() & ARM::HasV8Ops;
168 return !(STI.getFeatureBits() & ARM::FeatureNoARM);
172 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb))
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  /external/llvm/test/CodeGen/AArch64/
neon-aba-abd.ll 3 declare <8 x i8> @llvm.arm.neon.vabdu.v8i8(<8 x i8>, <8 x i8>)
4 declare <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8>, <8 x i8>)
8 %abd = call <8 x i8> @llvm.arm.neon.vabdu.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
15 %abd = call <8 x i8> @llvm.arm.neon.vabdu.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
23 %abd = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
30 %abd = call <8 x i8> @llvm.arm.neon.vabds.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
36 declare <16 x i8> @llvm.arm.neon.vabdu.v16i8(<16 x i8>, <16 x i8>)
37 declare <16 x i8> @llvm.arm.neon.vabds.v16i8(<16 x i8>, <16 x i8>)
41 %abd = call <16 x i8> @llvm.arm.neon.vabdu.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
48 %abd = call <16 x i8> @llvm.arm.neon.vabdu.v16i8(<16 x i8> %lhs, <16 x i8> %rhs
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  /external/valgrind/main/VEX/auxprogs/
genoffsets.c 148 // arm
149 GENOFFSET(ARM,arm,R0);
150 GENOFFSET(ARM,arm,R1);
151 GENOFFSET(ARM,arm,R2);
152 GENOFFSET(ARM,arm,R3);
153 GENOFFSET(ARM,arm,R4)
    [all...]
  /external/v8/src/
SConscript 144 'arch:arm': Split("""
145 arm/builtins-arm.cc
146 arm/code-stubs-arm.cc
147 arm/codegen-arm.cc
148 arm/constants-arm.cc
149 arm/cpu-arm.c
    [all...]
  /build/core/combo/arch/arm/
armv5te-vfp.mk 6 include $(BUILD_COMBOS)/arch/arm/armv5te.mk
armv5te.mk 1 # Configuration for Linux on ARM.
  /development/ndk/platforms/android-3/arch-arm/lib-bootstrap/
libdl.so 
  /development/tools/yuv420sp2rgb/
Android.mk 8 ifeq ($(TARGET_ARCH),arm)
  /external/chromium_org/ppapi/native_client/tests/ppapi_browser/bad/
ppapi_bad_crossorigin.nmf 5 "arm": {"url": "http://www.google.com/crossorigin.nexe"}
  /external/chromium_org/third_party/skia/src/opts/
opts_check_arm.cpp 10 * 2011-04-01 ARM
12 * Modified to return ARM version of memset16 and memset32 if no neon
32 // FIXME: memset.arm.S is using syntax incompatible with XCode
49 // FIXME: memset.arm.S is using syntax incompatible with XCode

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