| /external/llvm/include/llvm/MC/ |
| MCInstBuilder.h | 33 Inst.addOperand(MCOperand::CreateReg(Reg));
39 Inst.addOperand(MCOperand::CreateImm(Val));
45 Inst.addOperand(MCOperand::CreateFPImm(Val));
51 Inst.addOperand(MCOperand::CreateExpr(Val));
57 Inst.addOperand(MCOperand::CreateInst(Val));
|
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/AsmParser/ |
| PPCAsmParser.cpp | 391 Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()]));
396 Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()]));
401 Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()]));
406 Inst.addOperand(MCOperand::CreateReg(XRegsNoX0[getReg()]));
425 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
430 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
435 Inst.addOperand(MCOperand::CreateReg(VRegs[getReg()]));
440 Inst.addOperand(MCOperand::CreateReg(CRBITRegs[getCRBit()]));
445 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCCReg()]));
450 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCRBitMask()]))
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| R600ISelLowering.cpp | 66 .addOperand(MI->getOperand(0))
67 .addOperand(MI->getOperand(1))
77 .addOperand(MI->getOperand(0))
78 .addOperand(MI->getOperand(1))
89 .addOperand(MI->getOperand(0))
90 .addOperand(MI->getOperand(1))
102 .addOperand(MI->getOperand(0))
135 .addOperand(MI->getOperand(1))
139 .addOperand(MI->getOperand(0))
161 .addOperand(MI->getOperand(3)
[all...] |
| SIISelLowering.cpp | 83 .addOperand(MI->getOperand(0))
84 .addOperand(MI->getOperand(1))
87 .addOperand(MI->getOperand(1))
88 .addOperand(MI->getOperand(1))
98 .addOperand(MI->getOperand(0))
99 .addOperand(MI->getOperand(1))
102 .addOperand(MI->getOperand(1))
103 .addOperand(MI->getOperand(1))
113 .addOperand(MI->getOperand(0))
114 .addOperand(MI->getOperand(1)
[all...] |
| AMDGPUMCInstLower.cpp | 54 OutMI.addOperand(MCOp);
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600ISelLowering.cpp | 66 .addOperand(MI->getOperand(0))
67 .addOperand(MI->getOperand(1))
77 .addOperand(MI->getOperand(0))
78 .addOperand(MI->getOperand(1))
89 .addOperand(MI->getOperand(0))
90 .addOperand(MI->getOperand(1))
102 .addOperand(MI->getOperand(0))
135 .addOperand(MI->getOperand(1))
139 .addOperand(MI->getOperand(0))
161 .addOperand(MI->getOperand(3)
[all...] |
| SIISelLowering.cpp | 83 .addOperand(MI->getOperand(0))
84 .addOperand(MI->getOperand(1))
87 .addOperand(MI->getOperand(1))
88 .addOperand(MI->getOperand(1))
98 .addOperand(MI->getOperand(0))
99 .addOperand(MI->getOperand(1))
102 .addOperand(MI->getOperand(1))
103 .addOperand(MI->getOperand(1))
113 .addOperand(MI->getOperand(0))
114 .addOperand(MI->getOperand(1)
[all...] |
| AMDGPUMCInstLower.cpp | 54 OutMI.addOperand(MCOp);
|
| /external/llvm/lib/Target/ARM/ |
| ARMInstrInfo.cpp | 39 NopInst.addOperand(MCOperand::CreateImm(0));
40 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
41 NopInst.addOperand(MCOperand::CreateReg(0));
44 NopInst.addOperand(MCOperand::CreateReg(ARM::R0));
45 NopInst.addOperand(MCOperand::CreateReg(ARM::R0));
46 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
47 NopInst.addOperand(MCOperand::CreateReg(0));
48 NopInst.addOperand(MCOperand::CreateReg(0));
|
| Thumb1InstrInfo.cpp | 31 NopInst.addOperand(MCOperand::CreateReg(ARM::R8));
32 NopInst.addOperand(MCOperand::CreateReg(ARM::R8));
33 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
34 NopInst.addOperand(MCOperand::CreateReg(0));
|
| ARMExpandPseudoInsts.cpp | 81 UseMI.addOperand(MO);
83 DefMI.addOperand(MO);
400 MIB.addOperand(MI.getOperand(OpIdx++));
403 MIB.addOperand(MI.getOperand(OpIdx++));
404 MIB.addOperand(MI.getOperand(OpIdx++));
407 MIB.addOperand(MI.getOperand(OpIdx++));
417 MIB.addOperand(MI.getOperand(OpIdx++));
418 MIB.addOperand(MI.getOperand(OpIdx++));
425 MIB.addOperand(MO);
452 MIB.addOperand(MI.getOperand(OpIdx++))
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstrBuilder.h | 68 MI->addOperand(*MF, MachineOperand::CreateReg(RegNo,
84 MI->addOperand(*MF, MachineOperand::CreateImm(Val));
89 MI->addOperand(*MF, MachineOperand::CreateCImm(Val));
94 MI->addOperand(*MF, MachineOperand::CreateFPImm(Val));
100 MI->addOperand(*MF, MachineOperand::CreateMBB(MBB, TargetFlags));
105 MI->addOperand(*MF, MachineOperand::CreateFI(Idx));
112 MI->addOperand(*MF, MachineOperand::CreateCPI(Idx, Offset, TargetFlags));
118 MI->addOperand(*MF, MachineOperand::CreateTargetIndex(Idx, Offset,
125 MI->addOperand(*MF, MachineOperand::CreateJTI(Idx, TargetFlags));
132 MI->addOperand(*MF, MachineOperand::CreateGA(GV, Offset, TargetFlags))
[all...] |
| /external/llvm/lib/Target/SystemZ/Disassembler/ |
| SystemZDisassembler.cpp | 59 Inst.addOperand(MCOperand::CreateReg(RegNo));
108 Inst.addOperand(MCOperand::CreateImm(Imm));
115 Inst.addOperand(MCOperand::CreateImm(SignExtend64<N>(Imm)));
169 Inst.addOperand(MCOperand::CreateImm(SignExtend64<N>(Imm) * 2 + Address));
190 Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base]));
191 Inst.addOperand(MCOperand::CreateImm(Disp));
200 Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base]));
201 Inst.addOperand(MCOperand::CreateImm(SignExtend64<20>(Disp)));
211 Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base]));
212 Inst.addOperand(MCOperand::CreateImm(Disp))
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonSplitConst32AndConst64.cpp | 89 TII->get(Hexagon::LO), DestReg).addOperand(Symbol);
91 TII->get(Hexagon::HI), DestReg).addOperand(Symbol);
102 TII->get(Hexagon::LO_jt), DestReg).addOperand(Symbol);
104 TII->get(Hexagon::HI_jt), DestReg).addOperand(Symbol);
115 TII->get(Hexagon::LO_label), DestReg).addOperand(Symbol);
117 TII->get(Hexagon::HI_label), DestReg).addOperand(Symbol);
|
| /external/llvm/lib/Target/Mips/Disassembler/ |
| MipsDisassembler.cpp | 347 Inst.addOperand(MCOperand::CreateReg(Reg));
358 Inst.addOperand(MCOperand::CreateReg(Reg));
377 Inst.addOperand(MCOperand::CreateReg(Reg));
389 Inst.addOperand(MCOperand::CreateReg(Reg));
400 Inst.addOperand(MCOperand::CreateReg(Reg));
411 Inst.addOperand(MCOperand::CreateReg(Reg));
427 Inst.addOperand(MCOperand::CreateReg(Reg));
430 Inst.addOperand(MCOperand::CreateReg(Reg));
431 Inst.addOperand(MCOperand::CreateReg(Base));
432 Inst.addOperand(MCOperand::CreateImm(Offset))
[all...] |
| /external/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.cpp | 252 Inst.addOperand(MCOperand::CreateReg(Register));
263 Inst.addOperand(MCOperand::CreateReg(Register));
274 Inst.addOperand(MCOperand::CreateReg(Register));
285 Inst.addOperand(MCOperand::CreateReg(Register));
296 Inst.addOperand(MCOperand::CreateReg(Register));
307 Inst.addOperand(MCOperand::CreateReg(Register));
319 Inst.addOperand(MCOperand::CreateReg(Register));
330 Inst.addOperand(MCOperand::CreateReg(Register));
342 Inst.addOperand(MCOperand::CreateReg(Register));
353 Inst.addOperand(MCOperand::CreateReg(Register))
[all...] |
| /external/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | 277 Inst.addOperand(MCOperand::CreateReg(getReg()));
283 Inst.addOperand(MCOperand::CreateImm(0));
285 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
287 Inst.addOperand(MCOperand::CreateExpr(Expr));
299 Inst.addOperand(MCOperand::CreateReg(getMemBase()));
379 Inst.addOperand(MCOperand::CreateReg(Reg.RegNum));
453 NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
454 NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO));
455 NopInst.addOperand(MCOperand::CreateImm(0));
540 tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()))
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86MCInstLower.cpp | 231 OutMI.addOperand(OutMI.getOperand(0));
232 OutMI.addOperand(OutMI.getOperand(0));
254 Inst.addOperand(Saved);
333 Inst.addOperand(Saved);
375 OutMI.addOperand(MCOp);
458 OutMI.addOperand(Saved);
484 OutMI.addOperand(Saved);
601 OutMI.addOperand(MCOperand::CreateReg(X86::R10));
602 OutMI.addOperand(MCOperand::CreateReg(X86::RAX));
645 LEA.addOperand(MCOperand::CreateReg(X86::RDI)); // des
[all...] |
| /external/chromium_org/third_party/skia/src/pathops/ |
| SkOpEdgeBuilder.h | 41 void addOperand(const SkPath& path);
|
| /external/skia/src/pathops/ |
| SkOpEdgeBuilder.h | 41 void addOperand(const SkPath& path);
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZLongBranch.cpp | 346 .addOperand(MI->getOperand(0))
347 .addOperand(MI->getOperand(1))
352 .addOperand(MI->getOperand(2));
365 .addOperand(MI->getOperand(0))
366 .addOperand(MI->getOperand(1));
369 .addOperand(MI->getOperand(2))
370 .addOperand(MI->getOperand(3));
|
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | [all...] |
| /external/llvm/lib/Target/X86/Disassembler/ |
| X86Disassembler.cpp | 167 mcInst.addOperand(MCOperand::CreateReg(llvmRegnum));
284 mcInst.addOperand(MCOperand::CreateReg(X86::XMM0 + (immediate >> 4)));
287 mcInst.addOperand(MCOperand::CreateReg(X86::YMM0 + (immediate >> 4)));
290 mcInst.addOperand(MCOperand::CreateReg(X86::ZMM0 + (immediate >> 4)));
322 mcInst.addOperand(MCOperand::CreateImm(immediate));
353 mcInst.addOperand(MCOperand::CreateReg(X86::x)); break;
534 mcInst.addOperand(baseReg);
535 mcInst.addOperand(scaleAmount);
536 mcInst.addOperand(indexReg);
540 mcInst.addOperand(displacement)
[all...] |
| /external/llvm/lib/Target/R600/ |
| AMDGPUMCInstLower.cpp | 60 OutMI.addOperand(MCOp);
|
