| /external/llvm/lib/Target/MSP430/ |
| MSP430InstrFormats.td | 54 class MSP430Inst<dag outs, dag ins, SizeVal sz, Format f,
60 dag OutOperandList = outs;
78 dag outs, dag ins, string asmstr, list<dag> pattern>
79 : MSP430Inst<outs, ins, sz, DoubleOpFrm, asmstr> {
93 dag outs, dag ins, string asmstr, list<dag> pattern>
94 : IForm<opcode, dest, 1, src, sz, outs, ins, asmstr, pattern>;
97 dag outs, dag ins, string asmstr, list<dag> pattern>
98 : IForm8<opcode, DstReg, SrcReg, Size2Bytes, outs, ins, asmstr, pattern>;
101 dag outs, dag ins, string asmstr, list<dag> pattern>
102 : IForm8<opcode, DstReg, SrcImm, Size4Bytes, outs, ins, asmstr, pattern>
[all...] |
| MSP430InstrInfo.td | 116 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i16imm:$amt),
119 def ADJCALLSTACKUP : Pseudo<(outs), (ins i16imm:$amt1, i16imm:$amt2),
125 def Select8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$src2, i8imm:$cc),
129 def Select16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR16:$src2, i8imm:$cc),
134 def Shl8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt),
137 def Shl16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR8:$cnt),
140 def Sra8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt),
143 def Sra16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR8:$cnt),
146 def Srl8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt),
149 def Srl16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR8:$cnt)
[all...] |
| /external/llvm/tools/macho-dump/ |
| macho-dump.cpp | 58 outs() << " ('segment_name', '";
59 outs().write_escaped(Name, /*UseHexEscapes=*/true) << "')\n";
60 outs() << " ('vm_addr', " << VMAddr << ")\n";
61 outs() << " ('vm_size', " << VMSize << ")\n";
62 outs() << " ('file_offset', " << FileOffset << ")\n";
63 outs() << " ('file_size', " << FileSize << ")\n";
64 outs() << " ('maxprot', " << MaxProt << ")\n";
65 outs() << " ('initprot', " << InitProt << ")\n";
66 outs() << " ('num_sections', " << NumSections << ")\n";
67 outs() << " ('flags', " << Flags << ")\n"
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrFPStack.td | 78 def FP32_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP32:$src),
80 def FP32_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP32:$src),
82 def FP32_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP32:$src),
84 def FP64_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP64:$src),
86 def FP64_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP64:$src),
88 def FP64_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP64:$src),
90 def FP80_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP80:$src),
92 def FP80_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP80:$src),
94 def FP80_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP80:$src),
118 def FpPOP_RETVAL : FpI_<(outs RFP80:$dst), (ins), SpecialFP, []>
[all...] |
| X86InstrFormats.td | 165 class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
177 dag OutOperandList = outs;
254 class I<bits<8> o, Format f, dag outs, dag ins, string asm,
257 : X86Inst<o, f, NoImm, outs, ins, asm, itin, d> {
261 class Ii8 <bits<8> o, Format f, dag outs, dag ins, string asm,
264 : X86Inst<o, f, Imm8, outs, ins, asm, itin, d> {
268 class Ii8PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
270 : X86Inst<o, f, Imm8PCRel, outs, ins, asm, itin> {
274 class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm,
276 : X86Inst<o, f, Imm16, outs, ins, asm, itin>
[all...] |
| X86InstrSystem.td | 18 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)], IIC_RDTSC>,
22 def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
27 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
28 def UD2B : I<0xB9, RawFrm, (outs), (ins), "ud2b", []>, TB;
31 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", [], IIC_HLT>;
32 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", [], IIC_RSM>, TB;
36 def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>;
37 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3",
50 def INT : Ii8<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap",
54 def SYSCALL : I<0x05, RawFrm, (outs), (ins), "syscall", [], IIC_SYSCALL>, TB
[all...] |
| X86InstrControl.td | 24 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
27 def RETW : I <0xC3, RawFrm, (outs), (ins),
30 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
33 def RETIW : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt),
36 def LRETL : I <0xCB, RawFrm, (outs), (ins),
38 def LRETW : I <0xCB, RawFrm, (outs), (ins),
40 def LRETQ : RI <0xCB, RawFrm, (outs), (ins),
42 def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
44 def LRETIW : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
50 def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst)
[all...] |
| X86InstrVMX.td | 19 def INVEPT32 : I<0x80, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
22 def INVEPT64 : I<0x80, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
26 def INVVPID32 : I<0x81, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
29 def INVVPID64 : I<0x81, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
33 def VMCALL : I<0x01, MRM_C1, (outs), (ins), "vmcall", []>, TB;
34 def VMCLEARm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
37 def VMFUNC : I<0x01, MRM_D4, (outs), (ins), "vmfunc", []>, TB;
39 def VMLAUNCH : I<0x01, MRM_C2, (outs), (ins), "vmlaunch", []>, TB;
41 def VMRESUME : I<0x01, MRM_C3, (outs), (ins), "vmresume", []>, TB;
42 def VMPTRLDm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs)
[all...] |
| X86InstrShiftRotate.td | 20 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
23 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
26 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
29 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
34 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
39 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
43 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
46 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst),
55 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
57 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1)
[all...] |
| X86InstrSVM.td | 19 def VMMCALL : I<0x01, MRM_D9, (outs), (ins), "vmmcall", []>, TB;
22 def STGI : I<0x01, MRM_DC, (outs), (ins), "stgi", []>, TB;
25 def CLGI : I<0x01, MRM_DD, (outs), (ins), "clgi", []>, TB;
29 def SKINIT : I<0x01, MRM_DE, (outs), (ins), "skinit\t{%eax|eax}", []>, TB;
33 def VMRUN32 : I<0x01, MRM_D8, (outs), (ins),
36 def VMRUN64 : I<0x01, MRM_D8, (outs), (ins),
41 def VMLOAD32 : I<0x01, MRM_DA, (outs), (ins),
44 def VMLOAD64 : I<0x01, MRM_DA, (outs), (ins),
49 def VMSAVE32 : I<0x01, MRM_DB, (outs), (ins),
52 def VMSAVE64 : I<0x01, MRM_DB, (outs), (ins)
[all...] |
| X86InstrExtension.td | 16 def CBW : I<0x98, RawFrm, (outs), (ins),
19 def CWDE : I<0x98, RawFrm, (outs), (ins),
23 def CWD : I<0x99, RawFrm, (outs), (ins),
26 def CDQ : I<0x99, RawFrm, (outs), (ins),
31 def CDQE : RI<0x98, RawFrm, (outs), (ins),
35 def CQO : RI<0x99, RawFrm, (outs), (ins),
43 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
47 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
51 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8:$src),
55 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src)
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrFormats.td | 13 class InstXCore<int sz, dag outs, dag ins, string asmstr, list<dag> pattern>
18 dag OutOperandList = outs;
27 class PseudoInstXCore<dag outs, dag ins, string asmstr, list<dag> pattern>
28 : InstXCore<0, outs, ins, asmstr, pattern> {
36 class _F3R<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
37 : InstXCore<2, outs, ins, asmstr, pattern> {
45 class _F3RImm<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
46 : _F3R<opc, outs, ins, asmstr, pattern> {
50 class _FL3R<bits<9> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
51 : InstXCore<4, outs, ins, asmstr, pattern>
[all...] |
| XCoreInstrInfo.td | 204 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
207 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
213 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
215 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
221 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
224 def _2rus : _F2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
230 _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
235 _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
242 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
245 def _l2rus : _FL2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c)
[all...] |
| /dalvik/dx/tests/051-dex-explicit-null/ |
| expected.txt | 2 regs: 0001; ins: 0000; outs: 0000
6 regs: 0003; ins: 0001; outs: 0000
|
| /external/llvm/tools/llvm-objdump/ |
| COFFDump.cpp | 97 outs() << format(" 0x%02x: ", unsigned(UCs[0].u.CodeOffset))
101 outs() << " " << getUnwindRegisterName(UCs[0].getOpInfo());
105 outs() << " " << UCs[1].FrameOffset;
107 outs() << " " << UCs[1].FrameOffset
112 outs() << " " << ((UCs[0].getOpInfo() + 1) * 8);
115 outs() << " ";
118 outs() << " " << getUnwindRegisterName(UCs[0].getOpInfo())
122 outs() << " " << getUnwindRegisterName(UCs[0].getOpInfo())
127 outs() << " XMM" << static_cast<uint32_t>(UCs[0].getOpInfo())
131 outs() << " XMM" << UCs[0].getOpInfo(
[all...] |
| ELFDump.cpp | 28 outs() << "Program Header:\n";
34 outs() << " LOAD ";
37 outs() << " STACK ";
40 outs() << "EH_FRAME ";
43 outs() << " INTERP ";
46 outs() << " DYNAMIC ";
49 outs() << " PHDR ";
52 outs() << " TLS ";
55 outs() << " UNKNOWN ";
60 outs() << "off
[all...] |
| /dalvik/dx/tests/055-dex-explicit-throw/ |
| expected.txt | 2 regs: 0001; ins: 0000; outs: 0000
6 regs: 0002; ins: 0000; outs: 0000
|
| /dalvik/dx/tests/063-dex-empty-switch/ |
| expected.txt | 2 regs: 0005; ins: 0002; outs: 0000
10 regs: 0005; ins: 0002; outs: 0000
|
| /dalvik/dx/tests/111-use-null-as-array/ |
| expected.txt | 2 regs: 0002; ins: 0000; outs: 0000
8 regs: 0002; ins: 0000; outs: 0000
14 regs: 0002; ins: 0000; outs: 0000
20 regs: 0002; ins: 0000; outs: 0000
26 regs: 0002; ins: 0000; outs: 0000
32 regs: 0002; ins: 0000; outs: 0000
38 regs: 0002; ins: 0000; outs: 0000
44 regs: 0002; ins: 0000; outs: 0000
50 regs: 0002; ins: 0000; outs: 0000
56 regs: 0002; ins: 0000; outs: 000
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrFormats.td | 20 class A64Inst<dag outs, dag ins, string asmstr, list<dag> patterns,
38 let OutOperandList = outs;
45 class PseudoInst<dag outs, dag ins, list<dag> patterns> : Instruction {
48 let OutOperandList = outs;
57 class A64PseudoInst<dag outs, dag ins, list<dag> patterns>
58 : PseudoInst<outs, ins, patterns> {
64 class A64PseudoExpand<dag outs, dag ins, list<dag> patterns, dag Result>
65 : A64PseudoInst<outs, ins, patterns>,
71 class A64InstRd<dag outs, dag ins, string asmstr,
73 : A64Inst<outs, ins, asmstr, patterns, itin>
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrFormats.td | 85 class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
90 dag OutOperandList = outs;
181 class LDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
183 : InstHexagon<outs, ins, asmstr, pattern, cstr, LD, TypeLD>;
186 class LDInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [],
188 : LDInst<outs, ins, asmstr, pattern, cstr>;
190 class CONSTLDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
192 : LDInst<outs, ins, asmstr, pattern, cstr>;
196 class LDInstPost<dag outs, dag ins, string asmstr, list<dag> pattern = [],
198 : LDInst<outs, ins, asmstr, pattern, cstr>
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrFormats.td | 10 class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern>
19 dag OutOperandList = outs;
30 class F2<dag outs, dag ins, string asmstr, list<dag> pattern>
31 : InstSP<outs, ins, asmstr, pattern> {
41 class F2_1<bits<3> op2Val, dag outs, dag ins, string asmstr, list<dag> pattern>
42 : F2<outs, ins, asmstr, pattern> {
50 class F2_2<bits<4> condVal, bits<3> op2Val, dag outs, dag ins, string asmstr,
51 list<dag> pattern> : F2<outs, ins, asmstr, pattern> {
66 class F3<dag outs, dag ins, string asmstr, list<dag> pattern>
67 : InstSP<outs, ins, asmstr, pattern>
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstr64Bit.td | 86 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
90 def BCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
97 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>,
102 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
104 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
109 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
111 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
121 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func),
124 def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func),
127 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func)
[all...] |
| /dalvik/dx/tests/049-dex-instanceof/ |
| expected.txt | 2 regs: 0003; ins: 0001; outs: 0000
|
| /dalvik/dx/tests/050-dex-checkcast/ |
| expected.txt | 2 regs: 0003; ins: 0001; outs: 0000
|
