1 //===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef POWERPC_INSTRUCTIONINFO_H 15 #define POWERPC_INSTRUCTIONINFO_H 16 17 #include "PPC.h" 18 #include "PPCRegisterInfo.h" 19 #include "llvm/Target/TargetInstrInfo.h" 20 21 #define GET_INSTRINFO_HEADER 22 #include "PPCGenInstrInfo.inc" 23 24 namespace llvm { 25 26 /// PPCII - This namespace holds all of the PowerPC target-specific 27 /// per-instruction flags. These must match the corresponding definitions in 28 /// PPC.td and PPCInstrFormats.td. 29 namespace PPCII { 30 enum { 31 // PPC970 Instruction Flags. These flags describe the characteristics of the 32 // PowerPC 970 (aka G5) dispatch groups and how they are formed out of 33 // raw machine instructions. 34 35 /// PPC970_First - This instruction starts a new dispatch group, so it will 36 /// always be the first one in the group. 37 PPC970_First = 0x1, 38 39 /// PPC970_Single - This instruction starts a new dispatch group and 40 /// terminates it, so it will be the sole instruction in the group. 41 PPC970_Single = 0x2, 42 43 /// PPC970_Cracked - This instruction is cracked into two pieces, requiring 44 /// two dispatch pipes to be available to issue. 45 PPC970_Cracked = 0x4, 46 47 /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that 48 /// an instruction is issued to. 49 PPC970_Shift = 3, 50 PPC970_Mask = 0x07 << PPC970_Shift 51 }; 52 enum PPC970_Unit { 53 /// These are the various PPC970 execution unit pipelines. Each instruction 54 /// is one of these. 55 PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction 56 PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit 57 PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit 58 PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit 59 PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit 60 PPC970_VALU = 5 << PPC970_Shift, // Vector ALU 61 PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit 62 PPC970_BRU = 7 << PPC970_Shift // Branch Unit 63 }; 64 } // end namespace PPCII 65 66 67 class PPCInstrInfo : public PPCGenInstrInfo { 68 PPCTargetMachine &TM; 69 const PPCRegisterInfo RI; 70 71 bool StoreRegToStackSlot(MachineFunction &MF, 72 unsigned SrcReg, bool isKill, int FrameIdx, 73 const TargetRegisterClass *RC, 74 SmallVectorImpl<MachineInstr*> &NewMIs, 75 bool &NonRI, bool &SpillsVRS) const; 76 bool LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL, 77 unsigned DestReg, int FrameIdx, 78 const TargetRegisterClass *RC, 79 SmallVectorImpl<MachineInstr*> &NewMIs, 80 bool &NonRI, bool &SpillsVRS) const; 81 public: 82 explicit PPCInstrInfo(PPCTargetMachine &TM); 83 84 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 85 /// such, whenever a client has an instance of instruction info, it should 86 /// always be able to get register info as well (through this method). 87 /// 88 virtual const PPCRegisterInfo &getRegisterInfo() const { return RI; } 89 90 ScheduleHazardRecognizer * 91 CreateTargetHazardRecognizer(const TargetMachine *TM, 92 const ScheduleDAG *DAG) const; 93 ScheduleHazardRecognizer * 94 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, 95 const ScheduleDAG *DAG) const; 96 97 bool isCoalescableExtInstr(const MachineInstr &MI, 98 unsigned &SrcReg, unsigned &DstReg, 99 unsigned &SubIdx) const; 100 unsigned isLoadFromStackSlot(const MachineInstr *MI, 101 int &FrameIndex) const; 102 unsigned isStoreToStackSlot(const MachineInstr *MI, 103 int &FrameIndex) const; 104 105 // commuteInstruction - We can commute rlwimi instructions, but only if the 106 // rotate amt is zero. We also have to munge the immediates a bit. 107 virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const; 108 109 virtual void insertNoop(MachineBasicBlock &MBB, 110 MachineBasicBlock::iterator MI) const; 111 112 113 // Branch analysis. 114 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 115 MachineBasicBlock *&FBB, 116 SmallVectorImpl<MachineOperand> &Cond, 117 bool AllowModify) const; 118 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 119 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 120 MachineBasicBlock *FBB, 121 const SmallVectorImpl<MachineOperand> &Cond, 122 DebugLoc DL) const; 123 124 // Select analysis. 125 virtual bool canInsertSelect(const MachineBasicBlock&, 126 const SmallVectorImpl<MachineOperand> &Cond, 127 unsigned, unsigned, int&, int&, int&) const; 128 virtual void insertSelect(MachineBasicBlock &MBB, 129 MachineBasicBlock::iterator MI, DebugLoc DL, 130 unsigned DstReg, 131 const SmallVectorImpl<MachineOperand> &Cond, 132 unsigned TrueReg, unsigned FalseReg) const; 133 134 virtual void copyPhysReg(MachineBasicBlock &MBB, 135 MachineBasicBlock::iterator I, DebugLoc DL, 136 unsigned DestReg, unsigned SrcReg, 137 bool KillSrc) const; 138 139 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 140 MachineBasicBlock::iterator MBBI, 141 unsigned SrcReg, bool isKill, int FrameIndex, 142 const TargetRegisterClass *RC, 143 const TargetRegisterInfo *TRI) const; 144 145 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 146 MachineBasicBlock::iterator MBBI, 147 unsigned DestReg, int FrameIndex, 148 const TargetRegisterClass *RC, 149 const TargetRegisterInfo *TRI) const; 150 151 virtual 152 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 153 154 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, 155 unsigned Reg, MachineRegisterInfo *MRI) const; 156 157 // If conversion by predication (only supported by some branch instructions). 158 // All of the profitability checks always return true; it is always 159 // profitable to use the predicated branches. 160 virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, 161 unsigned NumCycles, unsigned ExtraPredCycles, 162 const BranchProbability &Probability) const { 163 return true; 164 } 165 166 virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, 167 unsigned NumT, unsigned ExtraT, 168 MachineBasicBlock &FMBB, 169 unsigned NumF, unsigned ExtraF, 170 const BranchProbability &Probability) const; 171 172 virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, 173 unsigned NumCycles, 174 const BranchProbability 175 &Probability) const { 176 return true; 177 } 178 179 virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, 180 MachineBasicBlock &FMBB) const { 181 return false; 182 } 183 184 // Predication support. 185 bool isPredicated(const MachineInstr *MI) const; 186 187 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 188 189 virtual 190 bool PredicateInstruction(MachineInstr *MI, 191 const SmallVectorImpl<MachineOperand> &Pred) const; 192 193 virtual 194 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 195 const SmallVectorImpl<MachineOperand> &Pred2) const; 196 197 virtual bool DefinesPredicate(MachineInstr *MI, 198 std::vector<MachineOperand> &Pred) const; 199 200 virtual bool isPredicable(MachineInstr *MI) const; 201 202 // Comparison optimization. 203 204 205 virtual bool analyzeCompare(const MachineInstr *MI, 206 unsigned &SrcReg, unsigned &SrcReg2, 207 int &Mask, int &Value) const; 208 209 virtual bool optimizeCompareInstr(MachineInstr *CmpInstr, 210 unsigned SrcReg, unsigned SrcReg2, 211 int Mask, int Value, 212 const MachineRegisterInfo *MRI) const; 213 214 /// GetInstSize - Return the number of bytes of code the specified 215 /// instruction may be. This returns the maximum number of bytes. 216 /// 217 virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const; 218 }; 219 220 } 221 222 #endif 223
