1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that Mips uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 #define DEBUG_TYPE "mips-lower" 15 #include "MipsISelLowering.h" 16 #include "InstPrinter/MipsInstPrinter.h" 17 #include "MCTargetDesc/MipsBaseInfo.h" 18 #include "MipsMachineFunction.h" 19 #include "MipsSubtarget.h" 20 #include "MipsTargetMachine.h" 21 #include "MipsTargetObjectFile.h" 22 #include "llvm/ADT/Statistic.h" 23 #include "llvm/CodeGen/CallingConvLower.h" 24 #include "llvm/CodeGen/MachineFrameInfo.h" 25 #include "llvm/CodeGen/MachineFunction.h" 26 #include "llvm/CodeGen/MachineInstrBuilder.h" 27 #include "llvm/CodeGen/MachineRegisterInfo.h" 28 #include "llvm/CodeGen/SelectionDAGISel.h" 29 #include "llvm/CodeGen/ValueTypes.h" 30 #include "llvm/IR/CallingConv.h" 31 #include "llvm/IR/DerivedTypes.h" 32 #include "llvm/IR/GlobalVariable.h" 33 #include "llvm/Support/CommandLine.h" 34 #include "llvm/Support/Debug.h" 35 #include "llvm/Support/ErrorHandling.h" 36 #include "llvm/Support/raw_ostream.h" 37 38 using namespace llvm; 39 40 STATISTIC(NumTailCalls, "Number of tail calls"); 41 42 static cl::opt<bool> 43 LargeGOT("mxgot", cl::Hidden, 44 cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false)); 45 46 static cl::opt<bool> 47 NoZeroDivCheck("mno-check-zero-division", cl::Hidden, 48 cl::desc("MIPS: Don't trap on integer division by zero."), 49 cl::init(false)); 50 51 static const uint16_t O32IntRegs[4] = { 52 Mips::A0, Mips::A1, Mips::A2, Mips::A3 53 }; 54 55 static const uint16_t Mips64IntRegs[8] = { 56 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, 57 Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64 58 }; 59 60 static const uint16_t Mips64DPRegs[8] = { 61 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, 62 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64 63 }; 64 65 // If I is a shifted mask, set the size (Size) and the first bit of the 66 // mask (Pos), and return true. 67 // For example, if I is 0x003ff800, (Pos, Size) = (11, 11). 68 static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) { 69 if (!isShiftedMask_64(I)) 70 return false; 71 72 Size = CountPopulation_64(I); 73 Pos = countTrailingZeros(I); 74 return true; 75 } 76 77 SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const { 78 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>(); 79 return DAG.getRegister(FI->getGlobalBaseReg(), Ty); 80 } 81 82 static SDValue getTargetNode(SDValue Op, SelectionDAG &DAG, unsigned Flag) { 83 EVT Ty = Op.getValueType(); 84 85 if (GlobalAddressSDNode *N = dyn_cast<GlobalAddressSDNode>(Op)) 86 return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(Op), Ty, 0, 87 Flag); 88 if (ExternalSymbolSDNode *N = dyn_cast<ExternalSymbolSDNode>(Op)) 89 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag); 90 if (BlockAddressSDNode *N = dyn_cast<BlockAddressSDNode>(Op)) 91 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag); 92 if (JumpTableSDNode *N = dyn_cast<JumpTableSDNode>(Op)) 93 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag); 94 if (ConstantPoolSDNode *N = dyn_cast<ConstantPoolSDNode>(Op)) 95 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(), 96 N->getOffset(), Flag); 97 98 llvm_unreachable("Unexpected node type."); 99 return SDValue(); 100 } 101 102 static SDValue getAddrNonPIC(SDValue Op, SelectionDAG &DAG) { 103 SDLoc DL(Op); 104 EVT Ty = Op.getValueType(); 105 SDValue Hi = getTargetNode(Op, DAG, MipsII::MO_ABS_HI); 106 SDValue Lo = getTargetNode(Op, DAG, MipsII::MO_ABS_LO); 107 return DAG.getNode(ISD::ADD, DL, Ty, 108 DAG.getNode(MipsISD::Hi, DL, Ty, Hi), 109 DAG.getNode(MipsISD::Lo, DL, Ty, Lo)); 110 } 111 112 SDValue MipsTargetLowering::getAddrLocal(SDValue Op, SelectionDAG &DAG, 113 bool HasMips64) const { 114 SDLoc DL(Op); 115 EVT Ty = Op.getValueType(); 116 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT; 117 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty), 118 getTargetNode(Op, DAG, GOTFlag)); 119 SDValue Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT, 120 MachinePointerInfo::getGOT(), false, false, false, 121 0); 122 unsigned LoFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO; 123 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty, getTargetNode(Op, DAG, LoFlag)); 124 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo); 125 } 126 127 SDValue MipsTargetLowering::getAddrGlobal(SDValue Op, SelectionDAG &DAG, 128 unsigned Flag) const { 129 SDLoc DL(Op); 130 EVT Ty = Op.getValueType(); 131 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty), 132 getTargetNode(Op, DAG, Flag)); 133 return DAG.getLoad(Ty, DL, DAG.getEntryNode(), Tgt, 134 MachinePointerInfo::getGOT(), false, false, false, 0); 135 } 136 137 SDValue MipsTargetLowering::getAddrGlobalLargeGOT(SDValue Op, SelectionDAG &DAG, 138 unsigned HiFlag, 139 unsigned LoFlag) const { 140 SDLoc DL(Op); 141 EVT Ty = Op.getValueType(); 142 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, Ty, getTargetNode(Op, DAG, HiFlag)); 143 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty)); 144 SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi, 145 getTargetNode(Op, DAG, LoFlag)); 146 return DAG.getLoad(Ty, DL, DAG.getEntryNode(), Wrapper, 147 MachinePointerInfo::getGOT(), false, false, false, 0); 148 } 149 150 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { 151 switch (Opcode) { 152 case MipsISD::JmpLink: return "MipsISD::JmpLink"; 153 case MipsISD::TailCall: return "MipsISD::TailCall"; 154 case MipsISD::Hi: return "MipsISD::Hi"; 155 case MipsISD::Lo: return "MipsISD::Lo"; 156 case MipsISD::GPRel: return "MipsISD::GPRel"; 157 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer"; 158 case MipsISD::Ret: return "MipsISD::Ret"; 159 case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN"; 160 case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; 161 case MipsISD::FPCmp: return "MipsISD::FPCmp"; 162 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; 163 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; 164 case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP"; 165 case MipsISD::ExtractLOHI: return "MipsISD::ExtractLOHI"; 166 case MipsISD::InsertLOHI: return "MipsISD::InsertLOHI"; 167 case MipsISD::Mult: return "MipsISD::Mult"; 168 case MipsISD::Multu: return "MipsISD::Multu"; 169 case MipsISD::MAdd: return "MipsISD::MAdd"; 170 case MipsISD::MAddu: return "MipsISD::MAddu"; 171 case MipsISD::MSub: return "MipsISD::MSub"; 172 case MipsISD::MSubu: return "MipsISD::MSubu"; 173 case MipsISD::DivRem: return "MipsISD::DivRem"; 174 case MipsISD::DivRemU: return "MipsISD::DivRemU"; 175 case MipsISD::DivRem16: return "MipsISD::DivRem16"; 176 case MipsISD::DivRemU16: return "MipsISD::DivRemU16"; 177 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; 178 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; 179 case MipsISD::Wrapper: return "MipsISD::Wrapper"; 180 case MipsISD::Sync: return "MipsISD::Sync"; 181 case MipsISD::Ext: return "MipsISD::Ext"; 182 case MipsISD::Ins: return "MipsISD::Ins"; 183 case MipsISD::LWL: return "MipsISD::LWL"; 184 case MipsISD::LWR: return "MipsISD::LWR"; 185 case MipsISD::SWL: return "MipsISD::SWL"; 186 case MipsISD::SWR: return "MipsISD::SWR"; 187 case MipsISD::LDL: return "MipsISD::LDL"; 188 case MipsISD::LDR: return "MipsISD::LDR"; 189 case MipsISD::SDL: return "MipsISD::SDL"; 190 case MipsISD::SDR: return "MipsISD::SDR"; 191 case MipsISD::EXTP: return "MipsISD::EXTP"; 192 case MipsISD::EXTPDP: return "MipsISD::EXTPDP"; 193 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H"; 194 case MipsISD::EXTR_W: return "MipsISD::EXTR_W"; 195 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W"; 196 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W"; 197 case MipsISD::SHILO: return "MipsISD::SHILO"; 198 case MipsISD::MTHLIP: return "MipsISD::MTHLIP"; 199 case MipsISD::MULT: return "MipsISD::MULT"; 200 case MipsISD::MULTU: return "MipsISD::MULTU"; 201 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP"; 202 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP"; 203 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP"; 204 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP"; 205 case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP"; 206 case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP"; 207 case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP"; 208 case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP"; 209 case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP"; 210 default: return NULL; 211 } 212 } 213 214 MipsTargetLowering:: 215 MipsTargetLowering(MipsTargetMachine &TM) 216 : TargetLowering(TM, new MipsTargetObjectFile()), 217 Subtarget(&TM.getSubtarget<MipsSubtarget>()), 218 HasMips64(Subtarget->hasMips64()), IsN64(Subtarget->isABI_N64()), 219 IsO32(Subtarget->isABI_O32()) { 220 // Mips does not have i1 type, so use i32 for 221 // setcc operations results (slt, sgt, ...). 222 setBooleanContents(ZeroOrOneBooleanContent); 223 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 224 225 // Load extented operations for i1 types must be promoted 226 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 227 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 228 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 229 230 // MIPS doesn't have extending float->double load/store 231 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 232 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 233 234 // Used by legalize types to correctly generate the setcc result. 235 // Without this, every float setcc comes with a AND/OR with the result, 236 // we don't want this, since the fpcmp result goes to a flag register, 237 // which is used implicitly by brcond and select operations. 238 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 239 240 // Mips Custom Operations 241 setOperationAction(ISD::BR_JT, MVT::Other, Custom); 242 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 243 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 244 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 245 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 246 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 247 setOperationAction(ISD::SELECT, MVT::f32, Custom); 248 setOperationAction(ISD::SELECT, MVT::f64, Custom); 249 setOperationAction(ISD::SELECT, MVT::i32, Custom); 250 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 251 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 252 setOperationAction(ISD::SETCC, MVT::f32, Custom); 253 setOperationAction(ISD::SETCC, MVT::f64, Custom); 254 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 255 setOperationAction(ISD::VASTART, MVT::Other, Custom); 256 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 257 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 258 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 259 260 if (!TM.Options.NoNaNsFPMath) { 261 setOperationAction(ISD::FABS, MVT::f32, Custom); 262 setOperationAction(ISD::FABS, MVT::f64, Custom); 263 } 264 265 if (HasMips64) { 266 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 267 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); 268 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 269 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 270 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 271 setOperationAction(ISD::SELECT, MVT::i64, Custom); 272 setOperationAction(ISD::LOAD, MVT::i64, Custom); 273 setOperationAction(ISD::STORE, MVT::i64, Custom); 274 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 275 } 276 277 if (!HasMips64) { 278 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 279 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 280 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 281 } 282 283 setOperationAction(ISD::ADD, MVT::i32, Custom); 284 if (HasMips64) 285 setOperationAction(ISD::ADD, MVT::i64, Custom); 286 287 setOperationAction(ISD::SDIV, MVT::i32, Expand); 288 setOperationAction(ISD::SREM, MVT::i32, Expand); 289 setOperationAction(ISD::UDIV, MVT::i32, Expand); 290 setOperationAction(ISD::UREM, MVT::i32, Expand); 291 setOperationAction(ISD::SDIV, MVT::i64, Expand); 292 setOperationAction(ISD::SREM, MVT::i64, Expand); 293 setOperationAction(ISD::UDIV, MVT::i64, Expand); 294 setOperationAction(ISD::UREM, MVT::i64, Expand); 295 296 // Operations not directly supported by Mips. 297 setOperationAction(ISD::BR_CC, MVT::f32, Expand); 298 setOperationAction(ISD::BR_CC, MVT::f64, Expand); 299 setOperationAction(ISD::BR_CC, MVT::i32, Expand); 300 setOperationAction(ISD::BR_CC, MVT::i64, Expand); 301 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); 302 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 303 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 304 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 305 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 306 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 307 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 308 setOperationAction(ISD::CTPOP, MVT::i64, Expand); 309 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 310 setOperationAction(ISD::CTTZ, MVT::i64, Expand); 311 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); 312 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 313 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); 314 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 315 setOperationAction(ISD::ROTL, MVT::i32, Expand); 316 setOperationAction(ISD::ROTL, MVT::i64, Expand); 317 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 318 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 319 320 if (!Subtarget->hasMips32r2()) 321 setOperationAction(ISD::ROTR, MVT::i32, Expand); 322 323 if (!Subtarget->hasMips64r2()) 324 setOperationAction(ISD::ROTR, MVT::i64, Expand); 325 326 setOperationAction(ISD::FSIN, MVT::f32, Expand); 327 setOperationAction(ISD::FSIN, MVT::f64, Expand); 328 setOperationAction(ISD::FCOS, MVT::f32, Expand); 329 setOperationAction(ISD::FCOS, MVT::f64, Expand); 330 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); 331 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); 332 setOperationAction(ISD::FPOWI, MVT::f32, Expand); 333 setOperationAction(ISD::FPOW, MVT::f32, Expand); 334 setOperationAction(ISD::FPOW, MVT::f64, Expand); 335 setOperationAction(ISD::FLOG, MVT::f32, Expand); 336 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 337 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 338 setOperationAction(ISD::FEXP, MVT::f32, Expand); 339 setOperationAction(ISD::FMA, MVT::f32, Expand); 340 setOperationAction(ISD::FMA, MVT::f64, Expand); 341 setOperationAction(ISD::FREM, MVT::f32, Expand); 342 setOperationAction(ISD::FREM, MVT::f64, Expand); 343 344 if (!TM.Options.NoNaNsFPMath) { 345 setOperationAction(ISD::FNEG, MVT::f32, Expand); 346 setOperationAction(ISD::FNEG, MVT::f64, Expand); 347 } 348 349 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom); 350 351 setOperationAction(ISD::VAARG, MVT::Other, Expand); 352 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 353 setOperationAction(ISD::VAEND, MVT::Other, Expand); 354 355 // Use the default for now 356 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 357 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 358 359 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand); 360 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); 361 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand); 362 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); 363 364 setInsertFencesForAtomic(true); 365 366 if (!Subtarget->hasSEInReg()) { 367 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 368 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 369 } 370 371 if (!Subtarget->hasBitCount()) { 372 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 373 setOperationAction(ISD::CTLZ, MVT::i64, Expand); 374 } 375 376 if (!Subtarget->hasSwap()) { 377 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 378 setOperationAction(ISD::BSWAP, MVT::i64, Expand); 379 } 380 381 if (HasMips64) { 382 setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom); 383 setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Custom); 384 setLoadExtAction(ISD::EXTLOAD, MVT::i32, Custom); 385 setTruncStoreAction(MVT::i64, MVT::i32, Custom); 386 } 387 388 setOperationAction(ISD::TRAP, MVT::Other, Legal); 389 390 setTargetDAGCombine(ISD::SDIVREM); 391 setTargetDAGCombine(ISD::UDIVREM); 392 setTargetDAGCombine(ISD::SELECT); 393 setTargetDAGCombine(ISD::AND); 394 setTargetDAGCombine(ISD::OR); 395 setTargetDAGCombine(ISD::ADD); 396 397 setMinFunctionAlignment(HasMips64 ? 3 : 2); 398 399 setStackPointerRegisterToSaveRestore(IsN64 ? Mips::SP_64 : Mips::SP); 400 401 setExceptionPointerRegister(IsN64 ? Mips::A0_64 : Mips::A0); 402 setExceptionSelectorRegister(IsN64 ? Mips::A1_64 : Mips::A1); 403 404 MaxStoresPerMemcpy = 16; 405 } 406 407 const MipsTargetLowering *MipsTargetLowering::create(MipsTargetMachine &TM) { 408 if (TM.getSubtargetImpl()->inMips16Mode()) 409 return llvm::createMips16TargetLowering(TM); 410 411 return llvm::createMipsSETargetLowering(TM); 412 } 413 414 EVT MipsTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const { 415 if (!VT.isVector()) 416 return MVT::i32; 417 return VT.changeVectorElementTypeToInteger(); 418 } 419 420 static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG, 421 TargetLowering::DAGCombinerInfo &DCI, 422 const MipsSubtarget *Subtarget) { 423 if (DCI.isBeforeLegalizeOps()) 424 return SDValue(); 425 426 EVT Ty = N->getValueType(0); 427 unsigned LO = (Ty == MVT::i32) ? Mips::LO : Mips::LO64; 428 unsigned HI = (Ty == MVT::i32) ? Mips::HI : Mips::HI64; 429 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 : 430 MipsISD::DivRemU16; 431 SDLoc DL(N); 432 433 SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue, 434 N->getOperand(0), N->getOperand(1)); 435 SDValue InChain = DAG.getEntryNode(); 436 SDValue InGlue = DivRem; 437 438 // insert MFLO 439 if (N->hasAnyUseOfValue(0)) { 440 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty, 441 InGlue); 442 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo); 443 InChain = CopyFromLo.getValue(1); 444 InGlue = CopyFromLo.getValue(2); 445 } 446 447 // insert MFHI 448 if (N->hasAnyUseOfValue(1)) { 449 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL, 450 HI, Ty, InGlue); 451 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi); 452 } 453 454 return SDValue(); 455 } 456 457 static Mips::CondCode condCodeToFCC(ISD::CondCode CC) { 458 switch (CC) { 459 default: llvm_unreachable("Unknown fp condition code!"); 460 case ISD::SETEQ: 461 case ISD::SETOEQ: return Mips::FCOND_OEQ; 462 case ISD::SETUNE: return Mips::FCOND_UNE; 463 case ISD::SETLT: 464 case ISD::SETOLT: return Mips::FCOND_OLT; 465 case ISD::SETGT: 466 case ISD::SETOGT: return Mips::FCOND_OGT; 467 case ISD::SETLE: 468 case ISD::SETOLE: return Mips::FCOND_OLE; 469 case ISD::SETGE: 470 case ISD::SETOGE: return Mips::FCOND_OGE; 471 case ISD::SETULT: return Mips::FCOND_ULT; 472 case ISD::SETULE: return Mips::FCOND_ULE; 473 case ISD::SETUGT: return Mips::FCOND_UGT; 474 case ISD::SETUGE: return Mips::FCOND_UGE; 475 case ISD::SETUO: return Mips::FCOND_UN; 476 case ISD::SETO: return Mips::FCOND_OR; 477 case ISD::SETNE: 478 case ISD::SETONE: return Mips::FCOND_ONE; 479 case ISD::SETUEQ: return Mips::FCOND_UEQ; 480 } 481 } 482 483 484 /// This function returns true if the floating point conditional branches and 485 /// conditional moves which use condition code CC should be inverted. 486 static bool invertFPCondCodeUser(Mips::CondCode CC) { 487 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 488 return false; 489 490 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && 491 "Illegal Condition Code"); 492 493 return true; 494 } 495 496 // Creates and returns an FPCmp node from a setcc node. 497 // Returns Op if setcc is not a floating point comparison. 498 static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) { 499 // must be a SETCC node 500 if (Op.getOpcode() != ISD::SETCC) 501 return Op; 502 503 SDValue LHS = Op.getOperand(0); 504 505 if (!LHS.getValueType().isFloatingPoint()) 506 return Op; 507 508 SDValue RHS = Op.getOperand(1); 509 SDLoc DL(Op); 510 511 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of 512 // node if necessary. 513 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 514 515 return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS, 516 DAG.getConstant(condCodeToFCC(CC), MVT::i32)); 517 } 518 519 // Creates and returns a CMovFPT/F node. 520 static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, 521 SDValue False, SDLoc DL) { 522 ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2)); 523 bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue()); 524 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 525 526 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, 527 True.getValueType(), True, FCC0, False, Cond); 528 } 529 530 static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, 531 TargetLowering::DAGCombinerInfo &DCI, 532 const MipsSubtarget *Subtarget) { 533 if (DCI.isBeforeLegalizeOps()) 534 return SDValue(); 535 536 SDValue SetCC = N->getOperand(0); 537 538 if ((SetCC.getOpcode() != ISD::SETCC) || 539 !SetCC.getOperand(0).getValueType().isInteger()) 540 return SDValue(); 541 542 SDValue False = N->getOperand(2); 543 EVT FalseTy = False.getValueType(); 544 545 if (!FalseTy.isInteger()) 546 return SDValue(); 547 548 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(False); 549 550 if (!CN || CN->getZExtValue()) 551 return SDValue(); 552 553 const SDLoc DL(N); 554 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); 555 SDValue True = N->getOperand(1); 556 557 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), 558 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); 559 560 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); 561 } 562 563 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, 564 TargetLowering::DAGCombinerInfo &DCI, 565 const MipsSubtarget *Subtarget) { 566 // Pattern match EXT. 567 // $dst = and ((sra or srl) $src , pos), (2**size - 1) 568 // => ext $dst, $src, size, pos 569 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2()) 570 return SDValue(); 571 572 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1); 573 unsigned ShiftRightOpc = ShiftRight.getOpcode(); 574 575 // Op's first operand must be a shift right. 576 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL) 577 return SDValue(); 578 579 // The second operand of the shift must be an immediate. 580 ConstantSDNode *CN; 581 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1)))) 582 return SDValue(); 583 584 uint64_t Pos = CN->getZExtValue(); 585 uint64_t SMPos, SMSize; 586 587 // Op's second operand must be a shifted mask. 588 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) || 589 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize)) 590 return SDValue(); 591 592 // Return if the shifted mask does not start at bit 0 or the sum of its size 593 // and Pos exceeds the word's size. 594 EVT ValTy = N->getValueType(0); 595 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits()) 596 return SDValue(); 597 598 return DAG.getNode(MipsISD::Ext, SDLoc(N), ValTy, 599 ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32), 600 DAG.getConstant(SMSize, MVT::i32)); 601 } 602 603 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, 604 TargetLowering::DAGCombinerInfo &DCI, 605 const MipsSubtarget *Subtarget) { 606 // Pattern match INS. 607 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1), 608 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1 609 // => ins $dst, $src, size, pos, $src1 610 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2()) 611 return SDValue(); 612 613 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); 614 uint64_t SMPos0, SMSize0, SMPos1, SMSize1; 615 ConstantSDNode *CN; 616 617 // See if Op's first operand matches (and $src1 , mask0). 618 if (And0.getOpcode() != ISD::AND) 619 return SDValue(); 620 621 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) || 622 !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0)) 623 return SDValue(); 624 625 // See if Op's second operand matches (and (shl $src, pos), mask1). 626 if (And1.getOpcode() != ISD::AND) 627 return SDValue(); 628 629 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) || 630 !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1)) 631 return SDValue(); 632 633 // The shift masks must have the same position and size. 634 if (SMPos0 != SMPos1 || SMSize0 != SMSize1) 635 return SDValue(); 636 637 SDValue Shl = And1.getOperand(0); 638 if (Shl.getOpcode() != ISD::SHL) 639 return SDValue(); 640 641 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1)))) 642 return SDValue(); 643 644 unsigned Shamt = CN->getZExtValue(); 645 646 // Return if the shift amount and the first bit position of mask are not the 647 // same. 648 EVT ValTy = N->getValueType(0); 649 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits())) 650 return SDValue(); 651 652 return DAG.getNode(MipsISD::Ins, SDLoc(N), ValTy, Shl.getOperand(0), 653 DAG.getConstant(SMPos0, MVT::i32), 654 DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0)); 655 } 656 657 static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG, 658 TargetLowering::DAGCombinerInfo &DCI, 659 const MipsSubtarget *Subtarget) { 660 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt)) 661 662 if (DCI.isBeforeLegalizeOps()) 663 return SDValue(); 664 665 SDValue Add = N->getOperand(1); 666 667 if (Add.getOpcode() != ISD::ADD) 668 return SDValue(); 669 670 SDValue Lo = Add.getOperand(1); 671 672 if ((Lo.getOpcode() != MipsISD::Lo) || 673 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable)) 674 return SDValue(); 675 676 EVT ValTy = N->getValueType(0); 677 SDLoc DL(N); 678 679 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0), 680 Add.getOperand(0)); 681 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo); 682 } 683 684 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) 685 const { 686 SelectionDAG &DAG = DCI.DAG; 687 unsigned Opc = N->getOpcode(); 688 689 switch (Opc) { 690 default: break; 691 case ISD::SDIVREM: 692 case ISD::UDIVREM: 693 return performDivRemCombine(N, DAG, DCI, Subtarget); 694 case ISD::SELECT: 695 return performSELECTCombine(N, DAG, DCI, Subtarget); 696 case ISD::AND: 697 return performANDCombine(N, DAG, DCI, Subtarget); 698 case ISD::OR: 699 return performORCombine(N, DAG, DCI, Subtarget); 700 case ISD::ADD: 701 return performADDCombine(N, DAG, DCI, Subtarget); 702 } 703 704 return SDValue(); 705 } 706 707 void 708 MipsTargetLowering::LowerOperationWrapper(SDNode *N, 709 SmallVectorImpl<SDValue> &Results, 710 SelectionDAG &DAG) const { 711 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 712 713 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I) 714 Results.push_back(Res.getValue(I)); 715 } 716 717 void 718 MipsTargetLowering::ReplaceNodeResults(SDNode *N, 719 SmallVectorImpl<SDValue> &Results, 720 SelectionDAG &DAG) const { 721 return LowerOperationWrapper(N, Results, DAG); 722 } 723 724 SDValue MipsTargetLowering:: 725 LowerOperation(SDValue Op, SelectionDAG &DAG) const 726 { 727 switch (Op.getOpcode()) 728 { 729 case ISD::BR_JT: return lowerBR_JT(Op, DAG); 730 case ISD::BRCOND: return lowerBRCOND(Op, DAG); 731 case ISD::ConstantPool: return lowerConstantPool(Op, DAG); 732 case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG); 733 case ISD::BlockAddress: return lowerBlockAddress(Op, DAG); 734 case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG); 735 case ISD::JumpTable: return lowerJumpTable(Op, DAG); 736 case ISD::SELECT: return lowerSELECT(Op, DAG); 737 case ISD::SELECT_CC: return lowerSELECT_CC(Op, DAG); 738 case ISD::SETCC: return lowerSETCC(Op, DAG); 739 case ISD::VASTART: return lowerVASTART(Op, DAG); 740 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG); 741 case ISD::FABS: return lowerFABS(Op, DAG); 742 case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG); 743 case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG); 744 case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG); 745 case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG); 746 case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG); 747 case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true); 748 case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false); 749 case ISD::LOAD: return lowerLOAD(Op, DAG); 750 case ISD::STORE: return lowerSTORE(Op, DAG); 751 case ISD::ADD: return lowerADD(Op, DAG); 752 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG); 753 } 754 return SDValue(); 755 } 756 757 //===----------------------------------------------------------------------===// 758 // Lower helper functions 759 //===----------------------------------------------------------------------===// 760 761 // addLiveIn - This helper function adds the specified physical register to the 762 // MachineFunction as a live in value. It also creates a corresponding 763 // virtual register for it. 764 static unsigned 765 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC) 766 { 767 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); 768 MF.getRegInfo().addLiveIn(PReg, VReg); 769 return VReg; 770 } 771 772 static MachineBasicBlock *expandPseudoDIV(MachineInstr *MI, 773 MachineBasicBlock &MBB, 774 const TargetInstrInfo &TII, 775 bool Is64Bit) { 776 if (NoZeroDivCheck) 777 return &MBB; 778 779 // Insert instruction "teq $divisor_reg, $zero, 7". 780 MachineBasicBlock::iterator I(MI); 781 MachineInstrBuilder MIB; 782 MIB = BuildMI(MBB, llvm::next(I), MI->getDebugLoc(), TII.get(Mips::TEQ)) 783 .addOperand(MI->getOperand(2)).addReg(Mips::ZERO).addImm(7); 784 785 // Use the 32-bit sub-register if this is a 64-bit division. 786 if (Is64Bit) 787 MIB->getOperand(0).setSubReg(Mips::sub_32); 788 789 return &MBB; 790 } 791 792 MachineBasicBlock * 793 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 794 MachineBasicBlock *BB) const { 795 switch (MI->getOpcode()) { 796 default: 797 llvm_unreachable("Unexpected instr type to insert"); 798 case Mips::ATOMIC_LOAD_ADD_I8: 799 case Mips::ATOMIC_LOAD_ADD_I8_P8: 800 return emitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu); 801 case Mips::ATOMIC_LOAD_ADD_I16: 802 case Mips::ATOMIC_LOAD_ADD_I16_P8: 803 return emitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu); 804 case Mips::ATOMIC_LOAD_ADD_I32: 805 case Mips::ATOMIC_LOAD_ADD_I32_P8: 806 return emitAtomicBinary(MI, BB, 4, Mips::ADDu); 807 case Mips::ATOMIC_LOAD_ADD_I64: 808 case Mips::ATOMIC_LOAD_ADD_I64_P8: 809 return emitAtomicBinary(MI, BB, 8, Mips::DADDu); 810 811 case Mips::ATOMIC_LOAD_AND_I8: 812 case Mips::ATOMIC_LOAD_AND_I8_P8: 813 return emitAtomicBinaryPartword(MI, BB, 1, Mips::AND); 814 case Mips::ATOMIC_LOAD_AND_I16: 815 case Mips::ATOMIC_LOAD_AND_I16_P8: 816 return emitAtomicBinaryPartword(MI, BB, 2, Mips::AND); 817 case Mips::ATOMIC_LOAD_AND_I32: 818 case Mips::ATOMIC_LOAD_AND_I32_P8: 819 return emitAtomicBinary(MI, BB, 4, Mips::AND); 820 case Mips::ATOMIC_LOAD_AND_I64: 821 case Mips::ATOMIC_LOAD_AND_I64_P8: 822 return emitAtomicBinary(MI, BB, 8, Mips::AND64); 823 824 case Mips::ATOMIC_LOAD_OR_I8: 825 case Mips::ATOMIC_LOAD_OR_I8_P8: 826 return emitAtomicBinaryPartword(MI, BB, 1, Mips::OR); 827 case Mips::ATOMIC_LOAD_OR_I16: 828 case Mips::ATOMIC_LOAD_OR_I16_P8: 829 return emitAtomicBinaryPartword(MI, BB, 2, Mips::OR); 830 case Mips::ATOMIC_LOAD_OR_I32: 831 case Mips::ATOMIC_LOAD_OR_I32_P8: 832 return emitAtomicBinary(MI, BB, 4, Mips::OR); 833 case Mips::ATOMIC_LOAD_OR_I64: 834 case Mips::ATOMIC_LOAD_OR_I64_P8: 835 return emitAtomicBinary(MI, BB, 8, Mips::OR64); 836 837 case Mips::ATOMIC_LOAD_XOR_I8: 838 case Mips::ATOMIC_LOAD_XOR_I8_P8: 839 return emitAtomicBinaryPartword(MI, BB, 1, Mips::XOR); 840 case Mips::ATOMIC_LOAD_XOR_I16: 841 case Mips::ATOMIC_LOAD_XOR_I16_P8: 842 return emitAtomicBinaryPartword(MI, BB, 2, Mips::XOR); 843 case Mips::ATOMIC_LOAD_XOR_I32: 844 case Mips::ATOMIC_LOAD_XOR_I32_P8: 845 return emitAtomicBinary(MI, BB, 4, Mips::XOR); 846 case Mips::ATOMIC_LOAD_XOR_I64: 847 case Mips::ATOMIC_LOAD_XOR_I64_P8: 848 return emitAtomicBinary(MI, BB, 8, Mips::XOR64); 849 850 case Mips::ATOMIC_LOAD_NAND_I8: 851 case Mips::ATOMIC_LOAD_NAND_I8_P8: 852 return emitAtomicBinaryPartword(MI, BB, 1, 0, true); 853 case Mips::ATOMIC_LOAD_NAND_I16: 854 case Mips::ATOMIC_LOAD_NAND_I16_P8: 855 return emitAtomicBinaryPartword(MI, BB, 2, 0, true); 856 case Mips::ATOMIC_LOAD_NAND_I32: 857 case Mips::ATOMIC_LOAD_NAND_I32_P8: 858 return emitAtomicBinary(MI, BB, 4, 0, true); 859 case Mips::ATOMIC_LOAD_NAND_I64: 860 case Mips::ATOMIC_LOAD_NAND_I64_P8: 861 return emitAtomicBinary(MI, BB, 8, 0, true); 862 863 case Mips::ATOMIC_LOAD_SUB_I8: 864 case Mips::ATOMIC_LOAD_SUB_I8_P8: 865 return emitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu); 866 case Mips::ATOMIC_LOAD_SUB_I16: 867 case Mips::ATOMIC_LOAD_SUB_I16_P8: 868 return emitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu); 869 case Mips::ATOMIC_LOAD_SUB_I32: 870 case Mips::ATOMIC_LOAD_SUB_I32_P8: 871 return emitAtomicBinary(MI, BB, 4, Mips::SUBu); 872 case Mips::ATOMIC_LOAD_SUB_I64: 873 case Mips::ATOMIC_LOAD_SUB_I64_P8: 874 return emitAtomicBinary(MI, BB, 8, Mips::DSUBu); 875 876 case Mips::ATOMIC_SWAP_I8: 877 case Mips::ATOMIC_SWAP_I8_P8: 878 return emitAtomicBinaryPartword(MI, BB, 1, 0); 879 case Mips::ATOMIC_SWAP_I16: 880 case Mips::ATOMIC_SWAP_I16_P8: 881 return emitAtomicBinaryPartword(MI, BB, 2, 0); 882 case Mips::ATOMIC_SWAP_I32: 883 case Mips::ATOMIC_SWAP_I32_P8: 884 return emitAtomicBinary(MI, BB, 4, 0); 885 case Mips::ATOMIC_SWAP_I64: 886 case Mips::ATOMIC_SWAP_I64_P8: 887 return emitAtomicBinary(MI, BB, 8, 0); 888 889 case Mips::ATOMIC_CMP_SWAP_I8: 890 case Mips::ATOMIC_CMP_SWAP_I8_P8: 891 return emitAtomicCmpSwapPartword(MI, BB, 1); 892 case Mips::ATOMIC_CMP_SWAP_I16: 893 case Mips::ATOMIC_CMP_SWAP_I16_P8: 894 return emitAtomicCmpSwapPartword(MI, BB, 2); 895 case Mips::ATOMIC_CMP_SWAP_I32: 896 case Mips::ATOMIC_CMP_SWAP_I32_P8: 897 return emitAtomicCmpSwap(MI, BB, 4); 898 case Mips::ATOMIC_CMP_SWAP_I64: 899 case Mips::ATOMIC_CMP_SWAP_I64_P8: 900 return emitAtomicCmpSwap(MI, BB, 8); 901 case Mips::PseudoSDIV: 902 case Mips::PseudoUDIV: 903 return expandPseudoDIV(MI, *BB, *getTargetMachine().getInstrInfo(), false); 904 case Mips::PseudoDSDIV: 905 case Mips::PseudoDUDIV: 906 return expandPseudoDIV(MI, *BB, *getTargetMachine().getInstrInfo(), true); 907 } 908 } 909 910 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and 911 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) 912 MachineBasicBlock * 913 MipsTargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 914 unsigned Size, unsigned BinOpcode, 915 bool Nand) const { 916 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary."); 917 918 MachineFunction *MF = BB->getParent(); 919 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 920 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 921 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 922 DebugLoc DL = MI->getDebugLoc(); 923 unsigned LL, SC, AND, NOR, ZERO, BEQ; 924 925 if (Size == 4) { 926 LL = IsN64 ? Mips::LL_P8 : Mips::LL; 927 SC = IsN64 ? Mips::SC_P8 : Mips::SC; 928 AND = Mips::AND; 929 NOR = Mips::NOR; 930 ZERO = Mips::ZERO; 931 BEQ = Mips::BEQ; 932 } 933 else { 934 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD; 935 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD; 936 AND = Mips::AND64; 937 NOR = Mips::NOR64; 938 ZERO = Mips::ZERO_64; 939 BEQ = Mips::BEQ64; 940 } 941 942 unsigned OldVal = MI->getOperand(0).getReg(); 943 unsigned Ptr = MI->getOperand(1).getReg(); 944 unsigned Incr = MI->getOperand(2).getReg(); 945 946 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 947 unsigned AndRes = RegInfo.createVirtualRegister(RC); 948 unsigned Success = RegInfo.createVirtualRegister(RC); 949 950 // insert new blocks after the current block 951 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 952 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 953 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 954 MachineFunction::iterator It = BB; 955 ++It; 956 MF->insert(It, loopMBB); 957 MF->insert(It, exitMBB); 958 959 // Transfer the remainder of BB and its successor edges to exitMBB. 960 exitMBB->splice(exitMBB->begin(), BB, 961 llvm::next(MachineBasicBlock::iterator(MI)), 962 BB->end()); 963 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 964 965 // thisMBB: 966 // ... 967 // fallthrough --> loopMBB 968 BB->addSuccessor(loopMBB); 969 loopMBB->addSuccessor(loopMBB); 970 loopMBB->addSuccessor(exitMBB); 971 972 // loopMBB: 973 // ll oldval, 0(ptr) 974 // <binop> storeval, oldval, incr 975 // sc success, storeval, 0(ptr) 976 // beq success, $0, loopMBB 977 BB = loopMBB; 978 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0); 979 if (Nand) { 980 // and andres, oldval, incr 981 // nor storeval, $0, andres 982 BuildMI(BB, DL, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr); 983 BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes); 984 } else if (BinOpcode) { 985 // <binop> storeval, oldval, incr 986 BuildMI(BB, DL, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr); 987 } else { 988 StoreVal = Incr; 989 } 990 BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0); 991 BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB); 992 993 MI->eraseFromParent(); // The instruction is gone now. 994 995 return exitMBB; 996 } 997 998 MachineBasicBlock * 999 MipsTargetLowering::emitAtomicBinaryPartword(MachineInstr *MI, 1000 MachineBasicBlock *BB, 1001 unsigned Size, unsigned BinOpcode, 1002 bool Nand) const { 1003 assert((Size == 1 || Size == 2) && 1004 "Unsupported size for EmitAtomicBinaryPartial."); 1005 1006 MachineFunction *MF = BB->getParent(); 1007 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1008 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1009 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1010 DebugLoc DL = MI->getDebugLoc(); 1011 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL; 1012 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC; 1013 1014 unsigned Dest = MI->getOperand(0).getReg(); 1015 unsigned Ptr = MI->getOperand(1).getReg(); 1016 unsigned Incr = MI->getOperand(2).getReg(); 1017 1018 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 1019 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1020 unsigned Mask = RegInfo.createVirtualRegister(RC); 1021 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1022 unsigned NewVal = RegInfo.createVirtualRegister(RC); 1023 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1024 unsigned Incr2 = RegInfo.createVirtualRegister(RC); 1025 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 1026 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1027 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1028 unsigned AndRes = RegInfo.createVirtualRegister(RC); 1029 unsigned BinOpRes = RegInfo.createVirtualRegister(RC); 1030 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1031 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1032 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1033 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1034 unsigned SllRes = RegInfo.createVirtualRegister(RC); 1035 unsigned Success = RegInfo.createVirtualRegister(RC); 1036 1037 // insert new blocks after the current block 1038 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1039 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1040 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1041 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1042 MachineFunction::iterator It = BB; 1043 ++It; 1044 MF->insert(It, loopMBB); 1045 MF->insert(It, sinkMBB); 1046 MF->insert(It, exitMBB); 1047 1048 // Transfer the remainder of BB and its successor edges to exitMBB. 1049 exitMBB->splice(exitMBB->begin(), BB, 1050 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1051 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1052 1053 BB->addSuccessor(loopMBB); 1054 loopMBB->addSuccessor(loopMBB); 1055 loopMBB->addSuccessor(sinkMBB); 1056 sinkMBB->addSuccessor(exitMBB); 1057 1058 // thisMBB: 1059 // addiu masklsb2,$0,-4 # 0xfffffffc 1060 // and alignedaddr,ptr,masklsb2 1061 // andi ptrlsb2,ptr,3 1062 // sll shiftamt,ptrlsb2,3 1063 // ori maskupper,$0,255 # 0xff 1064 // sll mask,maskupper,shiftamt 1065 // nor mask2,$0,mask 1066 // sll incr2,incr,shiftamt 1067 1068 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1069 BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2) 1070 .addReg(Mips::ZERO).addImm(-4); 1071 BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr) 1072 .addReg(Ptr).addReg(MaskLSB2); 1073 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 1074 if (Subtarget->isLittle()) { 1075 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1076 } else { 1077 unsigned Off = RegInfo.createVirtualRegister(RC); 1078 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1079 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1080 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1081 } 1082 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1083 .addReg(Mips::ZERO).addImm(MaskImm); 1084 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1085 .addReg(MaskUpper).addReg(ShiftAmt); 1086 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1087 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt); 1088 1089 // atomic.load.binop 1090 // loopMBB: 1091 // ll oldval,0(alignedaddr) 1092 // binop binopres,oldval,incr2 1093 // and newval,binopres,mask 1094 // and maskedoldval0,oldval,mask2 1095 // or storeval,maskedoldval0,newval 1096 // sc success,storeval,0(alignedaddr) 1097 // beq success,$0,loopMBB 1098 1099 // atomic.swap 1100 // loopMBB: 1101 // ll oldval,0(alignedaddr) 1102 // and newval,incr2,mask 1103 // and maskedoldval0,oldval,mask2 1104 // or storeval,maskedoldval0,newval 1105 // sc success,storeval,0(alignedaddr) 1106 // beq success,$0,loopMBB 1107 1108 BB = loopMBB; 1109 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); 1110 if (Nand) { 1111 // and andres, oldval, incr2 1112 // nor binopres, $0, andres 1113 // and newval, binopres, mask 1114 BuildMI(BB, DL, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2); 1115 BuildMI(BB, DL, TII->get(Mips::NOR), BinOpRes) 1116 .addReg(Mips::ZERO).addReg(AndRes); 1117 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1118 } else if (BinOpcode) { 1119 // <binop> binopres, oldval, incr2 1120 // and newval, binopres, mask 1121 BuildMI(BB, DL, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2); 1122 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1123 } else {// atomic.swap 1124 // and newval, incr2, mask 1125 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask); 1126 } 1127 1128 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0) 1129 .addReg(OldVal).addReg(Mask2); 1130 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal) 1131 .addReg(MaskedOldVal0).addReg(NewVal); 1132 BuildMI(BB, DL, TII->get(SC), Success) 1133 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1134 BuildMI(BB, DL, TII->get(Mips::BEQ)) 1135 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB); 1136 1137 // sinkMBB: 1138 // and maskedoldval1,oldval,mask 1139 // srl srlres,maskedoldval1,shiftamt 1140 // sll sllres,srlres,24 1141 // sra dest,sllres,24 1142 BB = sinkMBB; 1143 int64_t ShiftImm = (Size == 1) ? 24 : 16; 1144 1145 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1) 1146 .addReg(OldVal).addReg(Mask); 1147 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes) 1148 .addReg(MaskedOldVal1).addReg(ShiftAmt); 1149 BuildMI(BB, DL, TII->get(Mips::SLL), SllRes) 1150 .addReg(SrlRes).addImm(ShiftImm); 1151 BuildMI(BB, DL, TII->get(Mips::SRA), Dest) 1152 .addReg(SllRes).addImm(ShiftImm); 1153 1154 MI->eraseFromParent(); // The instruction is gone now. 1155 1156 return exitMBB; 1157 } 1158 1159 MachineBasicBlock * 1160 MipsTargetLowering::emitAtomicCmpSwap(MachineInstr *MI, 1161 MachineBasicBlock *BB, 1162 unsigned Size) const { 1163 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap."); 1164 1165 MachineFunction *MF = BB->getParent(); 1166 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1167 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); 1168 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1169 DebugLoc DL = MI->getDebugLoc(); 1170 unsigned LL, SC, ZERO, BNE, BEQ; 1171 1172 if (Size == 4) { 1173 LL = IsN64 ? Mips::LL_P8 : Mips::LL; 1174 SC = IsN64 ? Mips::SC_P8 : Mips::SC; 1175 ZERO = Mips::ZERO; 1176 BNE = Mips::BNE; 1177 BEQ = Mips::BEQ; 1178 } 1179 else { 1180 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD; 1181 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD; 1182 ZERO = Mips::ZERO_64; 1183 BNE = Mips::BNE64; 1184 BEQ = Mips::BEQ64; 1185 } 1186 1187 unsigned Dest = MI->getOperand(0).getReg(); 1188 unsigned Ptr = MI->getOperand(1).getReg(); 1189 unsigned OldVal = MI->getOperand(2).getReg(); 1190 unsigned NewVal = MI->getOperand(3).getReg(); 1191 1192 unsigned Success = RegInfo.createVirtualRegister(RC); 1193 1194 // insert new blocks after the current block 1195 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1196 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1197 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1198 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1199 MachineFunction::iterator It = BB; 1200 ++It; 1201 MF->insert(It, loop1MBB); 1202 MF->insert(It, loop2MBB); 1203 MF->insert(It, exitMBB); 1204 1205 // Transfer the remainder of BB and its successor edges to exitMBB. 1206 exitMBB->splice(exitMBB->begin(), BB, 1207 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1208 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1209 1210 // thisMBB: 1211 // ... 1212 // fallthrough --> loop1MBB 1213 BB->addSuccessor(loop1MBB); 1214 loop1MBB->addSuccessor(exitMBB); 1215 loop1MBB->addSuccessor(loop2MBB); 1216 loop2MBB->addSuccessor(loop1MBB); 1217 loop2MBB->addSuccessor(exitMBB); 1218 1219 // loop1MBB: 1220 // ll dest, 0(ptr) 1221 // bne dest, oldval, exitMBB 1222 BB = loop1MBB; 1223 BuildMI(BB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0); 1224 BuildMI(BB, DL, TII->get(BNE)) 1225 .addReg(Dest).addReg(OldVal).addMBB(exitMBB); 1226 1227 // loop2MBB: 1228 // sc success, newval, 0(ptr) 1229 // beq success, $0, loop1MBB 1230 BB = loop2MBB; 1231 BuildMI(BB, DL, TII->get(SC), Success) 1232 .addReg(NewVal).addReg(Ptr).addImm(0); 1233 BuildMI(BB, DL, TII->get(BEQ)) 1234 .addReg(Success).addReg(ZERO).addMBB(loop1MBB); 1235 1236 MI->eraseFromParent(); // The instruction is gone now. 1237 1238 return exitMBB; 1239 } 1240 1241 MachineBasicBlock * 1242 MipsTargetLowering::emitAtomicCmpSwapPartword(MachineInstr *MI, 1243 MachineBasicBlock *BB, 1244 unsigned Size) const { 1245 assert((Size == 1 || Size == 2) && 1246 "Unsupported size for EmitAtomicCmpSwapPartial."); 1247 1248 MachineFunction *MF = BB->getParent(); 1249 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1250 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1251 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1252 DebugLoc DL = MI->getDebugLoc(); 1253 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL; 1254 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC; 1255 1256 unsigned Dest = MI->getOperand(0).getReg(); 1257 unsigned Ptr = MI->getOperand(1).getReg(); 1258 unsigned CmpVal = MI->getOperand(2).getReg(); 1259 unsigned NewVal = MI->getOperand(3).getReg(); 1260 1261 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 1262 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1263 unsigned Mask = RegInfo.createVirtualRegister(RC); 1264 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1265 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC); 1266 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1267 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1268 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC); 1269 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 1270 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1271 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1272 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC); 1273 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC); 1274 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1275 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1276 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1277 unsigned SllRes = RegInfo.createVirtualRegister(RC); 1278 unsigned Success = RegInfo.createVirtualRegister(RC); 1279 1280 // insert new blocks after the current block 1281 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1282 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1283 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1284 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1285 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1286 MachineFunction::iterator It = BB; 1287 ++It; 1288 MF->insert(It, loop1MBB); 1289 MF->insert(It, loop2MBB); 1290 MF->insert(It, sinkMBB); 1291 MF->insert(It, exitMBB); 1292 1293 // Transfer the remainder of BB and its successor edges to exitMBB. 1294 exitMBB->splice(exitMBB->begin(), BB, 1295 llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 1296 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1297 1298 BB->addSuccessor(loop1MBB); 1299 loop1MBB->addSuccessor(sinkMBB); 1300 loop1MBB->addSuccessor(loop2MBB); 1301 loop2MBB->addSuccessor(loop1MBB); 1302 loop2MBB->addSuccessor(sinkMBB); 1303 sinkMBB->addSuccessor(exitMBB); 1304 1305 // FIXME: computation of newval2 can be moved to loop2MBB. 1306 // thisMBB: 1307 // addiu masklsb2,$0,-4 # 0xfffffffc 1308 // and alignedaddr,ptr,masklsb2 1309 // andi ptrlsb2,ptr,3 1310 // sll shiftamt,ptrlsb2,3 1311 // ori maskupper,$0,255 # 0xff 1312 // sll mask,maskupper,shiftamt 1313 // nor mask2,$0,mask 1314 // andi maskedcmpval,cmpval,255 1315 // sll shiftedcmpval,maskedcmpval,shiftamt 1316 // andi maskednewval,newval,255 1317 // sll shiftednewval,maskednewval,shiftamt 1318 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1319 BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2) 1320 .addReg(Mips::ZERO).addImm(-4); 1321 BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr) 1322 .addReg(Ptr).addReg(MaskLSB2); 1323 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 1324 if (Subtarget->isLittle()) { 1325 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1326 } else { 1327 unsigned Off = RegInfo.createVirtualRegister(RC); 1328 BuildMI(BB, DL, TII->get(Mips::XORi), Off) 1329 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); 1330 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1331 } 1332 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) 1333 .addReg(Mips::ZERO).addImm(MaskImm); 1334 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) 1335 .addReg(MaskUpper).addReg(ShiftAmt); 1336 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1337 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal) 1338 .addReg(CmpVal).addImm(MaskImm); 1339 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal) 1340 .addReg(MaskedCmpVal).addReg(ShiftAmt); 1341 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal) 1342 .addReg(NewVal).addImm(MaskImm); 1343 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal) 1344 .addReg(MaskedNewVal).addReg(ShiftAmt); 1345 1346 // loop1MBB: 1347 // ll oldval,0(alginedaddr) 1348 // and maskedoldval0,oldval,mask 1349 // bne maskedoldval0,shiftedcmpval,sinkMBB 1350 BB = loop1MBB; 1351 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); 1352 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0) 1353 .addReg(OldVal).addReg(Mask); 1354 BuildMI(BB, DL, TII->get(Mips::BNE)) 1355 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB); 1356 1357 // loop2MBB: 1358 // and maskedoldval1,oldval,mask2 1359 // or storeval,maskedoldval1,shiftednewval 1360 // sc success,storeval,0(alignedaddr) 1361 // beq success,$0,loop1MBB 1362 BB = loop2MBB; 1363 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1) 1364 .addReg(OldVal).addReg(Mask2); 1365 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal) 1366 .addReg(MaskedOldVal1).addReg(ShiftedNewVal); 1367 BuildMI(BB, DL, TII->get(SC), Success) 1368 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1369 BuildMI(BB, DL, TII->get(Mips::BEQ)) 1370 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB); 1371 1372 // sinkMBB: 1373 // srl srlres,maskedoldval0,shiftamt 1374 // sll sllres,srlres,24 1375 // sra dest,sllres,24 1376 BB = sinkMBB; 1377 int64_t ShiftImm = (Size == 1) ? 24 : 16; 1378 1379 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes) 1380 .addReg(MaskedOldVal0).addReg(ShiftAmt); 1381 BuildMI(BB, DL, TII->get(Mips::SLL), SllRes) 1382 .addReg(SrlRes).addImm(ShiftImm); 1383 BuildMI(BB, DL, TII->get(Mips::SRA), Dest) 1384 .addReg(SllRes).addImm(ShiftImm); 1385 1386 MI->eraseFromParent(); // The instruction is gone now. 1387 1388 return exitMBB; 1389 } 1390 1391 //===----------------------------------------------------------------------===// 1392 // Misc Lower Operation implementation 1393 //===----------------------------------------------------------------------===// 1394 SDValue MipsTargetLowering::lowerBR_JT(SDValue Op, SelectionDAG &DAG) const { 1395 SDValue Chain = Op.getOperand(0); 1396 SDValue Table = Op.getOperand(1); 1397 SDValue Index = Op.getOperand(2); 1398 SDLoc DL(Op); 1399 EVT PTy = getPointerTy(); 1400 unsigned EntrySize = 1401 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(*getDataLayout()); 1402 1403 Index = DAG.getNode(ISD::MUL, DL, PTy, Index, 1404 DAG.getConstant(EntrySize, PTy)); 1405 SDValue Addr = DAG.getNode(ISD::ADD, DL, PTy, Index, Table); 1406 1407 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8); 1408 Addr = DAG.getExtLoad(ISD::SEXTLOAD, DL, PTy, Chain, Addr, 1409 MachinePointerInfo::getJumpTable(), MemVT, false, false, 1410 0); 1411 Chain = Addr.getValue(1); 1412 1413 if ((getTargetMachine().getRelocationModel() == Reloc::PIC_) || IsN64) { 1414 // For PIC, the sequence is: 1415 // BRIND(load(Jumptable + index) + RelocBase) 1416 // RelocBase can be JumpTable, GOT or some sort of global base. 1417 Addr = DAG.getNode(ISD::ADD, DL, PTy, Addr, 1418 getPICJumpTableRelocBase(Table, DAG)); 1419 } 1420 1421 return DAG.getNode(ISD::BRIND, DL, MVT::Other, Chain, Addr); 1422 } 1423 1424 SDValue MipsTargetLowering:: 1425 lowerBRCOND(SDValue Op, SelectionDAG &DAG) const 1426 { 1427 // The first operand is the chain, the second is the condition, the third is 1428 // the block to branch to if the condition is true. 1429 SDValue Chain = Op.getOperand(0); 1430 SDValue Dest = Op.getOperand(2); 1431 SDLoc DL(Op); 1432 1433 SDValue CondRes = createFPCmp(DAG, Op.getOperand(1)); 1434 1435 // Return if flag is not set by a floating point comparison. 1436 if (CondRes.getOpcode() != MipsISD::FPCmp) 1437 return Op; 1438 1439 SDValue CCNode = CondRes.getOperand(2); 1440 Mips::CondCode CC = 1441 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); 1442 unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T; 1443 SDValue BrCode = DAG.getConstant(Opc, MVT::i32); 1444 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); 1445 return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode, 1446 FCC0, Dest, CondRes); 1447 } 1448 1449 SDValue MipsTargetLowering:: 1450 lowerSELECT(SDValue Op, SelectionDAG &DAG) const 1451 { 1452 SDValue Cond = createFPCmp(DAG, Op.getOperand(0)); 1453 1454 // Return if flag is not set by a floating point comparison. 1455 if (Cond.getOpcode() != MipsISD::FPCmp) 1456 return Op; 1457 1458 return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), 1459 SDLoc(Op)); 1460 } 1461 1462 SDValue MipsTargetLowering:: 1463 lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const 1464 { 1465 SDLoc DL(Op); 1466 EVT Ty = Op.getOperand(0).getValueType(); 1467 SDValue Cond = DAG.getNode(ISD::SETCC, DL, 1468 getSetCCResultType(*DAG.getContext(), Ty), 1469 Op.getOperand(0), Op.getOperand(1), 1470 Op.getOperand(4)); 1471 1472 return DAG.getNode(ISD::SELECT, DL, Op.getValueType(), Cond, Op.getOperand(2), 1473 Op.getOperand(3)); 1474 } 1475 1476 SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const { 1477 SDValue Cond = createFPCmp(DAG, Op); 1478 1479 assert(Cond.getOpcode() == MipsISD::FPCmp && 1480 "Floating point operand expected."); 1481 1482 SDValue True = DAG.getConstant(1, MVT::i32); 1483 SDValue False = DAG.getConstant(0, MVT::i32); 1484 1485 return createCMovFP(DAG, Cond, True, False, SDLoc(Op)); 1486 } 1487 1488 SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op, 1489 SelectionDAG &DAG) const { 1490 // FIXME there isn't actually debug info here 1491 SDLoc DL(Op); 1492 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 1493 1494 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) { 1495 const MipsTargetObjectFile &TLOF = 1496 (const MipsTargetObjectFile&)getObjFileLowering(); 1497 1498 // %gp_rel relocation 1499 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) { 1500 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, 0, 1501 MipsII::MO_GPREL); 1502 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, DL, 1503 DAG.getVTList(MVT::i32), &GA, 1); 1504 SDValue GPReg = DAG.getRegister(Mips::GP, MVT::i32); 1505 return DAG.getNode(ISD::ADD, DL, MVT::i32, GPReg, GPRelNode); 1506 } 1507 1508 // %hi/%lo relocation 1509 return getAddrNonPIC(Op, DAG); 1510 } 1511 1512 if (GV->hasInternalLinkage() || (GV->hasLocalLinkage() && !isa<Function>(GV))) 1513 return getAddrLocal(Op, DAG, HasMips64); 1514 1515 if (LargeGOT) 1516 return getAddrGlobalLargeGOT(Op, DAG, MipsII::MO_GOT_HI16, 1517 MipsII::MO_GOT_LO16); 1518 1519 return getAddrGlobal(Op, DAG, 1520 HasMips64 ? MipsII::MO_GOT_DISP : MipsII::MO_GOT16); 1521 } 1522 1523 SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op, 1524 SelectionDAG &DAG) const { 1525 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) 1526 return getAddrNonPIC(Op, DAG); 1527 1528 return getAddrLocal(Op, DAG, HasMips64); 1529 } 1530 1531 SDValue MipsTargetLowering:: 1532 lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const 1533 { 1534 // If the relocation model is PIC, use the General Dynamic TLS Model or 1535 // Local Dynamic TLS model, otherwise use the Initial Exec or 1536 // Local Exec TLS Model. 1537 1538 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 1539 SDLoc DL(GA); 1540 const GlobalValue *GV = GA->getGlobal(); 1541 EVT PtrVT = getPointerTy(); 1542 1543 TLSModel::Model model = getTargetMachine().getTLSModel(GV); 1544 1545 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) { 1546 // General Dynamic and Local Dynamic TLS Model. 1547 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM 1548 : MipsII::MO_TLSGD; 1549 1550 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag); 1551 SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, 1552 getGlobalReg(DAG, PtrVT), TGA); 1553 unsigned PtrSize = PtrVT.getSizeInBits(); 1554 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize); 1555 1556 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT); 1557 1558 ArgListTy Args; 1559 ArgListEntry Entry; 1560 Entry.Node = Argument; 1561 Entry.Ty = PtrTy; 1562 Args.push_back(Entry); 1563 1564 TargetLowering::CallLoweringInfo CLI(DAG.getEntryNode(), PtrTy, 1565 false, false, false, false, 0, CallingConv::C, 1566 /*IsTailCall=*/false, /*doesNotRet=*/false, 1567 /*isReturnValueUsed=*/true, 1568 TlsGetAddr, Args, DAG, DL); 1569 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 1570 1571 SDValue Ret = CallResult.first; 1572 1573 if (model != TLSModel::LocalDynamic) 1574 return Ret; 1575 1576 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1577 MipsII::MO_DTPREL_HI); 1578 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi); 1579 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1580 MipsII::MO_DTPREL_LO); 1581 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 1582 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret); 1583 return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo); 1584 } 1585 1586 SDValue Offset; 1587 if (model == TLSModel::InitialExec) { 1588 // Initial Exec TLS Model 1589 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1590 MipsII::MO_GOTTPREL); 1591 TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT), 1592 TGA); 1593 Offset = DAG.getLoad(PtrVT, DL, 1594 DAG.getEntryNode(), TGA, MachinePointerInfo(), 1595 false, false, false, 0); 1596 } else { 1597 // Local Exec TLS Model 1598 assert(model == TLSModel::LocalExec); 1599 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1600 MipsII::MO_TPREL_HI); 1601 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 1602 MipsII::MO_TPREL_LO); 1603 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi); 1604 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); 1605 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); 1606 } 1607 1608 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT); 1609 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset); 1610 } 1611 1612 SDValue MipsTargetLowering:: 1613 lowerJumpTable(SDValue Op, SelectionDAG &DAG) const 1614 { 1615 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) 1616 return getAddrNonPIC(Op, DAG); 1617 1618 return getAddrLocal(Op, DAG, HasMips64); 1619 } 1620 1621 SDValue MipsTargetLowering:: 1622 lowerConstantPool(SDValue Op, SelectionDAG &DAG) const 1623 { 1624 // gp_rel relocation 1625 // FIXME: we should reference the constant pool using small data sections, 1626 // but the asm printer currently doesn't support this feature without 1627 // hacking it. This feature should come soon so we can uncomment the 1628 // stuff below. 1629 //if (IsInSmallSection(C->getType())) { 1630 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP); 1631 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32); 1632 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode); 1633 1634 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) 1635 return getAddrNonPIC(Op, DAG); 1636 1637 return getAddrLocal(Op, DAG, HasMips64); 1638 } 1639 1640 SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const { 1641 MachineFunction &MF = DAG.getMachineFunction(); 1642 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 1643 1644 SDLoc DL(Op); 1645 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 1646 getPointerTy()); 1647 1648 // vastart just stores the address of the VarArgsFrameIndex slot into the 1649 // memory location argument. 1650 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1651 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1), 1652 MachinePointerInfo(SV), false, false, 0); 1653 } 1654 1655 static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, bool HasR2) { 1656 EVT TyX = Op.getOperand(0).getValueType(); 1657 EVT TyY = Op.getOperand(1).getValueType(); 1658 SDValue Const1 = DAG.getConstant(1, MVT::i32); 1659 SDValue Const31 = DAG.getConstant(31, MVT::i32); 1660 SDLoc DL(Op); 1661 SDValue Res; 1662 1663 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 1664 // to i32. 1665 SDValue X = (TyX == MVT::f32) ? 1666 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : 1667 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 1668 Const1); 1669 SDValue Y = (TyY == MVT::f32) ? 1670 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) : 1671 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1), 1672 Const1); 1673 1674 if (HasR2) { 1675 // ext E, Y, 31, 1 ; extract bit31 of Y 1676 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X 1677 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1); 1678 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X); 1679 } else { 1680 // sll SllX, X, 1 1681 // srl SrlX, SllX, 1 1682 // srl SrlY, Y, 31 1683 // sll SllY, SrlX, 31 1684 // or Or, SrlX, SllY 1685 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 1686 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 1687 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31); 1688 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31); 1689 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY); 1690 } 1691 1692 if (TyX == MVT::f32) 1693 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res); 1694 1695 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 1696 Op.getOperand(0), DAG.getConstant(0, MVT::i32)); 1697 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 1698 } 1699 1700 static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool HasR2) { 1701 unsigned WidthX = Op.getOperand(0).getValueSizeInBits(); 1702 unsigned WidthY = Op.getOperand(1).getValueSizeInBits(); 1703 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY); 1704 SDValue Const1 = DAG.getConstant(1, MVT::i32); 1705 SDLoc DL(Op); 1706 1707 // Bitcast to integer nodes. 1708 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0)); 1709 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1)); 1710 1711 if (HasR2) { 1712 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y 1713 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X 1714 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y, 1715 DAG.getConstant(WidthY - 1, MVT::i32), Const1); 1716 1717 if (WidthX > WidthY) 1718 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E); 1719 else if (WidthY > WidthX) 1720 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E); 1721 1722 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E, 1723 DAG.getConstant(WidthX - 1, MVT::i32), Const1, X); 1724 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I); 1725 } 1726 1727 // (d)sll SllX, X, 1 1728 // (d)srl SrlX, SllX, 1 1729 // (d)srl SrlY, Y, width(Y)-1 1730 // (d)sll SllY, SrlX, width(Y)-1 1731 // or Or, SrlX, SllY 1732 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1); 1733 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); 1734 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, 1735 DAG.getConstant(WidthY - 1, MVT::i32)); 1736 1737 if (WidthX > WidthY) 1738 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY); 1739 else if (WidthY > WidthX) 1740 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY); 1741 1742 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY, 1743 DAG.getConstant(WidthX - 1, MVT::i32)); 1744 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY); 1745 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or); 1746 } 1747 1748 SDValue 1749 MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 1750 if (Subtarget->hasMips64()) 1751 return lowerFCOPYSIGN64(Op, DAG, Subtarget->hasMips32r2()); 1752 1753 return lowerFCOPYSIGN32(Op, DAG, Subtarget->hasMips32r2()); 1754 } 1755 1756 static SDValue lowerFABS32(SDValue Op, SelectionDAG &DAG, bool HasR2) { 1757 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32); 1758 SDLoc DL(Op); 1759 1760 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it 1761 // to i32. 1762 SDValue X = (Op.getValueType() == MVT::f32) ? 1763 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : 1764 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), 1765 Const1); 1766 1767 // Clear MSB. 1768 if (HasR2) 1769 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, 1770 DAG.getRegister(Mips::ZERO, MVT::i32), 1771 DAG.getConstant(31, MVT::i32), Const1, X); 1772 else { 1773 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); 1774 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); 1775 } 1776 1777 if (Op.getValueType() == MVT::f32) 1778 return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res); 1779 1780 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 1781 Op.getOperand(0), DAG.getConstant(0, MVT::i32)); 1782 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); 1783 } 1784 1785 static SDValue lowerFABS64(SDValue Op, SelectionDAG &DAG, bool HasR2) { 1786 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32); 1787 SDLoc DL(Op); 1788 1789 // Bitcast to integer node. 1790 SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0)); 1791 1792 // Clear MSB. 1793 if (HasR2) 1794 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64, 1795 DAG.getRegister(Mips::ZERO_64, MVT::i64), 1796 DAG.getConstant(63, MVT::i32), Const1, X); 1797 else { 1798 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1); 1799 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1); 1800 } 1801 1802 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res); 1803 } 1804 1805 SDValue 1806 MipsTargetLowering::lowerFABS(SDValue Op, SelectionDAG &DAG) const { 1807 if (Subtarget->hasMips64() && (Op.getValueType() == MVT::f64)) 1808 return lowerFABS64(Op, DAG, Subtarget->hasMips32r2()); 1809 1810 return lowerFABS32(Op, DAG, Subtarget->hasMips32r2()); 1811 } 1812 1813 SDValue MipsTargetLowering:: 1814 lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 1815 // check the depth 1816 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 1817 "Frame address can only be determined for current frame."); 1818 1819 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1820 MFI->setFrameAddressIsTaken(true); 1821 EVT VT = Op.getValueType(); 1822 SDLoc DL(Op); 1823 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL, 1824 IsN64 ? Mips::FP_64 : Mips::FP, VT); 1825 return FrameAddr; 1826 } 1827 1828 SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op, 1829 SelectionDAG &DAG) const { 1830 // check the depth 1831 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 1832 "Return address can be determined only for current frame."); 1833 1834 MachineFunction &MF = DAG.getMachineFunction(); 1835 MachineFrameInfo *MFI = MF.getFrameInfo(); 1836 MVT VT = Op.getSimpleValueType(); 1837 unsigned RA = IsN64 ? Mips::RA_64 : Mips::RA; 1838 MFI->setReturnAddressIsTaken(true); 1839 1840 // Return RA, which contains the return address. Mark it an implicit live-in. 1841 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT)); 1842 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT); 1843 } 1844 1845 // An EH_RETURN is the result of lowering llvm.eh.return which in turn is 1846 // generated from __builtin_eh_return (offset, handler) 1847 // The effect of this is to adjust the stack pointer by "offset" 1848 // and then branch to "handler". 1849 SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) 1850 const { 1851 MachineFunction &MF = DAG.getMachineFunction(); 1852 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 1853 1854 MipsFI->setCallsEhReturn(); 1855 SDValue Chain = Op.getOperand(0); 1856 SDValue Offset = Op.getOperand(1); 1857 SDValue Handler = Op.getOperand(2); 1858 SDLoc DL(Op); 1859 EVT Ty = IsN64 ? MVT::i64 : MVT::i32; 1860 1861 // Store stack offset in V1, store jump target in V0. Glue CopyToReg and 1862 // EH_RETURN nodes, so that instructions are emitted back-to-back. 1863 unsigned OffsetReg = IsN64 ? Mips::V1_64 : Mips::V1; 1864 unsigned AddrReg = IsN64 ? Mips::V0_64 : Mips::V0; 1865 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue()); 1866 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1)); 1867 return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain, 1868 DAG.getRegister(OffsetReg, Ty), 1869 DAG.getRegister(AddrReg, getPointerTy()), 1870 Chain.getValue(1)); 1871 } 1872 1873 SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op, 1874 SelectionDAG &DAG) const { 1875 // FIXME: Need pseudo-fence for 'singlethread' fences 1876 // FIXME: Set SType for weaker fences where supported/appropriate. 1877 unsigned SType = 0; 1878 SDLoc DL(Op); 1879 return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0), 1880 DAG.getConstant(SType, MVT::i32)); 1881 } 1882 1883 SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op, 1884 SelectionDAG &DAG) const { 1885 SDLoc DL(Op); 1886 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 1887 SDValue Shamt = Op.getOperand(2); 1888 1889 // if shamt < 32: 1890 // lo = (shl lo, shamt) 1891 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt)) 1892 // else: 1893 // lo = 0 1894 // hi = (shl lo, shamt[4:0]) 1895 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 1896 DAG.getConstant(-1, MVT::i32)); 1897 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, 1898 DAG.getConstant(1, MVT::i32)); 1899 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo, 1900 Not); 1901 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, Shamt); 1902 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo); 1903 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, MVT::i32, Lo, Shamt); 1904 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 1905 DAG.getConstant(0x20, MVT::i32)); 1906 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, 1907 DAG.getConstant(0, MVT::i32), ShiftLeftLo); 1908 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftLeftLo, Or); 1909 1910 SDValue Ops[2] = {Lo, Hi}; 1911 return DAG.getMergeValues(Ops, 2, DL); 1912 } 1913 1914 SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, 1915 bool IsSRA) const { 1916 SDLoc DL(Op); 1917 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); 1918 SDValue Shamt = Op.getOperand(2); 1919 1920 // if shamt < 32: 1921 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt)) 1922 // if isSRA: 1923 // hi = (sra hi, shamt) 1924 // else: 1925 // hi = (srl hi, shamt) 1926 // else: 1927 // if isSRA: 1928 // lo = (sra hi, shamt[4:0]) 1929 // hi = (sra hi, 31) 1930 // else: 1931 // lo = (srl hi, shamt[4:0]) 1932 // hi = 0 1933 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, 1934 DAG.getConstant(-1, MVT::i32)); 1935 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, 1936 DAG.getConstant(1, MVT::i32)); 1937 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, ShiftLeft1Hi, Not); 1938 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt); 1939 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo); 1940 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32, 1941 Hi, Shamt); 1942 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, 1943 DAG.getConstant(0x20, MVT::i32)); 1944 SDValue Shift31 = DAG.getNode(ISD::SRA, DL, MVT::i32, Hi, 1945 DAG.getConstant(31, MVT::i32)); 1946 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftRightHi, Or); 1947 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, 1948 IsSRA ? Shift31 : DAG.getConstant(0, MVT::i32), 1949 ShiftRightHi); 1950 1951 SDValue Ops[2] = {Lo, Hi}; 1952 return DAG.getMergeValues(Ops, 2, DL); 1953 } 1954 1955 static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, 1956 SDValue Chain, SDValue Src, unsigned Offset) { 1957 SDValue Ptr = LD->getBasePtr(); 1958 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT(); 1959 EVT BasePtrVT = Ptr.getValueType(); 1960 SDLoc DL(LD); 1961 SDVTList VTList = DAG.getVTList(VT, MVT::Other); 1962 1963 if (Offset) 1964 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 1965 DAG.getConstant(Offset, BasePtrVT)); 1966 1967 SDValue Ops[] = { Chain, Ptr, Src }; 1968 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT, 1969 LD->getMemOperand()); 1970 } 1971 1972 // Expand an unaligned 32 or 64-bit integer load node. 1973 SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const { 1974 LoadSDNode *LD = cast<LoadSDNode>(Op); 1975 EVT MemVT = LD->getMemoryVT(); 1976 1977 // Return if load is aligned or if MemVT is neither i32 nor i64. 1978 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) || 1979 ((MemVT != MVT::i32) && (MemVT != MVT::i64))) 1980 return SDValue(); 1981 1982 bool IsLittle = Subtarget->isLittle(); 1983 EVT VT = Op.getValueType(); 1984 ISD::LoadExtType ExtType = LD->getExtensionType(); 1985 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT); 1986 1987 assert((VT == MVT::i32) || (VT == MVT::i64)); 1988 1989 // Expand 1990 // (set dst, (i64 (load baseptr))) 1991 // to 1992 // (set tmp, (ldl (add baseptr, 7), undef)) 1993 // (set dst, (ldr baseptr, tmp)) 1994 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) { 1995 SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef, 1996 IsLittle ? 7 : 0); 1997 return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL, 1998 IsLittle ? 0 : 7); 1999 } 2000 2001 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef, 2002 IsLittle ? 3 : 0); 2003 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL, 2004 IsLittle ? 0 : 3); 2005 2006 // Expand 2007 // (set dst, (i32 (load baseptr))) or 2008 // (set dst, (i64 (sextload baseptr))) or 2009 // (set dst, (i64 (extload baseptr))) 2010 // to 2011 // (set tmp, (lwl (add baseptr, 3), undef)) 2012 // (set dst, (lwr baseptr, tmp)) 2013 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) || 2014 (ExtType == ISD::EXTLOAD)) 2015 return LWR; 2016 2017 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)); 2018 2019 // Expand 2020 // (set dst, (i64 (zextload baseptr))) 2021 // to 2022 // (set tmp0, (lwl (add baseptr, 3), undef)) 2023 // (set tmp1, (lwr baseptr, tmp0)) 2024 // (set tmp2, (shl tmp1, 32)) 2025 // (set dst, (srl tmp2, 32)) 2026 SDLoc DL(LD); 2027 SDValue Const32 = DAG.getConstant(32, MVT::i32); 2028 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32); 2029 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32); 2030 SDValue Ops[] = { SRL, LWR.getValue(1) }; 2031 return DAG.getMergeValues(Ops, 2, DL); 2032 } 2033 2034 static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD, 2035 SDValue Chain, unsigned Offset) { 2036 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue(); 2037 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType(); 2038 SDLoc DL(SD); 2039 SDVTList VTList = DAG.getVTList(MVT::Other); 2040 2041 if (Offset) 2042 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr, 2043 DAG.getConstant(Offset, BasePtrVT)); 2044 2045 SDValue Ops[] = { Chain, Value, Ptr }; 2046 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, 3, MemVT, 2047 SD->getMemOperand()); 2048 } 2049 2050 // Expand an unaligned 32 or 64-bit integer store node. 2051 static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG, 2052 bool IsLittle) { 2053 SDValue Value = SD->getValue(), Chain = SD->getChain(); 2054 EVT VT = Value.getValueType(); 2055 2056 // Expand 2057 // (store val, baseptr) or 2058 // (truncstore val, baseptr) 2059 // to 2060 // (swl val, (add baseptr, 3)) 2061 // (swr val, baseptr) 2062 if ((VT == MVT::i32) || SD->isTruncatingStore()) { 2063 SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain, 2064 IsLittle ? 3 : 0); 2065 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3); 2066 } 2067 2068 assert(VT == MVT::i64); 2069 2070 // Expand 2071 // (store val, baseptr) 2072 // to 2073 // (sdl val, (add baseptr, 7)) 2074 // (sdr val, baseptr) 2075 SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0); 2076 return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7); 2077 } 2078 2079 // Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr). 2080 static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG) { 2081 SDValue Val = SD->getValue(); 2082 2083 if (Val.getOpcode() != ISD::FP_TO_SINT) 2084 return SDValue(); 2085 2086 EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits()); 2087 SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy, 2088 Val.getOperand(0)); 2089 2090 return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(), 2091 SD->getPointerInfo(), SD->isVolatile(), 2092 SD->isNonTemporal(), SD->getAlignment()); 2093 } 2094 2095 SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const { 2096 StoreSDNode *SD = cast<StoreSDNode>(Op); 2097 EVT MemVT = SD->getMemoryVT(); 2098 2099 // Lower unaligned integer stores. 2100 if ((SD->getAlignment() < MemVT.getSizeInBits() / 8) && 2101 ((MemVT == MVT::i32) || (MemVT == MVT::i64))) 2102 return lowerUnalignedIntStore(SD, DAG, Subtarget->isLittle()); 2103 2104 return lowerFP_TO_SINT_STORE(SD, DAG); 2105 } 2106 2107 SDValue MipsTargetLowering::lowerADD(SDValue Op, SelectionDAG &DAG) const { 2108 if (Op->getOperand(0).getOpcode() != ISD::FRAMEADDR 2109 || cast<ConstantSDNode> 2110 (Op->getOperand(0).getOperand(0))->getZExtValue() != 0 2111 || Op->getOperand(1).getOpcode() != ISD::FRAME_TO_ARGS_OFFSET) 2112 return SDValue(); 2113 2114 // The pattern 2115 // (add (frameaddr 0), (frame_to_args_offset)) 2116 // results from lowering llvm.eh.dwarf.cfa intrinsic. Transform it to 2117 // (add FrameObject, 0) 2118 // where FrameObject is a fixed StackObject with offset 0 which points to 2119 // the old stack pointer. 2120 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2121 EVT ValTy = Op->getValueType(0); 2122 int FI = MFI->CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false); 2123 SDValue InArgsAddr = DAG.getFrameIndex(FI, ValTy); 2124 return DAG.getNode(ISD::ADD, SDLoc(Op), ValTy, InArgsAddr, 2125 DAG.getConstant(0, ValTy)); 2126 } 2127 2128 SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op, 2129 SelectionDAG &DAG) const { 2130 EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits()); 2131 SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy, 2132 Op.getOperand(0)); 2133 return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc); 2134 } 2135 2136 //===----------------------------------------------------------------------===// 2137 // Calling Convention Implementation 2138 //===----------------------------------------------------------------------===// 2139 2140 //===----------------------------------------------------------------------===// 2141 // TODO: Implement a generic logic using tblgen that can support this. 2142 // Mips O32 ABI rules: 2143 // --- 2144 // i32 - Passed in A0, A1, A2, A3 and stack 2145 // f32 - Only passed in f32 registers if no int reg has been used yet to hold 2146 // an argument. Otherwise, passed in A1, A2, A3 and stack. 2147 // f64 - Only passed in two aliased f32 registers if no int reg has been used 2148 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is 2149 // not used, it must be shadowed. If only A3 is avaiable, shadow it and 2150 // go to stack. 2151 // 2152 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack. 2153 //===----------------------------------------------------------------------===// 2154 2155 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, 2156 MVT LocVT, CCValAssign::LocInfo LocInfo, 2157 ISD::ArgFlagsTy ArgFlags, CCState &State) { 2158 2159 static const unsigned IntRegsSize=4, FloatRegsSize=2; 2160 2161 static const uint16_t IntRegs[] = { 2162 Mips::A0, Mips::A1, Mips::A2, Mips::A3 2163 }; 2164 static const uint16_t F32Regs[] = { 2165 Mips::F12, Mips::F14 2166 }; 2167 static const uint16_t F64Regs[] = { 2168 Mips::D6, Mips::D7 2169 }; 2170 2171 // Do not process byval args here. 2172 if (ArgFlags.isByVal()) 2173 return true; 2174 2175 // Promote i8 and i16 2176 if (LocVT == MVT::i8 || LocVT == MVT::i16) { 2177 LocVT = MVT::i32; 2178 if (ArgFlags.isSExt()) 2179 LocInfo = CCValAssign::SExt; 2180 else if (ArgFlags.isZExt()) 2181 LocInfo = CCValAssign::ZExt; 2182 else 2183 LocInfo = CCValAssign::AExt; 2184 } 2185 2186 unsigned Reg; 2187 2188 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following 2189 // is true: function is vararg, argument is 3rd or higher, there is previous 2190 // argument which is not f32 or f64. 2191 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 2192 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo; 2193 unsigned OrigAlign = ArgFlags.getOrigAlign(); 2194 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8); 2195 2196 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) { 2197 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2198 // If this is the first part of an i64 arg, 2199 // the allocated register must be either A0 or A2. 2200 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3)) 2201 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2202 LocVT = MVT::i32; 2203 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) { 2204 // Allocate int register and shadow next int register. If first 2205 // available register is Mips::A1 or Mips::A3, shadow it too. 2206 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2207 if (Reg == Mips::A1 || Reg == Mips::A3) 2208 Reg = State.AllocateReg(IntRegs, IntRegsSize); 2209 State.AllocateReg(IntRegs, IntRegsSize); 2210 LocVT = MVT::i32; 2211 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) { 2212 // we are guaranteed to find an available float register 2213 if (ValVT == MVT::f32) { 2214 Reg = State.AllocateReg(F32Regs, FloatRegsSize); 2215 // Shadow int register 2216 State.AllocateReg(IntRegs, IntRegsSize); 2217 } else { 2218 Reg = State.AllocateReg(F64Regs, FloatRegsSize); 2219 // Shadow int registers 2220 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize); 2221 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) 2222 State.AllocateReg(IntRegs, IntRegsSize); 2223 State.AllocateReg(IntRegs, IntRegsSize); 2224 } 2225 } else 2226 llvm_unreachable("Cannot handle this ValVT."); 2227 2228 if (!Reg) { 2229 unsigned Offset = State.AllocateStack(ValVT.getSizeInBits() >> 3, 2230 OrigAlign); 2231 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 2232 } else 2233 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 2234 2235 return false; 2236 } 2237 2238 #include "MipsGenCallingConv.inc" 2239 2240 //===----------------------------------------------------------------------===// 2241 // Call Calling Convention Implementation 2242 //===----------------------------------------------------------------------===// 2243 2244 static const unsigned O32IntRegsSize = 4; 2245 2246 // Return next O32 integer argument register. 2247 static unsigned getNextIntArgReg(unsigned Reg) { 2248 assert((Reg == Mips::A0) || (Reg == Mips::A2)); 2249 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3; 2250 } 2251 2252 SDValue 2253 MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset, 2254 SDValue Chain, SDValue Arg, SDLoc DL, 2255 bool IsTailCall, SelectionDAG &DAG) const { 2256 if (!IsTailCall) { 2257 SDValue PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, 2258 DAG.getIntPtrConstant(Offset)); 2259 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo(), false, 2260 false, 0); 2261 } 2262 2263 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2264 int FI = MFI->CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false); 2265 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2266 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(), 2267 /*isVolatile=*/ true, false, 0); 2268 } 2269 2270 void MipsTargetLowering:: 2271 getOpndList(SmallVectorImpl<SDValue> &Ops, 2272 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 2273 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 2274 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const { 2275 // Insert node "GP copy globalreg" before call to function. 2276 // 2277 // R_MIPS_CALL* operators (emitted when non-internal functions are called 2278 // in PIC mode) allow symbols to be resolved via lazy binding. 2279 // The lazy binding stub requires GP to point to the GOT. 2280 if (IsPICCall && !InternalLinkage) { 2281 unsigned GPReg = IsN64 ? Mips::GP_64 : Mips::GP; 2282 EVT Ty = IsN64 ? MVT::i64 : MVT::i32; 2283 RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty))); 2284 } 2285 2286 // Build a sequence of copy-to-reg nodes chained together with token 2287 // chain and flag operands which copy the outgoing args into registers. 2288 // The InFlag in necessary since all emitted instructions must be 2289 // stuck together. 2290 SDValue InFlag; 2291 2292 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2293 Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first, 2294 RegsToPass[i].second, InFlag); 2295 InFlag = Chain.getValue(1); 2296 } 2297 2298 // Add argument registers to the end of the list so that they are 2299 // known live into the call. 2300 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2301 Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first, 2302 RegsToPass[i].second.getValueType())); 2303 2304 // Add a register mask operand representing the call-preserved registers. 2305 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 2306 const uint32_t *Mask = TRI->getCallPreservedMask(CLI.CallConv); 2307 assert(Mask && "Missing call preserved mask for calling convention"); 2308 if (Subtarget->inMips16HardFloat()) { 2309 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) { 2310 llvm::StringRef Sym = G->getGlobal()->getName(); 2311 Function *F = G->getGlobal()->getParent()->getFunction(Sym); 2312 if (F->hasFnAttribute("__Mips16RetHelper")) { 2313 Mask = MipsRegisterInfo::getMips16RetHelperMask(); 2314 } 2315 } 2316 } 2317 Ops.push_back(CLI.DAG.getRegisterMask(Mask)); 2318 2319 if (InFlag.getNode()) 2320 Ops.push_back(InFlag); 2321 } 2322 2323 /// LowerCall - functions arguments are copied from virtual regs to 2324 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 2325 SDValue 2326 MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 2327 SmallVectorImpl<SDValue> &InVals) const { 2328 SelectionDAG &DAG = CLI.DAG; 2329 SDLoc DL = CLI.DL; 2330 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; 2331 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; 2332 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; 2333 SDValue Chain = CLI.Chain; 2334 SDValue Callee = CLI.Callee; 2335 bool &IsTailCall = CLI.IsTailCall; 2336 CallingConv::ID CallConv = CLI.CallConv; 2337 bool IsVarArg = CLI.IsVarArg; 2338 2339 MachineFunction &MF = DAG.getMachineFunction(); 2340 MachineFrameInfo *MFI = MF.getFrameInfo(); 2341 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering(); 2342 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 2343 2344 // Analyze operands of the call, assigning locations to each operand. 2345 SmallVector<CCValAssign, 16> ArgLocs; 2346 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), 2347 getTargetMachine(), ArgLocs, *DAG.getContext()); 2348 MipsCC::SpecialCallingConvType SpecialCallingConv = 2349 getSpecialCallingConv(Callee); 2350 MipsCC MipsCCInfo(CallConv, IsO32, CCInfo, SpecialCallingConv); 2351 2352 MipsCCInfo.analyzeCallOperands(Outs, IsVarArg, 2353 getTargetMachine().Options.UseSoftFloat, 2354 Callee.getNode(), CLI.Args); 2355 2356 // Get a count of how many bytes are to be pushed on the stack. 2357 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 2358 2359 // Check if it's really possible to do a tail call. 2360 if (IsTailCall) 2361 IsTailCall = 2362 isEligibleForTailCallOptimization(MipsCCInfo, NextStackOffset, 2363 *MF.getInfo<MipsFunctionInfo>()); 2364 2365 if (IsTailCall) 2366 ++NumTailCalls; 2367 2368 // Chain is the output chain of the last Load/Store or CopyToReg node. 2369 // ByValChain is the output chain of the last Memcpy node created for copying 2370 // byval arguments to the stack. 2371 unsigned StackAlignment = TFL->getStackAlignment(); 2372 NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment); 2373 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true); 2374 2375 if (!IsTailCall) 2376 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal, DL); 2377 2378 SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, 2379 IsN64 ? Mips::SP_64 : Mips::SP, 2380 getPointerTy()); 2381 2382 // With EABI is it possible to have 16 args on registers. 2383 std::deque< std::pair<unsigned, SDValue> > RegsToPass; 2384 SmallVector<SDValue, 8> MemOpChains; 2385 MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin(); 2386 2387 // Walk the register/memloc assignments, inserting copies/loads. 2388 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2389 SDValue Arg = OutVals[i]; 2390 CCValAssign &VA = ArgLocs[i]; 2391 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); 2392 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2393 2394 // ByVal Arg. 2395 if (Flags.isByVal()) { 2396 assert(Flags.getByValSize() && 2397 "ByVal args of size 0 should have been ignored by front-end."); 2398 assert(ByValArg != MipsCCInfo.byval_end()); 2399 assert(!IsTailCall && 2400 "Do not tail-call optimize if there is a byval argument."); 2401 passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg, 2402 MipsCCInfo, *ByValArg, Flags, Subtarget->isLittle()); 2403 ++ByValArg; 2404 continue; 2405 } 2406 2407 // Promote the value if needed. 2408 switch (VA.getLocInfo()) { 2409 default: llvm_unreachable("Unknown loc info!"); 2410 case CCValAssign::Full: 2411 if (VA.isRegLoc()) { 2412 if ((ValVT == MVT::f32 && LocVT == MVT::i32) || 2413 (ValVT == MVT::f64 && LocVT == MVT::i64) || 2414 (ValVT == MVT::i64 && LocVT == MVT::f64)) 2415 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); 2416 else if (ValVT == MVT::f64 && LocVT == MVT::i32) { 2417 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2418 Arg, DAG.getConstant(0, MVT::i32)); 2419 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 2420 Arg, DAG.getConstant(1, MVT::i32)); 2421 if (!Subtarget->isLittle()) 2422 std::swap(Lo, Hi); 2423 unsigned LocRegLo = VA.getLocReg(); 2424 unsigned LocRegHigh = getNextIntArgReg(LocRegLo); 2425 RegsToPass.push_back(std::make_pair(LocRegLo, Lo)); 2426 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi)); 2427 continue; 2428 } 2429 } 2430 break; 2431 case CCValAssign::SExt: 2432 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg); 2433 break; 2434 case CCValAssign::ZExt: 2435 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg); 2436 break; 2437 case CCValAssign::AExt: 2438 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg); 2439 break; 2440 } 2441 2442 // Arguments that can be passed on register must be kept at 2443 // RegsToPass vector 2444 if (VA.isRegLoc()) { 2445 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2446 continue; 2447 } 2448 2449 // Register can't get to this point... 2450 assert(VA.isMemLoc()); 2451 2452 // emit ISD::STORE whichs stores the 2453 // parameter value to a stack Location 2454 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(), 2455 Chain, Arg, DL, IsTailCall, DAG)); 2456 } 2457 2458 // Transform all store nodes into one single node because all store 2459 // nodes are independent of each other. 2460 if (!MemOpChains.empty()) 2461 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 2462 &MemOpChains[0], MemOpChains.size()); 2463 2464 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 2465 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 2466 // node so that legalize doesn't hack it. 2467 bool IsPICCall = (IsN64 || IsPIC); // true if calls are translated to jalr $25 2468 bool GlobalOrExternal = false, InternalLinkage = false; 2469 SDValue CalleeLo; 2470 2471 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2472 if (IsPICCall) { 2473 InternalLinkage = G->getGlobal()->hasInternalLinkage(); 2474 2475 if (InternalLinkage) 2476 Callee = getAddrLocal(Callee, DAG, HasMips64); 2477 else if (LargeGOT) 2478 Callee = getAddrGlobalLargeGOT(Callee, DAG, MipsII::MO_CALL_HI16, 2479 MipsII::MO_CALL_LO16); 2480 else 2481 Callee = getAddrGlobal(Callee, DAG, MipsII::MO_GOT_CALL); 2482 } else 2483 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, getPointerTy(), 0, 2484 MipsII::MO_NO_FLAG); 2485 GlobalOrExternal = true; 2486 } 2487 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2488 if (!IsN64 && !IsPIC) // !N64 && static 2489 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 2490 MipsII::MO_NO_FLAG); 2491 else if (LargeGOT) 2492 Callee = getAddrGlobalLargeGOT(Callee, DAG, MipsII::MO_CALL_HI16, 2493 MipsII::MO_CALL_LO16); 2494 else // N64 || PIC 2495 Callee = getAddrGlobal(Callee, DAG, MipsII::MO_GOT_CALL); 2496 2497 GlobalOrExternal = true; 2498 } 2499 2500 SmallVector<SDValue, 8> Ops(1, Chain); 2501 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2502 2503 getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, InternalLinkage, 2504 CLI, Callee, Chain); 2505 2506 if (IsTailCall) 2507 return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, &Ops[0], Ops.size()); 2508 2509 Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, &Ops[0], Ops.size()); 2510 SDValue InFlag = Chain.getValue(1); 2511 2512 // Create the CALLSEQ_END node. 2513 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal, 2514 DAG.getIntPtrConstant(0, true), InFlag, DL); 2515 InFlag = Chain.getValue(1); 2516 2517 // Handle result values, copying them out of physregs into vregs that we 2518 // return. 2519 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, 2520 Ins, DL, DAG, InVals, CLI.Callee.getNode(), CLI.RetTy); 2521 } 2522 2523 /// LowerCallResult - Lower the result values of a call into the 2524 /// appropriate copies out of appropriate physical registers. 2525 SDValue 2526 MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 2527 CallingConv::ID CallConv, bool IsVarArg, 2528 const SmallVectorImpl<ISD::InputArg> &Ins, 2529 SDLoc DL, SelectionDAG &DAG, 2530 SmallVectorImpl<SDValue> &InVals, 2531 const SDNode *CallNode, 2532 const Type *RetTy) const { 2533 // Assign locations to each value returned by this call. 2534 SmallVector<CCValAssign, 16> RVLocs; 2535 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), 2536 getTargetMachine(), RVLocs, *DAG.getContext()); 2537 MipsCC MipsCCInfo(CallConv, IsO32, CCInfo); 2538 2539 MipsCCInfo.analyzeCallResult(Ins, getTargetMachine().Options.UseSoftFloat, 2540 CallNode, RetTy); 2541 2542 // Copy all of the result registers out of their specified physreg. 2543 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2544 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(), 2545 RVLocs[i].getLocVT(), InFlag); 2546 Chain = Val.getValue(1); 2547 InFlag = Val.getValue(2); 2548 2549 if (RVLocs[i].getValVT() != RVLocs[i].getLocVT()) 2550 Val = DAG.getNode(ISD::BITCAST, DL, RVLocs[i].getValVT(), Val); 2551 2552 InVals.push_back(Val); 2553 } 2554 2555 return Chain; 2556 } 2557 2558 //===----------------------------------------------------------------------===// 2559 // Formal Arguments Calling Convention Implementation 2560 //===----------------------------------------------------------------------===// 2561 /// LowerFormalArguments - transform physical registers into virtual registers 2562 /// and generate load operations for arguments places on the stack. 2563 SDValue 2564 MipsTargetLowering::LowerFormalArguments(SDValue Chain, 2565 CallingConv::ID CallConv, 2566 bool IsVarArg, 2567 const SmallVectorImpl<ISD::InputArg> &Ins, 2568 SDLoc DL, SelectionDAG &DAG, 2569 SmallVectorImpl<SDValue> &InVals) 2570 const { 2571 MachineFunction &MF = DAG.getMachineFunction(); 2572 MachineFrameInfo *MFI = MF.getFrameInfo(); 2573 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2574 2575 MipsFI->setVarArgsFrameIndex(0); 2576 2577 // Used with vargs to acumulate store chains. 2578 std::vector<SDValue> OutChains; 2579 2580 // Assign locations to all of the incoming arguments. 2581 SmallVector<CCValAssign, 16> ArgLocs; 2582 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), 2583 getTargetMachine(), ArgLocs, *DAG.getContext()); 2584 MipsCC MipsCCInfo(CallConv, IsO32, CCInfo); 2585 Function::const_arg_iterator FuncArg = 2586 DAG.getMachineFunction().getFunction()->arg_begin(); 2587 bool UseSoftFloat = getTargetMachine().Options.UseSoftFloat; 2588 2589 MipsCCInfo.analyzeFormalArguments(Ins, UseSoftFloat, FuncArg); 2590 MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(), 2591 MipsCCInfo.hasByValArg()); 2592 2593 unsigned CurArgIdx = 0; 2594 MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin(); 2595 2596 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2597 CCValAssign &VA = ArgLocs[i]; 2598 std::advance(FuncArg, Ins[i].OrigArgIndex - CurArgIdx); 2599 CurArgIdx = Ins[i].OrigArgIndex; 2600 EVT ValVT = VA.getValVT(); 2601 ISD::ArgFlagsTy Flags = Ins[i].Flags; 2602 bool IsRegLoc = VA.isRegLoc(); 2603 2604 if (Flags.isByVal()) { 2605 assert(Flags.getByValSize() && 2606 "ByVal args of size 0 should have been ignored by front-end."); 2607 assert(ByValArg != MipsCCInfo.byval_end()); 2608 copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg, 2609 MipsCCInfo, *ByValArg); 2610 ++ByValArg; 2611 continue; 2612 } 2613 2614 // Arguments stored on registers 2615 if (IsRegLoc) { 2616 EVT RegVT = VA.getLocVT(); 2617 unsigned ArgReg = VA.getLocReg(); 2618 const TargetRegisterClass *RC; 2619 2620 if (RegVT == MVT::i32) 2621 RC = Subtarget->inMips16Mode()? &Mips::CPU16RegsRegClass : 2622 &Mips::GPR32RegClass; 2623 else if (RegVT == MVT::i64) 2624 RC = &Mips::GPR64RegClass; 2625 else if (RegVT == MVT::f32) 2626 RC = &Mips::FGR32RegClass; 2627 else if (RegVT == MVT::f64) 2628 RC = HasMips64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; 2629 else 2630 llvm_unreachable("RegVT not supported by FormalArguments Lowering"); 2631 2632 // Transform the arguments stored on 2633 // physical registers into virtual ones 2634 unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC); 2635 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); 2636 2637 // If this is an 8 or 16-bit value, it has been passed promoted 2638 // to 32 bits. Insert an assert[sz]ext to capture this, then 2639 // truncate to the right size. 2640 if (VA.getLocInfo() != CCValAssign::Full) { 2641 unsigned Opcode = 0; 2642 if (VA.getLocInfo() == CCValAssign::SExt) 2643 Opcode = ISD::AssertSext; 2644 else if (VA.getLocInfo() == CCValAssign::ZExt) 2645 Opcode = ISD::AssertZext; 2646 if (Opcode) 2647 ArgValue = DAG.getNode(Opcode, DL, RegVT, ArgValue, 2648 DAG.getValueType(ValVT)); 2649 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, ValVT, ArgValue); 2650 } 2651 2652 // Handle floating point arguments passed in integer registers and 2653 // long double arguments passed in floating point registers. 2654 if ((RegVT == MVT::i32 && ValVT == MVT::f32) || 2655 (RegVT == MVT::i64 && ValVT == MVT::f64) || 2656 (RegVT == MVT::f64 && ValVT == MVT::i64)) 2657 ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue); 2658 else if (IsO32 && RegVT == MVT::i32 && ValVT == MVT::f64) { 2659 unsigned Reg2 = addLiveIn(DAG.getMachineFunction(), 2660 getNextIntArgReg(ArgReg), RC); 2661 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT); 2662 if (!Subtarget->isLittle()) 2663 std::swap(ArgValue, ArgValue2); 2664 ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, 2665 ArgValue, ArgValue2); 2666 } 2667 2668 InVals.push_back(ArgValue); 2669 } else { // VA.isRegLoc() 2670 2671 // sanity check 2672 assert(VA.isMemLoc()); 2673 2674 // The stack pointer offset is relative to the caller stack frame. 2675 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 2676 VA.getLocMemOffset(), true); 2677 2678 // Create load nodes to retrieve arguments from the stack 2679 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2680 InVals.push_back(DAG.getLoad(ValVT, DL, Chain, FIN, 2681 MachinePointerInfo::getFixedStack(FI), 2682 false, false, false, 0)); 2683 } 2684 } 2685 2686 // The mips ABIs for returning structs by value requires that we copy 2687 // the sret argument into $v0 for the return. Save the argument into 2688 // a virtual register so that we can access it from the return points. 2689 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 2690 unsigned Reg = MipsFI->getSRetReturnReg(); 2691 if (!Reg) { 2692 Reg = MF.getRegInfo(). 2693 createVirtualRegister(getRegClassFor(IsN64 ? MVT::i64 : MVT::i32)); 2694 MipsFI->setSRetReturnReg(Reg); 2695 } 2696 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[0]); 2697 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain); 2698 } 2699 2700 if (IsVarArg) 2701 writeVarArgRegs(OutChains, MipsCCInfo, Chain, DL, DAG); 2702 2703 // All stores are grouped in one node to allow the matching between 2704 // the size of Ins and InVals. This only happens when on varg functions 2705 if (!OutChains.empty()) { 2706 OutChains.push_back(Chain); 2707 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 2708 &OutChains[0], OutChains.size()); 2709 } 2710 2711 return Chain; 2712 } 2713 2714 //===----------------------------------------------------------------------===// 2715 // Return Value Calling Convention Implementation 2716 //===----------------------------------------------------------------------===// 2717 2718 bool 2719 MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv, 2720 MachineFunction &MF, bool IsVarArg, 2721 const SmallVectorImpl<ISD::OutputArg> &Outs, 2722 LLVMContext &Context) const { 2723 SmallVector<CCValAssign, 16> RVLocs; 2724 CCState CCInfo(CallConv, IsVarArg, MF, getTargetMachine(), 2725 RVLocs, Context); 2726 return CCInfo.CheckReturn(Outs, RetCC_Mips); 2727 } 2728 2729 SDValue 2730 MipsTargetLowering::LowerReturn(SDValue Chain, 2731 CallingConv::ID CallConv, bool IsVarArg, 2732 const SmallVectorImpl<ISD::OutputArg> &Outs, 2733 const SmallVectorImpl<SDValue> &OutVals, 2734 SDLoc DL, SelectionDAG &DAG) const { 2735 // CCValAssign - represent the assignment of 2736 // the return value to a location 2737 SmallVector<CCValAssign, 16> RVLocs; 2738 MachineFunction &MF = DAG.getMachineFunction(); 2739 2740 // CCState - Info about the registers and stack slot. 2741 CCState CCInfo(CallConv, IsVarArg, MF, getTargetMachine(), RVLocs, 2742 *DAG.getContext()); 2743 MipsCC MipsCCInfo(CallConv, IsO32, CCInfo); 2744 2745 // Analyze return values. 2746 MipsCCInfo.analyzeReturn(Outs, getTargetMachine().Options.UseSoftFloat, 2747 MF.getFunction()->getReturnType()); 2748 2749 SDValue Flag; 2750 SmallVector<SDValue, 4> RetOps(1, Chain); 2751 2752 // Copy the result values into the output registers. 2753 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2754 SDValue Val = OutVals[i]; 2755 CCValAssign &VA = RVLocs[i]; 2756 assert(VA.isRegLoc() && "Can only return in registers!"); 2757 2758 if (RVLocs[i].getValVT() != RVLocs[i].getLocVT()) 2759 Val = DAG.getNode(ISD::BITCAST, DL, RVLocs[i].getLocVT(), Val); 2760 2761 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag); 2762 2763 // Guarantee that all emitted copies are stuck together with flags. 2764 Flag = Chain.getValue(1); 2765 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 2766 } 2767 2768 // The mips ABIs for returning structs by value requires that we copy 2769 // the sret argument into $v0 for the return. We saved the argument into 2770 // a virtual register in the entry block, so now we copy the value out 2771 // and into $v0. 2772 if (MF.getFunction()->hasStructRetAttr()) { 2773 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2774 unsigned Reg = MipsFI->getSRetReturnReg(); 2775 2776 if (!Reg) 2777 llvm_unreachable("sret virtual register not created in the entry block"); 2778 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy()); 2779 unsigned V0 = IsN64 ? Mips::V0_64 : Mips::V0; 2780 2781 Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag); 2782 Flag = Chain.getValue(1); 2783 RetOps.push_back(DAG.getRegister(V0, getPointerTy())); 2784 } 2785 2786 RetOps[0] = Chain; // Update chain. 2787 2788 // Add the flag if we have it. 2789 if (Flag.getNode()) 2790 RetOps.push_back(Flag); 2791 2792 // Return on Mips is always a "jr $ra" 2793 return DAG.getNode(MipsISD::Ret, DL, MVT::Other, &RetOps[0], RetOps.size()); 2794 } 2795 2796 //===----------------------------------------------------------------------===// 2797 // Mips Inline Assembly Support 2798 //===----------------------------------------------------------------------===// 2799 2800 /// getConstraintType - Given a constraint letter, return the type of 2801 /// constraint it is for this target. 2802 MipsTargetLowering::ConstraintType MipsTargetLowering:: 2803 getConstraintType(const std::string &Constraint) const 2804 { 2805 // Mips specific constrainy 2806 // GCC config/mips/constraints.md 2807 // 2808 // 'd' : An address register. Equivalent to r 2809 // unless generating MIPS16 code. 2810 // 'y' : Equivalent to r; retained for 2811 // backwards compatibility. 2812 // 'c' : A register suitable for use in an indirect 2813 // jump. This will always be $25 for -mabicalls. 2814 // 'l' : The lo register. 1 word storage. 2815 // 'x' : The hilo register pair. Double word storage. 2816 if (Constraint.size() == 1) { 2817 switch (Constraint[0]) { 2818 default : break; 2819 case 'd': 2820 case 'y': 2821 case 'f': 2822 case 'c': 2823 case 'l': 2824 case 'x': 2825 return C_RegisterClass; 2826 case 'R': 2827 return C_Memory; 2828 } 2829 } 2830 return TargetLowering::getConstraintType(Constraint); 2831 } 2832 2833 /// Examine constraint type and operand type and determine a weight value. 2834 /// This object must already have been set up with the operand type 2835 /// and the current alternative constraint selected. 2836 TargetLowering::ConstraintWeight 2837 MipsTargetLowering::getSingleConstraintMatchWeight( 2838 AsmOperandInfo &info, const char *constraint) const { 2839 ConstraintWeight weight = CW_Invalid; 2840 Value *CallOperandVal = info.CallOperandVal; 2841 // If we don't have a value, we can't do a match, 2842 // but allow it at the lowest weight. 2843 if (CallOperandVal == NULL) 2844 return CW_Default; 2845 Type *type = CallOperandVal->getType(); 2846 // Look at the constraint type. 2847 switch (*constraint) { 2848 default: 2849 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 2850 break; 2851 case 'd': 2852 case 'y': 2853 if (type->isIntegerTy()) 2854 weight = CW_Register; 2855 break; 2856 case 'f': 2857 if (type->isFloatTy()) 2858 weight = CW_Register; 2859 break; 2860 case 'c': // $25 for indirect jumps 2861 case 'l': // lo register 2862 case 'x': // hilo register pair 2863 if (type->isIntegerTy()) 2864 weight = CW_SpecificReg; 2865 break; 2866 case 'I': // signed 16 bit immediate 2867 case 'J': // integer zero 2868 case 'K': // unsigned 16 bit immediate 2869 case 'L': // signed 32 bit immediate where lower 16 bits are 0 2870 case 'N': // immediate in the range of -65535 to -1 (inclusive) 2871 case 'O': // signed 15 bit immediate (+- 16383) 2872 case 'P': // immediate in the range of 65535 to 1 (inclusive) 2873 if (isa<ConstantInt>(CallOperandVal)) 2874 weight = CW_Constant; 2875 break; 2876 case 'R': 2877 weight = CW_Memory; 2878 break; 2879 } 2880 return weight; 2881 } 2882 2883 /// Given a register class constraint, like 'r', if this corresponds directly 2884 /// to an LLVM register class, return a register of 0 and the register class 2885 /// pointer. 2886 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering:: 2887 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const 2888 { 2889 if (Constraint.size() == 1) { 2890 switch (Constraint[0]) { 2891 case 'd': // Address register. Same as 'r' unless generating MIPS16 code. 2892 case 'y': // Same as 'r'. Exists for compatibility. 2893 case 'r': 2894 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { 2895 if (Subtarget->inMips16Mode()) 2896 return std::make_pair(0U, &Mips::CPU16RegsRegClass); 2897 return std::make_pair(0U, &Mips::GPR32RegClass); 2898 } 2899 if (VT == MVT::i64 && !HasMips64) 2900 return std::make_pair(0U, &Mips::GPR32RegClass); 2901 if (VT == MVT::i64 && HasMips64) 2902 return std::make_pair(0U, &Mips::GPR64RegClass); 2903 // This will generate an error message 2904 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 2905 case 'f': 2906 if (VT == MVT::f32) 2907 return std::make_pair(0U, &Mips::FGR32RegClass); 2908 if ((VT == MVT::f64) && (!Subtarget->isSingleFloat())) { 2909 if (Subtarget->isFP64bit()) 2910 return std::make_pair(0U, &Mips::FGR64RegClass); 2911 return std::make_pair(0U, &Mips::AFGR64RegClass); 2912 } 2913 break; 2914 case 'c': // register suitable for indirect jump 2915 if (VT == MVT::i32) 2916 return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass); 2917 assert(VT == MVT::i64 && "Unexpected type."); 2918 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass); 2919 case 'l': // register suitable for indirect jump 2920 if (VT == MVT::i32) 2921 return std::make_pair((unsigned)Mips::LO, &Mips::LORegsRegClass); 2922 return std::make_pair((unsigned)Mips::LO64, &Mips::LORegs64RegClass); 2923 case 'x': // register suitable for indirect jump 2924 // Fixme: Not triggering the use of both hi and low 2925 // This will generate an error message 2926 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); 2927 } 2928 } 2929 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 2930 } 2931 2932 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 2933 /// vector. If it is invalid, don't add anything to Ops. 2934 void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 2935 std::string &Constraint, 2936 std::vector<SDValue>&Ops, 2937 SelectionDAG &DAG) const { 2938 SDValue Result(0, 0); 2939 2940 // Only support length 1 constraints for now. 2941 if (Constraint.length() > 1) return; 2942 2943 char ConstraintLetter = Constraint[0]; 2944 switch (ConstraintLetter) { 2945 default: break; // This will fall through to the generic implementation 2946 case 'I': // Signed 16 bit constant 2947 // If this fails, the parent routine will give an error 2948 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 2949 EVT Type = Op.getValueType(); 2950 int64_t Val = C->getSExtValue(); 2951 if (isInt<16>(Val)) { 2952 Result = DAG.getTargetConstant(Val, Type); 2953 break; 2954 } 2955 } 2956 return; 2957 case 'J': // integer zero 2958 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 2959 EVT Type = Op.getValueType(); 2960 int64_t Val = C->getZExtValue(); 2961 if (Val == 0) { 2962 Result = DAG.getTargetConstant(0, Type); 2963 break; 2964 } 2965 } 2966 return; 2967 case 'K': // unsigned 16 bit immediate 2968 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 2969 EVT Type = Op.getValueType(); 2970 uint64_t Val = (uint64_t)C->getZExtValue(); 2971 if (isUInt<16>(Val)) { 2972 Result = DAG.getTargetConstant(Val, Type); 2973 break; 2974 } 2975 } 2976 return; 2977 case 'L': // signed 32 bit immediate where lower 16 bits are 0 2978 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 2979 EVT Type = Op.getValueType(); 2980 int64_t Val = C->getSExtValue(); 2981 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){ 2982 Result = DAG.getTargetConstant(Val, Type); 2983 break; 2984 } 2985 } 2986 return; 2987 case 'N': // immediate in the range of -65535 to -1 (inclusive) 2988 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 2989 EVT Type = Op.getValueType(); 2990 int64_t Val = C->getSExtValue(); 2991 if ((Val >= -65535) && (Val <= -1)) { 2992 Result = DAG.getTargetConstant(Val, Type); 2993 break; 2994 } 2995 } 2996 return; 2997 case 'O': // signed 15 bit immediate 2998 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 2999 EVT Type = Op.getValueType(); 3000 int64_t Val = C->getSExtValue(); 3001 if ((isInt<15>(Val))) { 3002 Result = DAG.getTargetConstant(Val, Type); 3003 break; 3004 } 3005 } 3006 return; 3007 case 'P': // immediate in the range of 1 to 65535 (inclusive) 3008 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3009 EVT Type = Op.getValueType(); 3010 int64_t Val = C->getSExtValue(); 3011 if ((Val <= 65535) && (Val >= 1)) { 3012 Result = DAG.getTargetConstant(Val, Type); 3013 break; 3014 } 3015 } 3016 return; 3017 } 3018 3019 if (Result.getNode()) { 3020 Ops.push_back(Result); 3021 return; 3022 } 3023 3024 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 3025 } 3026 3027 bool 3028 MipsTargetLowering::isLegalAddressingMode(const AddrMode &AM, Type *Ty) const { 3029 // No global is ever allowed as a base. 3030 if (AM.BaseGV) 3031 return false; 3032 3033 switch (AM.Scale) { 3034 case 0: // "r+i" or just "i", depending on HasBaseReg. 3035 break; 3036 case 1: 3037 if (!AM.HasBaseReg) // allow "r+i". 3038 break; 3039 return false; // disallow "r+r" or "r+r+i". 3040 default: 3041 return false; 3042 } 3043 3044 return true; 3045 } 3046 3047 bool 3048 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 3049 // The Mips target isn't yet aware of offsets. 3050 return false; 3051 } 3052 3053 EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 3054 unsigned SrcAlign, 3055 bool IsMemset, bool ZeroMemset, 3056 bool MemcpyStrSrc, 3057 MachineFunction &MF) const { 3058 if (Subtarget->hasMips64()) 3059 return MVT::i64; 3060 3061 return MVT::i32; 3062 } 3063 3064 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 3065 if (VT != MVT::f32 && VT != MVT::f64) 3066 return false; 3067 if (Imm.isNegZero()) 3068 return false; 3069 return Imm.isZero(); 3070 } 3071 3072 unsigned MipsTargetLowering::getJumpTableEncoding() const { 3073 if (IsN64) 3074 return MachineJumpTableInfo::EK_GPRel64BlockAddress; 3075 3076 return TargetLowering::getJumpTableEncoding(); 3077 } 3078 3079 /// This function returns true if CallSym is a long double emulation routine. 3080 static bool isF128SoftLibCall(const char *CallSym) { 3081 const char *const LibCalls[] = 3082 {"__addtf3", "__divtf3", "__eqtf2", "__extenddftf2", "__extendsftf2", 3083 "__fixtfdi", "__fixtfsi", "__fixtfti", "__fixunstfdi", "__fixunstfsi", 3084 "__fixunstfti", "__floatditf", "__floatsitf", "__floattitf", 3085 "__floatunditf", "__floatunsitf", "__floatuntitf", "__getf2", "__gttf2", 3086 "__letf2", "__lttf2", "__multf3", "__netf2", "__powitf2", "__subtf3", 3087 "__trunctfdf2", "__trunctfsf2", "__unordtf2", 3088 "ceill", "copysignl", "cosl", "exp2l", "expl", "floorl", "fmal", "fmodl", 3089 "log10l", "log2l", "logl", "nearbyintl", "powl", "rintl", "sinl", "sqrtl", 3090 "truncl"}; 3091 3092 const char * const *End = LibCalls + array_lengthof(LibCalls); 3093 3094 // Check that LibCalls is sorted alphabetically. 3095 MipsTargetLowering::LTStr Comp; 3096 3097 #ifndef NDEBUG 3098 for (const char * const *I = LibCalls; I < End - 1; ++I) 3099 assert(Comp(*I, *(I + 1))); 3100 #endif 3101 3102 return std::binary_search(LibCalls, End, CallSym, Comp); 3103 } 3104 3105 /// This function returns true if Ty is fp128 or i128 which was originally a 3106 /// fp128. 3107 static bool originalTypeIsF128(const Type *Ty, const SDNode *CallNode) { 3108 if (Ty->isFP128Ty()) 3109 return true; 3110 3111 const ExternalSymbolSDNode *ES = 3112 dyn_cast_or_null<const ExternalSymbolSDNode>(CallNode); 3113 3114 // If the Ty is i128 and the function being called is a long double emulation 3115 // routine, then the original type is f128. 3116 return (ES && Ty->isIntegerTy(128) && isF128SoftLibCall(ES->getSymbol())); 3117 } 3118 3119 MipsTargetLowering::MipsCC::SpecialCallingConvType 3120 MipsTargetLowering::getSpecialCallingConv(SDValue Callee) const { 3121 MipsCC::SpecialCallingConvType SpecialCallingConv = 3122 MipsCC::NoSpecialCallingConv;; 3123 if (Subtarget->inMips16HardFloat()) { 3124 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 3125 llvm::StringRef Sym = G->getGlobal()->getName(); 3126 Function *F = G->getGlobal()->getParent()->getFunction(Sym); 3127 if (F->hasFnAttribute("__Mips16RetHelper")) { 3128 SpecialCallingConv = MipsCC::Mips16RetHelperConv; 3129 } 3130 } 3131 } 3132 return SpecialCallingConv; 3133 } 3134 3135 MipsTargetLowering::MipsCC::MipsCC( 3136 CallingConv::ID CC, bool IsO32_, CCState &Info, 3137 MipsCC::SpecialCallingConvType SpecialCallingConv_) 3138 : CCInfo(Info), CallConv(CC), IsO32(IsO32_), 3139 SpecialCallingConv(SpecialCallingConv_){ 3140 // Pre-allocate reserved argument area. 3141 CCInfo.AllocateStack(reservedArgArea(), 1); 3142 } 3143 3144 3145 void MipsTargetLowering::MipsCC:: 3146 analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Args, 3147 bool IsVarArg, bool IsSoftFloat, const SDNode *CallNode, 3148 std::vector<ArgListEntry> &FuncArgs) { 3149 assert((CallConv != CallingConv::Fast || !IsVarArg) && 3150 "CallingConv::Fast shouldn't be used for vararg functions."); 3151 3152 unsigned NumOpnds = Args.size(); 3153 llvm::CCAssignFn *FixedFn = fixedArgFn(), *VarFn = varArgFn(); 3154 3155 for (unsigned I = 0; I != NumOpnds; ++I) { 3156 MVT ArgVT = Args[I].VT; 3157 ISD::ArgFlagsTy ArgFlags = Args[I].Flags; 3158 bool R; 3159 3160 if (ArgFlags.isByVal()) { 3161 handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags); 3162 continue; 3163 } 3164 3165 if (IsVarArg && !Args[I].IsFixed) 3166 R = VarFn(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo); 3167 else { 3168 MVT RegVT = getRegVT(ArgVT, FuncArgs[Args[I].OrigArgIndex].Ty, CallNode, 3169 IsSoftFloat); 3170 R = FixedFn(I, ArgVT, RegVT, CCValAssign::Full, ArgFlags, CCInfo); 3171 } 3172 3173 if (R) { 3174 #ifndef NDEBUG 3175 dbgs() << "Call operand #" << I << " has unhandled type " 3176 << EVT(ArgVT).getEVTString(); 3177 #endif 3178 llvm_unreachable(0); 3179 } 3180 } 3181 } 3182 3183 void MipsTargetLowering::MipsCC:: 3184 analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Args, 3185 bool IsSoftFloat, Function::const_arg_iterator FuncArg) { 3186 unsigned NumArgs = Args.size(); 3187 llvm::CCAssignFn *FixedFn = fixedArgFn(); 3188 unsigned CurArgIdx = 0; 3189 3190 for (unsigned I = 0; I != NumArgs; ++I) { 3191 MVT ArgVT = Args[I].VT; 3192 ISD::ArgFlagsTy ArgFlags = Args[I].Flags; 3193 std::advance(FuncArg, Args[I].OrigArgIndex - CurArgIdx); 3194 CurArgIdx = Args[I].OrigArgIndex; 3195 3196 if (ArgFlags.isByVal()) { 3197 handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags); 3198 continue; 3199 } 3200 3201 MVT RegVT = getRegVT(ArgVT, FuncArg->getType(), 0, IsSoftFloat); 3202 3203 if (!FixedFn(I, ArgVT, RegVT, CCValAssign::Full, ArgFlags, CCInfo)) 3204 continue; 3205 3206 #ifndef NDEBUG 3207 dbgs() << "Formal Arg #" << I << " has unhandled type " 3208 << EVT(ArgVT).getEVTString(); 3209 #endif 3210 llvm_unreachable(0); 3211 } 3212 } 3213 3214 template<typename Ty> 3215 void MipsTargetLowering::MipsCC:: 3216 analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat, 3217 const SDNode *CallNode, const Type *RetTy) const { 3218 CCAssignFn *Fn; 3219 3220 if (IsSoftFloat && originalTypeIsF128(RetTy, CallNode)) 3221 Fn = RetCC_F128Soft; 3222 else 3223 Fn = RetCC_Mips; 3224 3225 for (unsigned I = 0, E = RetVals.size(); I < E; ++I) { 3226 MVT VT = RetVals[I].VT; 3227 ISD::ArgFlagsTy Flags = RetVals[I].Flags; 3228 MVT RegVT = this->getRegVT(VT, RetTy, CallNode, IsSoftFloat); 3229 3230 if (Fn(I, VT, RegVT, CCValAssign::Full, Flags, this->CCInfo)) { 3231 #ifndef NDEBUG 3232 dbgs() << "Call result #" << I << " has unhandled type " 3233 << EVT(VT).getEVTString() << '\n'; 3234 #endif 3235 llvm_unreachable(0); 3236 } 3237 } 3238 } 3239 3240 void MipsTargetLowering::MipsCC:: 3241 analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, bool IsSoftFloat, 3242 const SDNode *CallNode, const Type *RetTy) const { 3243 analyzeReturn(Ins, IsSoftFloat, CallNode, RetTy); 3244 } 3245 3246 void MipsTargetLowering::MipsCC:: 3247 analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsSoftFloat, 3248 const Type *RetTy) const { 3249 analyzeReturn(Outs, IsSoftFloat, 0, RetTy); 3250 } 3251 3252 void 3253 MipsTargetLowering::MipsCC::handleByValArg(unsigned ValNo, MVT ValVT, 3254 MVT LocVT, 3255 CCValAssign::LocInfo LocInfo, 3256 ISD::ArgFlagsTy ArgFlags) { 3257 assert(ArgFlags.getByValSize() && "Byval argument's size shouldn't be 0."); 3258 3259 struct ByValArgInfo ByVal; 3260 unsigned RegSize = regSize(); 3261 unsigned ByValSize = RoundUpToAlignment(ArgFlags.getByValSize(), RegSize); 3262 unsigned Align = std::min(std::max(ArgFlags.getByValAlign(), RegSize), 3263 RegSize * 2); 3264 3265 if (useRegsForByval()) 3266 allocateRegs(ByVal, ByValSize, Align); 3267 3268 // Allocate space on caller's stack. 3269 ByVal.Address = CCInfo.AllocateStack(ByValSize - RegSize * ByVal.NumRegs, 3270 Align); 3271 CCInfo.addLoc(CCValAssign::getMem(ValNo, ValVT, ByVal.Address, LocVT, 3272 LocInfo)); 3273 ByValArgs.push_back(ByVal); 3274 } 3275 3276 unsigned MipsTargetLowering::MipsCC::numIntArgRegs() const { 3277 return IsO32 ? array_lengthof(O32IntRegs) : array_lengthof(Mips64IntRegs); 3278 } 3279 3280 unsigned MipsTargetLowering::MipsCC::reservedArgArea() const { 3281 return (IsO32 && (CallConv != CallingConv::Fast)) ? 16 : 0; 3282 } 3283 3284 const uint16_t *MipsTargetLowering::MipsCC::intArgRegs() const { 3285 return IsO32 ? O32IntRegs : Mips64IntRegs; 3286 } 3287 3288 llvm::CCAssignFn *MipsTargetLowering::MipsCC::fixedArgFn() const { 3289 if (CallConv == CallingConv::Fast) 3290 return CC_Mips_FastCC; 3291 3292 if (SpecialCallingConv == Mips16RetHelperConv) 3293 return CC_Mips16RetHelper; 3294 return IsO32 ? CC_MipsO32 : CC_MipsN; 3295 } 3296 3297 llvm::CCAssignFn *MipsTargetLowering::MipsCC::varArgFn() const { 3298 return IsO32 ? CC_MipsO32 : CC_MipsN_VarArg; 3299 } 3300 3301 const uint16_t *MipsTargetLowering::MipsCC::shadowRegs() const { 3302 return IsO32 ? O32IntRegs : Mips64DPRegs; 3303 } 3304 3305 void MipsTargetLowering::MipsCC::allocateRegs(ByValArgInfo &ByVal, 3306 unsigned ByValSize, 3307 unsigned Align) { 3308 unsigned RegSize = regSize(), NumIntArgRegs = numIntArgRegs(); 3309 const uint16_t *IntArgRegs = intArgRegs(), *ShadowRegs = shadowRegs(); 3310 assert(!(ByValSize % RegSize) && !(Align % RegSize) && 3311 "Byval argument's size and alignment should be a multiple of" 3312 "RegSize."); 3313 3314 ByVal.FirstIdx = CCInfo.getFirstUnallocated(IntArgRegs, NumIntArgRegs); 3315 3316 // If Align > RegSize, the first arg register must be even. 3317 if ((Align > RegSize) && (ByVal.FirstIdx % 2)) { 3318 CCInfo.AllocateReg(IntArgRegs[ByVal.FirstIdx], ShadowRegs[ByVal.FirstIdx]); 3319 ++ByVal.FirstIdx; 3320 } 3321 3322 // Mark the registers allocated. 3323 for (unsigned I = ByVal.FirstIdx; ByValSize && (I < NumIntArgRegs); 3324 ByValSize -= RegSize, ++I, ++ByVal.NumRegs) 3325 CCInfo.AllocateReg(IntArgRegs[I], ShadowRegs[I]); 3326 } 3327 3328 MVT MipsTargetLowering::MipsCC::getRegVT(MVT VT, const Type *OrigTy, 3329 const SDNode *CallNode, 3330 bool IsSoftFloat) const { 3331 if (IsSoftFloat || IsO32) 3332 return VT; 3333 3334 // Check if the original type was fp128. 3335 if (originalTypeIsF128(OrigTy, CallNode)) { 3336 assert(VT == MVT::i64); 3337 return MVT::f64; 3338 } 3339 3340 return VT; 3341 } 3342 3343 void MipsTargetLowering:: 3344 copyByValRegs(SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains, 3345 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags, 3346 SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg, 3347 const MipsCC &CC, const ByValArgInfo &ByVal) const { 3348 MachineFunction &MF = DAG.getMachineFunction(); 3349 MachineFrameInfo *MFI = MF.getFrameInfo(); 3350 unsigned RegAreaSize = ByVal.NumRegs * CC.regSize(); 3351 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize); 3352 int FrameObjOffset; 3353 3354 if (RegAreaSize) 3355 FrameObjOffset = (int)CC.reservedArgArea() - 3356 (int)((CC.numIntArgRegs() - ByVal.FirstIdx) * CC.regSize()); 3357 else 3358 FrameObjOffset = ByVal.Address; 3359 3360 // Create frame object. 3361 EVT PtrTy = getPointerTy(); 3362 int FI = MFI->CreateFixedObject(FrameObjSize, FrameObjOffset, true); 3363 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 3364 InVals.push_back(FIN); 3365 3366 if (!ByVal.NumRegs) 3367 return; 3368 3369 // Copy arg registers. 3370 MVT RegTy = MVT::getIntegerVT(CC.regSize() * 8); 3371 const TargetRegisterClass *RC = getRegClassFor(RegTy); 3372 3373 for (unsigned I = 0; I < ByVal.NumRegs; ++I) { 3374 unsigned ArgReg = CC.intArgRegs()[ByVal.FirstIdx + I]; 3375 unsigned VReg = addLiveIn(MF, ArgReg, RC); 3376 unsigned Offset = I * CC.regSize(); 3377 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN, 3378 DAG.getConstant(Offset, PtrTy)); 3379 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy), 3380 StorePtr, MachinePointerInfo(FuncArg, Offset), 3381 false, false, 0); 3382 OutChains.push_back(Store); 3383 } 3384 } 3385 3386 // Copy byVal arg to registers and stack. 3387 void MipsTargetLowering:: 3388 passByValArg(SDValue Chain, SDLoc DL, 3389 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 3390 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr, 3391 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, 3392 const MipsCC &CC, const ByValArgInfo &ByVal, 3393 const ISD::ArgFlagsTy &Flags, bool isLittle) const { 3394 unsigned ByValSize = Flags.getByValSize(); 3395 unsigned Offset = 0; // Offset in # of bytes from the beginning of struct. 3396 unsigned RegSize = CC.regSize(); 3397 unsigned Alignment = std::min(Flags.getByValAlign(), RegSize); 3398 EVT PtrTy = getPointerTy(), RegTy = MVT::getIntegerVT(RegSize * 8); 3399 3400 if (ByVal.NumRegs) { 3401 const uint16_t *ArgRegs = CC.intArgRegs(); 3402 bool LeftoverBytes = (ByVal.NumRegs * RegSize > ByValSize); 3403 unsigned I = 0; 3404 3405 // Copy words to registers. 3406 for (; I < ByVal.NumRegs - LeftoverBytes; ++I, Offset += RegSize) { 3407 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3408 DAG.getConstant(Offset, PtrTy)); 3409 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr, 3410 MachinePointerInfo(), false, false, false, 3411 Alignment); 3412 MemOpChains.push_back(LoadVal.getValue(1)); 3413 unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I]; 3414 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal)); 3415 } 3416 3417 // Return if the struct has been fully copied. 3418 if (ByValSize == Offset) 3419 return; 3420 3421 // Copy the remainder of the byval argument with sub-word loads and shifts. 3422 if (LeftoverBytes) { 3423 assert((ByValSize > Offset) && (ByValSize < Offset + RegSize) && 3424 "Size of the remainder should be smaller than RegSize."); 3425 SDValue Val; 3426 3427 for (unsigned LoadSize = RegSize / 2, TotalSizeLoaded = 0; 3428 Offset < ByValSize; LoadSize /= 2) { 3429 unsigned RemSize = ByValSize - Offset; 3430 3431 if (RemSize < LoadSize) 3432 continue; 3433 3434 // Load subword. 3435 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3436 DAG.getConstant(Offset, PtrTy)); 3437 SDValue LoadVal = 3438 DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, 3439 MachinePointerInfo(), MVT::getIntegerVT(LoadSize * 8), 3440 false, false, Alignment); 3441 MemOpChains.push_back(LoadVal.getValue(1)); 3442 3443 // Shift the loaded value. 3444 unsigned Shamt; 3445 3446 if (isLittle) 3447 Shamt = TotalSizeLoaded; 3448 else 3449 Shamt = (RegSize - (TotalSizeLoaded + LoadSize)) * 8; 3450 3451 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal, 3452 DAG.getConstant(Shamt, MVT::i32)); 3453 3454 if (Val.getNode()) 3455 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift); 3456 else 3457 Val = Shift; 3458 3459 Offset += LoadSize; 3460 TotalSizeLoaded += LoadSize; 3461 Alignment = std::min(Alignment, LoadSize); 3462 } 3463 3464 unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I]; 3465 RegsToPass.push_back(std::make_pair(ArgReg, Val)); 3466 return; 3467 } 3468 } 3469 3470 // Copy remainder of byval arg to it with memcpy. 3471 unsigned MemCpySize = ByValSize - Offset; 3472 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, 3473 DAG.getConstant(Offset, PtrTy)); 3474 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr, 3475 DAG.getIntPtrConstant(ByVal.Address)); 3476 Chain = DAG.getMemcpy(Chain, DL, Dst, Src, 3477 DAG.getConstant(MemCpySize, PtrTy), Alignment, 3478 /*isVolatile=*/false, /*AlwaysInline=*/false, 3479 MachinePointerInfo(0), MachinePointerInfo(0)); 3480 MemOpChains.push_back(Chain); 3481 } 3482 3483 void 3484 MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains, 3485 const MipsCC &CC, SDValue Chain, 3486 SDLoc DL, SelectionDAG &DAG) const { 3487 unsigned NumRegs = CC.numIntArgRegs(); 3488 const uint16_t *ArgRegs = CC.intArgRegs(); 3489 const CCState &CCInfo = CC.getCCInfo(); 3490 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumRegs); 3491 unsigned RegSize = CC.regSize(); 3492 MVT RegTy = MVT::getIntegerVT(RegSize * 8); 3493 const TargetRegisterClass *RC = getRegClassFor(RegTy); 3494 MachineFunction &MF = DAG.getMachineFunction(); 3495 MachineFrameInfo *MFI = MF.getFrameInfo(); 3496 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 3497 3498 // Offset of the first variable argument from stack pointer. 3499 int VaArgOffset; 3500 3501 if (NumRegs == Idx) 3502 VaArgOffset = RoundUpToAlignment(CCInfo.getNextStackOffset(), RegSize); 3503 else 3504 VaArgOffset = 3505 (int)CC.reservedArgArea() - (int)(RegSize * (NumRegs - Idx)); 3506 3507 // Record the frame index of the first variable argument 3508 // which is a value necessary to VASTART. 3509 int FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true); 3510 MipsFI->setVarArgsFrameIndex(FI); 3511 3512 // Copy the integer registers that have not been used for argument passing 3513 // to the argument register save area. For O32, the save area is allocated 3514 // in the caller's stack frame, while for N32/64, it is allocated in the 3515 // callee's stack frame. 3516 for (unsigned I = Idx; I < NumRegs; ++I, VaArgOffset += RegSize) { 3517 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC); 3518 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy); 3519 FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true); 3520 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy()); 3521 SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff, 3522 MachinePointerInfo(), false, false, 0); 3523 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue(0); 3524 OutChains.push_back(Store); 3525 } 3526 } 3527
