| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.h | 185 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
214 SDValue getAddrLocal(SDValue Op, SelectionDAG &DAG, bool HasMips64) const;
216 SDValue getAddrGlobal(SDValue Op, SelectionDAG &DAG, unsigned Flag) const;
218 SDValue getAddrGlobalLargeGOT(SDValue Op, SelectionDAG &DAG,
344 SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
345 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
346 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
347 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
348 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
349 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
[all...] |
| /external/clang/lib/StaticAnalyzer/Checkers/ |
| DivZeroChecker.cpp | 50 BinaryOperator::Opcode Op = B->getOpcode();
51 if (Op != BO_Div &&
52 Op != BO_Rem &&
53 Op != BO_DivAssign &&
54 Op != BO_RemAssign)
|
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.h | 44 // Add pseudo op to model memcpy for struct byval.
257 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
332 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
337 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
361 virtual void LowerAsmOperandForConstraint(SDValue Op,
435 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
436 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
437 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
439 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
440 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| Reassociate.cpp | 53 Value *Op;
54 ValueEntry(unsigned R, Value *O) : Rank(R), Op(O) {}
67 << *Ops[0].Op->getType() << '\t';
70 WriteAsOperand(dbgs(), Ops[i].Op, false, M);
324 Neg->setOperand(1, Constant::getNullValue(Neg->getType())); // Drop use of op.
344 /// The existing weight LHS represents the computation X op X op ... op X where
345 /// X occurs LHS times. The combined weight represents X op X op ... op X wit
[all...] |
| /external/chromium_org/third_party/skia/include/core/ |
| SkClipStack.h | 53 Element(const SkRect& rect, SkRegion::Op op, bool doAA) {
54 this->initRect(0, rect, op, doAA);
57 Element(const SkPath& path, SkRegion::Op op, bool doAA) {
58 this->initPath(0, path, op, doAA);
95 SkRegion::Op getOp() const { return fOp; }
105 void setOp(SkRegion::Op op) { fOp = op; }
[all...] |
| /external/llvm/lib/Target/R600/InstPrinter/ |
| AMDGPUInstPrinter.cpp | 29 const MCOperand &Op = MI->getOperand(OpNo);
30 if (Op.isReg()) {
31 switch (Op.getReg()) {
34 default: O << getRegisterName(Op.getReg()); break;
36 } else if (Op.isImm()) {
37 O << Op.getImm();
38 } else if (Op.isFPImm()) {
39 O << Op.getFPImm();
40 } else if (Op.isExpr()) {
41 const MCExpr *Exp = Op.getExpr()
[all...] |
| /external/skia/include/core/ |
| SkClipStack.h | 53 Element(const SkRect& rect, SkRegion::Op op, bool doAA) {
54 this->initRect(0, rect, op, doAA);
57 Element(const SkPath& path, SkRegion::Op op, bool doAA) {
58 this->initPath(0, path, op, doAA);
95 SkRegion::Op getOp() const { return fOp; }
105 void setOp(SkRegion::Op op) { fOp = op; }
[all...] |
| /cts/tests/tests/graphics/src/android/graphics/cts/ |
| RegionTest.java | 343 assertFalse(mRegion.op(rect1, Region.Op.DIFFERENCE));
344 assertFalse(mRegion.op(rect1, Region.Op.INTERSECT));
345 assertFalse(mRegion.op(rect1, Region.Op.UNION));
346 assertFalse(mRegion.op(rect1, Region.Op.XOR));
347 assertFalse(mRegion.op(rect1, Region.Op.REVERSE_DIFFERENCE))
[all...] |
| /external/llvm/lib/Target/R600/ |
| AMDILISelLowering.cpp | 247 // isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
248 // be zero. Op is expected to be a target specific node. Used by DAG
253 const SDValue Op,
261 switch (Op.getOpcode()) {
265 Op.getOperand(1),
271 Op.getOperand(0),
291 AMDGPUTargetLowering::LowerSDIV(SDValue Op, SelectionDAG &DAG) const {
292 EVT OVT = Op.getValueType();
295 DST = LowerSDIV64(Op, DAG);
297 DST = LowerSDIV32(Op, DAG)
[all...] |
| /external/clang/lib/CodeGen/ |
| CGExprComplex.cpp | 144 ComplexPairTy EmitCast(CastExpr::CastKind CK, Expr *Op, QualType DestTy);
227 ComplexPairTy EmitBinAdd(const BinOpInfo &Op);
228 ComplexPairTy EmitBinSub(const BinOpInfo &Op);
229 ComplexPairTy EmitBinMul(const BinOpInfo &Op);
230 ComplexPairTy EmitBinDiv(const BinOpInfo &Op);
410 ComplexPairTy ComplexExprEmitter::EmitCast(CastExpr::CastKind CK, Expr *Op,
415 // Atomic to non-atomic casts may be more than a no-op for some platforms and
422 return Visit(Op);
425 LValue origLV = CGF.EmitLValue(Op);
478 return EmitScalarToComplexCast(CGF.EmitScalarExpr(Op),
[all...] |
| /external/llvm/include/llvm/Transforms/Utils/ |
| Local.h | 204 Value *Op = *i;
206 if (ConstantInt *OpC = dyn_cast<ConstantInt>(Op)) {
227 if (Op->getType() != IntPtrTy)
228 Op = Builder->CreateIntCast(Op, IntPtrTy, true, Op->getName()+".c");
231 Op = Builder->CreateMul(Op, ConstantInt::get(IntPtrTy, Size),
236 Result = Builder->CreateAdd(Op, Result, GEP->getName()+".offs");
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.h | 82 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
84 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
134 virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
153 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
155 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
156 SDValue LowerLOADi1(SDValue Op, SelectionDAG &DAG) const;
158 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
159 SDValue LowerSTOREi1(SDValue Op, SelectionDAG &DAG) const;
160 SDValue LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const;
|
| /external/llvm/utils/TableGen/ |
| CodeGenInstruction.h | 45 static ConstraintInfo getTied(unsigned Op) {
48 I.OtherTiedOperand = Op;
167 std::pair<unsigned,unsigned> ParseOperandName(const std::string &Op,
172 unsigned getFlattenedOperandNumber(std::pair<unsigned,unsigned> Op) const {
173 return OperandList[Op.first].MIOperandNo + Op.second;
178 std::pair<unsigned,unsigned> getSubOperandNumber(unsigned Op) const {
181 if (OperandList[i].MIOperandNo+OperandList[i].MINumOperands > Op)
182 return std::make_pair(i, Op-OperandList[i].MIOperandNo);
190 std::pair<unsigned,unsigned> Op = getSubOperandNumber(FlatOpNo)
[all...] |
| /external/llvm/utils/PerfectShuffle/ |
| PerfectShuffle.cpp | 89 Operator *Op; // The Operation used to generate this value.
147 static const char *getZeroCostOpName(unsigned short Op) {
148 if (ShufTab[Op].Arg0 == 0x0123)
150 else if (ShufTab[Op].Arg0 == 0x4567)
162 std::cerr << " = " << ShufTab[ThisOp].Op->getName() << "(";
176 if (!ShufTab[Vals[ValNo]].Op->isOnlyLHSOperator()) {
222 ShufTab[0x0123].Op = 0;
225 ShufTab[0x4567].Op = 0;
304 Operator *Op = TheOperators[opnum];
306 // Evaluate op(LHS,LHS
[all...] |
| /external/llvm/include/llvm/Bitcode/ |
| BitstreamWriter.h | 276 /// record. This is a no-op, since the abbrev specifies the literal to use.
278 void EmitAbbreviatedLiteral(const BitCodeAbbrevOp &Op, uintty V) {
279 assert(Op.isLiteral() && "Not a literal");
282 assert(V == Op.getLiteralValue() &&
289 void EmitAbbreviatedField(const BitCodeAbbrevOp &Op, uintty V) {
290 assert(!Op.isLiteral() && "Literals should use EmitAbbreviatedLiteral!");
293 switch (Op.getEncoding()) {
296 if (Op.getEncodingData())
297 Emit((unsigned)V, (unsigned)Op.getEncodingData());
300 if (Op.getEncodingData()
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| SIISelLowering.cpp | 261 SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
263 switch (Op.getOpcode()) {
264 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
265 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
266 case ISD::LOAD: return LowerLOAD(Op, DAG);
267 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
268 case ISD::AND: return Loweri1ContextSwitch(Op, DAG, ISD::AND);
271 cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
272 EVT VT = Op.getValueType();
277 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG)
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIISelLowering.cpp | 261 SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
263 switch (Op.getOpcode()) {
264 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
265 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
266 case ISD::LOAD: return LowerLOAD(Op, DAG);
267 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
268 case ISD::AND: return Loweri1ContextSwitch(Op, DAG, ISD::AND);
271 cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
272 EVT VT = Op.getValueType();
277 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG)
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.h | 52 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
57 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
121 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
122 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
123 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
126 SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const;
127 SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF,
129 SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const;
|
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.h | 112 inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) {
113 if (MI->getOperand(Op).isFI()) return true;
114 return Op+4 <= MI->getNumOperands() &&
115 MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) &&
116 MI->getOperand(Op+2).isReg() &&
117 (MI->getOperand(Op+3).isImm() ||
118 MI->getOperand(Op+3).isGlobal() ||
119 MI->getOperand(Op+3).isCPI() ||
120 MI->getOperand(Op+3).isJTI())
[all...] |
| X86AsmPrinter.h | 60 void printMemReference(const MachineInstr *MI, unsigned Op, raw_ostream &O,
62 void printLeaMemReference(const MachineInstr *MI, unsigned Op, raw_ostream &O,
65 void printIntelMemReference(const MachineInstr *MI, unsigned Op,
|
| /external/openfst/src/include/fst/script/ |
| script-impl.h | 127 OperationSignature op) {
128 this->SetEntry(make_pair(operation_name, arc_type), op); local
171 #define REGISTER_FST_OPERATION(Op, Arc, ArgPack) \
173 arc_dispatched_operation_ ## ArgPack ## Op ## Arc ## _registerer( \
174 make_pair(#Op, Arc::Type()), Op<Arc>)
186 typename OpReg::OpType op = reg->GetOperation(op_name, arc_type); local
188 if (op == 0) {
194 op(args);
|
| /external/llvm/lib/Transforms/ObjCARC/ |
| DependencyAnalysis.cpp | 58 const Value *Op = *I;
59 if (IsPotentialRetainableObjPtr(Op, *PA.getAA()) && PA.related(Ptr, Op))
90 const Value *Op = *OI;
91 if (IsPotentialRetainableObjPtr(Op, *PA.getAA()) && PA.related(Ptr, Op))
98 const Value *Op = GetUnderlyingObjCPtr(SI->getPointerOperand());
101 return IsPotentialRetainableObjPtr(Op, *PA.getAA()) && PA.related(Op, Ptr);
107 const Value *Op = *OI
[all...] |
| /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.4.3/i686-linux/include/c++/4.4.3/parallel/ |
| omp_loop.h | 51 * @param f Functor to "process" an element with op (depends on
62 typename Op,
66 Op
69 Op o, Fu& f, Red r, Result base,
|
| omp_loop_static.h | 51 * @param f Functor to "process" an element with op (depends on
62 typename Op,
66 Op
69 Op o, Fu& f, Red r,
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| TargetLowering.cpp | 265 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
267 SDLoc dl(Op);
270 switch (Op.getOpcode()) {
275 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
278 if (Op.getOpcode() == ISD::XOR &&
284 EVT VT = Op.getValueType();
285 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
289 return CombineTo(Op, New);
304 TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
[all...] |
