| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 34 tm.getRelocationModel() == Reloc::PIC_ ? Mips::B : Mips::J),
52 if ((Opc == Mips::LW) || (Opc == Mips::LW_P8) || (Opc == Mips::LD) ||
53 (Opc == Mips::LD_P8) || (Opc == Mips::LWC1) || (Opc == Mips::LWC1_P8) ||
54 (Opc == Mips::LDC1) || (Opc == Mips::LDC164) |
[all...] |
| Mips16InstrInfo.cpp | 39 : MipsInstrInfo(tm, Mips::BimmX16),
74 if (Mips::CPU16RegsRegClass.contains(DestReg) &&
75 Mips::GPR32RegClass.contains(SrcReg))
76 Opc = Mips::MoveR3216;
77 else if (Mips::GPR32RegClass.contains(DestReg) &&
78 Mips::CPU16RegsRegClass.contains(SrcReg))
79 Opc = Mips::Move32R16;
80 else if ((SrcReg == Mips::HI) &&
81 (Mips::CPU16RegsRegClass.contains(DestReg)))
82 Opc = Mips::Mfhi16, SrcReg = 0
[all...] |
| MipsRelocations.h | 1 //===-- MipsRelocations.h - Mips Code Relocations ---------------*- C++ -*-===//
10 // This file defines the Mips target-specific relocation types
21 namespace Mips{
|
| MipsRegisterInfo.cpp | 1 //===-- MipsRegisterInfo.cpp - MIPS Register Information -== --------------===//
10 // This file contains the MIPS implementation of the TargetRegisterInfo class.
14 #define DEBUG_TYPE "mips-reg-info"
17 #include "Mips.h"
46 : MipsGenRegisterInfo(Mips::RA), Subtarget(ST) {}
48 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
57 case Mips::GPR32RegClassID:
58 case Mips::GPR64RegClassID:
59 case Mips::DSPRegsRegClassID: {
63 case Mips::FGR32RegClassID
[all...] |
| MipsLongBranch.cpp | 19 #define DEBUG_TYPE "mips-long-branch"
21 #include "Mips.h"
39 "skip-mips-long-branch",
41 cl::desc("MIPS: Skip long branch pass."),
45 "force-mips-long-branch",
47 cl::desc("MIPS: Expand all branches to long format."),
73 return "Mips Long Branch";
288 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
289 .addReg(Mips::SP).addImm(-8)
[all...] |
| Mips16ISelLowering.cpp | 13 #define DEBUG_TYPE "mips-lower"
28 "pseudos for Mips 16"),
122 addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
123 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
128 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
166 case Mips::SelBeqZ:
167 return emitSel16(Mips::BeqzRxImm16, MI, BB);
168 case Mips::SelBneZ:
169 return emitSel16(Mips::BnezRxImm16, MI, BB);
170 case Mips::SelTBteqZCmpi
[all...] |
| MipsMachineFunction.cpp | 1 //===-- MipsMachineFunctionInfo.cpp - Private data used for Mips ----------===//
22 FixGlobalBaseReg("mips-fix-global-base-reg", cl::Hidden, cl::init(true),
38 RC=(const TargetRegisterClass*)&Mips::CPU16RegsRegClass;
41 (const TargetRegisterClass*)&Mips::GPR64RegClass :
42 (const TargetRegisterClass*)&Mips::GPR32RegClass;
55 RC=(const TargetRegisterClass*)&Mips::CPU16RegsRegClass;
63 &Mips::GPR64RegClass : &Mips::GPR32RegClass;
|
| MipsSEISelDAGToDAG.cpp | 14 #define DEBUG_TYPE "mips-isel"
16 #include "Mips.h"
51 MIB.addReg(Mips::DSPPos, Flag);
54 MIB.addReg(Mips::DSPSCount, Flag);
57 MIB.addReg(Mips::DSPCarry, Flag);
60 MIB.addReg(Mips::DSPOutFlag, Flag);
63 MIB.addReg(Mips::DSPCCond, Flag);
66 MIB.addReg(Mips::DSPEFI, Flag);
74 if ((MI.getOpcode() == Mips::ADDiu) &&
75 (MI.getOperand(1).getReg() == Mips::ZERO) &
[all...] |
| Mips16FrameLowering.cpp | 47 TII.makeFrame(Mips::SP, StackSize, MBB, MBBI);
59 unsigned S2 = MRI->getDwarfRegNum(Mips::S2, true);
62 unsigned S1 = MRI->getDwarfRegNum(Mips::S1, true);
65 unsigned S0 = MRI->getDwarfRegNum(Mips::S0, true);
68 unsigned RA = MRI->getDwarfRegNum(Mips::RA, true);
72 BuildMI(MBB, MBBI, dl, TII.get(Mips::MoveR3216), Mips::S0)
73 .addReg(Mips::SP);
90 BuildMI(MBB, MBBI, dl, TII.get(Mips::Move32R16), Mips::SP
[all...] |
| MipsSEFrameLowering.cpp | 72 case Mips::LOAD_CCOND_DSP:
73 case Mips::LOAD_CCOND_DSP_P8:
76 case Mips::STORE_CCOND_DSP:
77 case Mips::STORE_CCOND_DSP_P8:
80 case Mips::LOAD_AC64:
81 case Mips::LOAD_AC64_P8:
82 case Mips::LOAD_AC_DSP:
83 case Mips::LOAD_AC_DSP_P8:
86 case Mips::LOAD_AC128:
87 case Mips::LOAD_AC128_P8
[all...] |
| MipsCodeEmitter.cpp | 1 //===-- Mips/MipsCodeEmitter.cpp - Convert Mips Code to Machine Code ------===//
10 // This file contains the pass that transforms the Mips machine instructions
16 #include "Mips.h"
75 return "Mips Machine Code Emitter";
166 return Mips::reloc_mips_26;
169 return Mips::reloc_mips_pc16;
170 if (Form == MipsII::FrmI && MI.getOpcode() == Mips::LUi)
171 return Mips::reloc_mips_hi;
172 return Mips::reloc_mips_lo
[all...] |
| Mips16ISelDAGToDAG.cpp | 14 #define DEBUG_TYPE "mips-isel"
16 #include "Mips.h"
53 unsigned Opcode = Mips::Mflo16;
58 unsigned Opcode = Mips::Mfhi16;
77 (const TargetRegisterClass*)&Mips::CPU16RegsRegClass;
83 BuildMI(MBB, I, DL, TII.get(Mips::LiRxImmX16), V0)
85 BuildMI(MBB, I, DL, TII.get(Mips::AddiuRxPcImmX16), V1)
87 BuildMI(MBB, I, DL, TII.get(Mips::SllX16), V2).addReg(V0).addImm(16);
88 BuildMI(MBB, I, DL, TII.get(Mips::AdduRxRyRz16), GlobalBaseReg)
107 BuildMI(MBB, I, DL, TII.get(Mips::MoveR3216), Mips16SPAliasReg
[all...] |
| MipsISelLowering.cpp | 1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
14 #define DEBUG_TYPE "mips-lower"
44 cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false));
48 cl::desc("MIPS: Don't trap on integer division by zero."),
52 Mips::A0, Mips::A1, Mips::A2, Mips::A3
56 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64
[all...] |
| Mips16RegisterInfo.cpp | 16 #include "Mips.h"
69 TII.copyPhysReg(MBB, I, DL, Mips::T0, Reg, true);
70 TII.copyPhysReg(MBB, UseMI, DL, Reg, Mips::T0, true);
77 return &Mips::CPU16RegsRegClass;
107 FrameReg = Mips::SP;
111 FrameReg = Mips::S0;
117 FrameReg = Mips::SP;
|
| MipsSERegisterInfo.cpp | 16 #include "Mips.h"
59 return &Mips::GPR32RegClass;
62 return &Mips::GPR64RegClass;
95 FrameReg = Subtarget.isABI_N64() ? Mips::SP_64 : Mips::SP;
119 unsigned ADDu = Subtarget.isABI_N64() ? Mips::DADDu : Mips::ADDu;
|
| MipsAnalyzeImmediate.cpp | 10 #include "Mips.h"
130 ADDiu = Mips::ADDiu;
131 ORi = Mips::ORi;
132 SLL = Mips::SLL;
133 LUi = Mips::LUi;
135 ADDiu = Mips::DADDiu;
136 ORi = Mips::ORi64;
137 SLL = Mips::DSLL;
138 LUi = Mips::LUi64;
|
| Makefile | 1 ##===- lib/Target/Mips/Makefile ----------------------------*- Makefile -*-===##
12 TARGET = Mips
|
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsAsmBackend.cpp | 1 //===-- MipsASMBackend.cpp - Mips Asm Backend ----------------------------===//
39 case Mips::fixup_Mips_LO16:
40 case Mips::fixup_Mips_GPREL16:
41 case Mips::fixup_Mips_GPOFF_HI:
42 case Mips::fixup_Mips_GPOFF_LO:
43 case Mips::fixup_Mips_GOT_PAGE:
44 case Mips::fixup_Mips_GOT_OFST:
45 case Mips::fixup_Mips_GOT_DISP:
46 case Mips::fixup_Mips_GOT_LO16:
47 case Mips::fixup_Mips_CALL_LO16
[all...] |
| MipsMCCodeEmitter.cpp | 1 //===-- MipsMCCodeEmitter.cpp - Convert Mips Code to Machine Code ---------===//
136 case Mips::DSLL:
137 Inst.setOpcode(Mips::DSLL32);
139 case Mips::DSRL:
140 Inst.setOpcode(Mips::DSRL32);
142 case Mips::DSRA:
143 Inst.setOpcode(Mips::DSRA32);
152 if (Opcode == Mips::DEXT)
169 InstIn.setOpcode((Opcode == Mips::DEXT) ? Mips::DEXTU : Mips::DINSU)
[all...] |
| MipsELFObjectWriter.cpp | 1 //===-- MipsELFObjectWriter.cpp - Mips ELF Writer -------------------------===//
105 case Mips::fixup_Mips_GPREL16:
108 case Mips::fixup_Mips_26:
111 case Mips::fixup_Mips_CALL16:
114 case Mips::fixup_Mips_GOT_Global:
115 case Mips::fixup_Mips_GOT_Local:
118 case Mips::fixup_Mips_HI16:
121 case Mips::fixup_Mips_LO16:
124 case Mips::fixup_Mips_TLSGD:
127 case Mips::fixup_Mips_GOTTPREL
[all...] |
| /external/llvm/lib/Target/Mips/InstPrinter/ |
| MipsInstPrinter.cpp | 1 //===-- MipsInstPrinter.cpp - Convert Mips MCInst to assembly syntax ------===//
10 // This class prints an Mips MCInst to a .s file.
35 const char* Mips::MipsFCCToString(Mips::CondCode CC) {
82 case Mips::RDHWR:
83 case Mips::RDHWR64:
96 case Mips::RDHWR:
97 case Mips::RDHWR64:
211 O << MipsFCCToString((Mips::CondCode)MO.getImm());
232 case Mips::BEQ
[all...] |
| /build/target/product/ |
| sdk_mips.mk | 28 PRODUCT_MODEL := Android SDK for Mips
|
| /external/llvm/host/include/llvm/Config/ |
| Targets.def | 27 LLVM_TARGET(Mips)
|
| /external/llvm/device/include/llvm/Config/ |
| Targets.def | 29 LLVM_TARGET(Mips)
|
| /external/llvm/ |
| Android.mk | 47 # MIPS Code Generation Libraries
49 lib/Target/Mips \
50 lib/Target/Mips/AsmParser \
51 lib/Target/Mips/InstPrinter \
52 lib/Target/Mips/Disassembler \
53 lib/Target/Mips/MCTargetDesc \
54 lib/Target/Mips/TargetInfo
|
