1 //===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the Base ARM implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef ARMBASEINSTRUCTIONINFO_H 15 #define ARMBASEINSTRUCTIONINFO_H 16 17 #include "MCTargetDesc/ARMBaseInfo.h" 18 #include "llvm/ADT/DenseMap.h" 19 #include "llvm/ADT/SmallSet.h" 20 #include "llvm/CodeGen/MachineInstrBuilder.h" 21 #include "llvm/Target/TargetInstrInfo.h" 22 23 #define GET_INSTRINFO_HEADER 24 #include "ARMGenInstrInfo.inc" 25 26 namespace llvm { 27 class ARMSubtarget; 28 class ARMBaseRegisterInfo; 29 30 class ARMBaseInstrInfo : public ARMGenInstrInfo { 31 const ARMSubtarget &Subtarget; 32 33 protected: 34 // Can be only subclassed. 35 explicit ARMBaseInstrInfo(const ARMSubtarget &STI); 36 37 public: 38 // Return whether the target has an explicit NOP encoding. 39 bool hasNOP() const; 40 41 // Return the non-pre/post incrementing version of 'Opc'. Return 0 42 // if there is not such an opcode. 43 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0; 44 45 MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, 46 MachineBasicBlock::iterator &MBBI, 47 LiveVariables *LV) const override; 48 49 virtual const ARMBaseRegisterInfo &getRegisterInfo() const = 0; 50 const ARMSubtarget &getSubtarget() const { return Subtarget; } 51 52 ScheduleHazardRecognizer * 53 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, 54 const ScheduleDAG *DAG) const override; 55 56 ScheduleHazardRecognizer * 57 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, 58 const ScheduleDAG *DAG) const override; 59 60 // Branch analysis. 61 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 62 MachineBasicBlock *&FBB, 63 SmallVectorImpl<MachineOperand> &Cond, 64 bool AllowModify = false) const override; 65 unsigned RemoveBranch(MachineBasicBlock &MBB) const override; 66 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 67 MachineBasicBlock *FBB, 68 const SmallVectorImpl<MachineOperand> &Cond, 69 DebugLoc DL) const override; 70 71 bool 72 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 73 74 // Predication support. 75 bool isPredicated(const MachineInstr *MI) const override; 76 77 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const { 78 int PIdx = MI->findFirstPredOperandIdx(); 79 return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm() 80 : ARMCC::AL; 81 } 82 83 bool PredicateInstruction(MachineInstr *MI, 84 const SmallVectorImpl<MachineOperand> &Pred) const override; 85 86 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 87 const SmallVectorImpl<MachineOperand> &Pred2) const override; 88 89 bool DefinesPredicate(MachineInstr *MI, 90 std::vector<MachineOperand> &Pred) const override; 91 92 bool isPredicable(MachineInstr *MI) const override; 93 94 /// GetInstSize - Returns the size of the specified MachineInstr. 95 /// 96 virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const; 97 98 unsigned isLoadFromStackSlot(const MachineInstr *MI, 99 int &FrameIndex) const override; 100 unsigned isStoreToStackSlot(const MachineInstr *MI, 101 int &FrameIndex) const override; 102 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 103 int &FrameIndex) const override; 104 unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, 105 int &FrameIndex) const override; 106 107 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 108 DebugLoc DL, unsigned DestReg, unsigned SrcReg, 109 bool KillSrc) const override; 110 111 void storeRegToStackSlot(MachineBasicBlock &MBB, 112 MachineBasicBlock::iterator MBBI, 113 unsigned SrcReg, bool isKill, int FrameIndex, 114 const TargetRegisterClass *RC, 115 const TargetRegisterInfo *TRI) const override; 116 117 void loadRegFromStackSlot(MachineBasicBlock &MBB, 118 MachineBasicBlock::iterator MBBI, 119 unsigned DestReg, int FrameIndex, 120 const TargetRegisterClass *RC, 121 const TargetRegisterInfo *TRI) const override; 122 123 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override; 124 125 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 126 unsigned DestReg, unsigned SubIdx, 127 const MachineInstr *Orig, 128 const TargetRegisterInfo &TRI) const override; 129 130 MachineInstr *duplicate(MachineInstr *Orig, 131 MachineFunction &MF) const override; 132 133 MachineInstr *commuteInstruction(MachineInstr*, 134 bool=false) const override; 135 136 const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg, 137 unsigned SubIdx, unsigned State, 138 const TargetRegisterInfo *TRI) const; 139 140 bool produceSameValue(const MachineInstr *MI0, const MachineInstr *MI1, 141 const MachineRegisterInfo *MRI) const override; 142 143 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to 144 /// determine if two loads are loading from the same base address. It should 145 /// only return true if the base pointers are the same and the only 146 /// differences between the two addresses is the offset. It also returns the 147 /// offsets by reference. 148 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, 149 int64_t &Offset2) const override; 150 151 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 152 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads 153 /// should be scheduled togther. On some targets if two loads are loading from 154 /// addresses in the same cache line, it's better if they are scheduled 155 /// together. This function takes two integers that represent the load offsets 156 /// from the common base address. It returns true if it decides it's desirable 157 /// to schedule the two loads together. "NumLoads" is the number of loads that 158 /// have already been scheduled after Load1. 159 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 160 int64_t Offset1, int64_t Offset2, 161 unsigned NumLoads) const override; 162 163 bool isSchedulingBoundary(const MachineInstr *MI, 164 const MachineBasicBlock *MBB, 165 const MachineFunction &MF) const override; 166 167 bool isProfitableToIfCvt(MachineBasicBlock &MBB, 168 unsigned NumCycles, unsigned ExtraPredCycles, 169 const BranchProbability &Probability) const override; 170 171 bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT, 172 unsigned ExtraT, MachineBasicBlock &FMBB, 173 unsigned NumF, unsigned ExtraF, 174 const BranchProbability &Probability) const override; 175 176 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 177 const BranchProbability &Probability) const override { 178 return NumCycles == 1; 179 } 180 181 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, 182 MachineBasicBlock &FMBB) const override; 183 184 /// analyzeCompare - For a comparison instruction, return the source registers 185 /// in SrcReg and SrcReg2 if having two register operands, and the value it 186 /// compares against in CmpValue. Return true if the comparison instruction 187 /// can be analyzed. 188 bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, 189 unsigned &SrcReg2, int &CmpMask, 190 int &CmpValue) const override; 191 192 /// optimizeCompareInstr - Convert the instruction to set the zero flag so 193 /// that we can remove a "comparison with zero"; Remove a redundant CMP 194 /// instruction if the flags can be updated in the same way by an earlier 195 /// instruction such as SUB. 196 bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, 197 unsigned SrcReg2, int CmpMask, int CmpValue, 198 const MachineRegisterInfo *MRI) const override; 199 200 bool analyzeSelect(const MachineInstr *MI, 201 SmallVectorImpl<MachineOperand> &Cond, 202 unsigned &TrueOp, unsigned &FalseOp, 203 bool &Optimizable) const override; 204 205 MachineInstr *optimizeSelect(MachineInstr *MI, bool) const override; 206 207 /// FoldImmediate - 'Reg' is known to be defined by a move immediate 208 /// instruction, try to fold the immediate into the use instruction. 209 bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, 210 unsigned Reg, MachineRegisterInfo *MRI) const override; 211 212 unsigned getNumMicroOps(const InstrItineraryData *ItinData, 213 const MachineInstr *MI) const override; 214 215 int getOperandLatency(const InstrItineraryData *ItinData, 216 const MachineInstr *DefMI, unsigned DefIdx, 217 const MachineInstr *UseMI, 218 unsigned UseIdx) const override; 219 int getOperandLatency(const InstrItineraryData *ItinData, 220 SDNode *DefNode, unsigned DefIdx, 221 SDNode *UseNode, unsigned UseIdx) const override; 222 223 /// VFP/NEON execution domains. 224 std::pair<uint16_t, uint16_t> 225 getExecutionDomain(const MachineInstr *MI) const override; 226 void setExecutionDomain(MachineInstr *MI, unsigned Domain) const override; 227 228 unsigned getPartialRegUpdateClearance(const MachineInstr*, unsigned, 229 const TargetRegisterInfo*) const override; 230 void breakPartialRegDependency(MachineBasicBlock::iterator, unsigned, 231 const TargetRegisterInfo *TRI) const override; 232 233 void 234 getUnconditionalBranch(MCInst &Branch, 235 const MCSymbolRefExpr *BranchTarget) const override; 236 237 void getTrap(MCInst &MI) const override; 238 239 /// Get the number of addresses by LDM or VLDM or zero for unknown. 240 unsigned getNumLDMAddresses(const MachineInstr *MI) const; 241 242 private: 243 unsigned getInstBundleLength(const MachineInstr *MI) const; 244 245 int getVLDMDefCycle(const InstrItineraryData *ItinData, 246 const MCInstrDesc &DefMCID, 247 unsigned DefClass, 248 unsigned DefIdx, unsigned DefAlign) const; 249 int getLDMDefCycle(const InstrItineraryData *ItinData, 250 const MCInstrDesc &DefMCID, 251 unsigned DefClass, 252 unsigned DefIdx, unsigned DefAlign) const; 253 int getVSTMUseCycle(const InstrItineraryData *ItinData, 254 const MCInstrDesc &UseMCID, 255 unsigned UseClass, 256 unsigned UseIdx, unsigned UseAlign) const; 257 int getSTMUseCycle(const InstrItineraryData *ItinData, 258 const MCInstrDesc &UseMCID, 259 unsigned UseClass, 260 unsigned UseIdx, unsigned UseAlign) const; 261 int getOperandLatency(const InstrItineraryData *ItinData, 262 const MCInstrDesc &DefMCID, 263 unsigned DefIdx, unsigned DefAlign, 264 const MCInstrDesc &UseMCID, 265 unsigned UseIdx, unsigned UseAlign) const; 266 267 unsigned getPredicationCost(const MachineInstr *MI) const override; 268 269 unsigned getInstrLatency(const InstrItineraryData *ItinData, 270 const MachineInstr *MI, 271 unsigned *PredCost = nullptr) const override; 272 273 int getInstrLatency(const InstrItineraryData *ItinData, 274 SDNode *Node) const override; 275 276 bool hasHighOperandLatency(const InstrItineraryData *ItinData, 277 const MachineRegisterInfo *MRI, 278 const MachineInstr *DefMI, unsigned DefIdx, 279 const MachineInstr *UseMI, 280 unsigned UseIdx) const override; 281 bool hasLowDefLatency(const InstrItineraryData *ItinData, 282 const MachineInstr *DefMI, 283 unsigned DefIdx) const override; 284 285 /// verifyInstruction - Perform target specific instruction verification. 286 bool verifyInstruction(const MachineInstr *MI, 287 StringRef &ErrInfo) const override; 288 289 private: 290 /// Modeling special VFP / NEON fp MLA / MLS hazards. 291 292 /// MLxEntryMap - Map fp MLA / MLS to the corresponding entry in the internal 293 /// MLx table. 294 DenseMap<unsigned, unsigned> MLxEntryMap; 295 296 /// MLxHazardOpcodes - Set of add / sub and multiply opcodes that would cause 297 /// stalls when scheduled together with fp MLA / MLS opcodes. 298 SmallSet<unsigned, 16> MLxHazardOpcodes; 299 300 public: 301 /// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS 302 /// instruction. 303 bool isFpMLxInstruction(unsigned Opcode) const { 304 return MLxEntryMap.count(Opcode); 305 } 306 307 /// isFpMLxInstruction - This version also returns the multiply opcode and the 308 /// addition / subtraction opcode to expand to. Return true for 'HasLane' for 309 /// the MLX instructions with an extra lane operand. 310 bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc, 311 unsigned &AddSubOpc, bool &NegAcc, 312 bool &HasLane) const; 313 314 /// canCauseFpMLxStall - Return true if an instruction of the specified opcode 315 /// will cause stalls when scheduled after (within 4-cycle window) a fp 316 /// MLA / MLS instruction. 317 bool canCauseFpMLxStall(unsigned Opcode) const { 318 return MLxHazardOpcodes.count(Opcode); 319 } 320 321 /// Returns true if the instruction has a shift by immediate that can be 322 /// executed in one cycle less. 323 bool isSwiftFastImmShift(const MachineInstr *MI) const; 324 }; 325 326 static inline 327 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) { 328 return MIB.addImm((int64_t)ARMCC::AL).addReg(0); 329 } 330 331 static inline 332 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) { 333 return MIB.addReg(0); 334 } 335 336 static inline 337 const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB, 338 bool isDead = false) { 339 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead)); 340 } 341 342 static inline 343 const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) { 344 return MIB.addReg(0); 345 } 346 347 static inline 348 bool isUncondBranchOpcode(int Opc) { 349 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B; 350 } 351 352 static inline 353 bool isCondBranchOpcode(int Opc) { 354 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc; 355 } 356 357 static inline 358 bool isJumpTableBranchOpcode(int Opc) { 359 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd || 360 Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT; 361 } 362 363 static inline 364 bool isIndirectBranchOpcode(int Opc) { 365 return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND; 366 } 367 368 static inline bool isPopOpcode(int Opc) { 369 return Opc == ARM::tPOP_RET || Opc == ARM::LDMIA_RET || 370 Opc == ARM::t2LDMIA_RET || Opc == ARM::tPOP || Opc == ARM::LDMIA_UPD || 371 Opc == ARM::t2LDMIA_UPD || Opc == ARM::VLDMDIA_UPD; 372 } 373 374 static inline bool isPushOpcode(int Opc) { 375 return Opc == ARM::tPUSH || Opc == ARM::t2STMDB_UPD || 376 Opc == ARM::STMDB_UPD || Opc == ARM::VSTMDDB_UPD; 377 } 378 379 /// getInstrPredicate - If instruction is predicated, returns its predicate 380 /// condition, otherwise returns AL. It also returns the condition code 381 /// register by reference. 382 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg); 383 384 int getMatchingCondBranchOpcode(int Opc); 385 386 /// Determine if MI can be folded into an ARM MOVCC instruction, and return the 387 /// opcode of the SSA instruction representing the conditional MI. 388 unsigned canFoldARMInstrIntoMOVCC(unsigned Reg, 389 MachineInstr *&MI, 390 const MachineRegisterInfo &MRI); 391 392 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether 393 /// the instruction is encoded with an 'S' bit is determined by the optional 394 /// CPSR def operand. 395 unsigned convertAddSubFlagsOpcode(unsigned OldOpc); 396 397 /// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of 398 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2 399 /// code. 400 void emitARMRegPlusImmediate(MachineBasicBlock &MBB, 401 MachineBasicBlock::iterator &MBBI, DebugLoc dl, 402 unsigned DestReg, unsigned BaseReg, int NumBytes, 403 ARMCC::CondCodes Pred, unsigned PredReg, 404 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0); 405 406 void emitT2RegPlusImmediate(MachineBasicBlock &MBB, 407 MachineBasicBlock::iterator &MBBI, DebugLoc dl, 408 unsigned DestReg, unsigned BaseReg, int NumBytes, 409 ARMCC::CondCodes Pred, unsigned PredReg, 410 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0); 411 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB, 412 MachineBasicBlock::iterator &MBBI, DebugLoc dl, 413 unsigned DestReg, unsigned BaseReg, 414 int NumBytes, const TargetInstrInfo &TII, 415 const ARMBaseRegisterInfo& MRI, 416 unsigned MIFlags = 0); 417 418 /// Tries to add registers to the reglist of a given base-updating 419 /// push/pop instruction to adjust the stack by an additional 420 /// NumBytes. This can save a few bytes per function in code-size, but 421 /// obviously generates more memory traffic. As such, it only takes 422 /// effect in functions being optimised for size. 423 bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget, 424 MachineFunction &MF, MachineInstr *MI, 425 unsigned NumBytes); 426 427 /// rewriteARMFrameIndex / rewriteT2FrameIndex - 428 /// Rewrite MI to access 'Offset' bytes from the FP. Return false if the 429 /// offset could not be handled directly in MI, and return the left-over 430 /// portion by reference. 431 bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 432 unsigned FrameReg, int &Offset, 433 const ARMBaseInstrInfo &TII); 434 435 bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, 436 unsigned FrameReg, int &Offset, 437 const ARMBaseInstrInfo &TII); 438 439 } // End llvm namespace 440 441 #endif 442
