| /external/llvm/lib/Target/ARM/ |
| ARMHazardRecognizer.cpp | 19 static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI,
30 return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI);
45 MachineInstr *DefMI = LastMI;
61 DefMI = &*I;
65 if (TII.isFpMLxInstruction(DefMI->getOpcode()) &&
67 hasRAWHazard(DefMI, MI, TII.getRegisterInfo()))) {
|
| MLxExpansionPass.cpp | 95 MachineInstr *DefMI = MRI->getVRegDef(Reg);
97 if (DefMI->getParent() != MBB)
99 if (DefMI->isCopyLike()) {
100 Reg = DefMI->getOperand(1).getReg();
102 DefMI = MRI->getVRegDef(Reg);
105 } else if (DefMI->isInsertSubreg()) {
106 Reg = DefMI->getOperand(2).getReg();
108 DefMI = MRI->getVRegDef(Reg);
114 return DefMI;
149 MachineInstr *DefMI = MRI->getVRegDef(Reg)
[all...] |
| ARMBaseInstrInfo.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| LiveRangeEdit.cpp | 52 const MachineInstr *DefMI,
54 assert(DefMI && "Missing instruction");
56 if (!TII.isTriviallyReMaterializable(DefMI, aa))
68 MachineInstr *DefMI = LIS.getInstructionFromIndex(VNI->def);
69 if (!DefMI)
71 checkRematerializable(VNI, DefMI, aa);
168 MachineInstr *DefMI = nullptr, *UseMI = nullptr;
174 if (DefMI && DefMI != MI)
178 DefMI = MI
[all...] |
| TargetSchedule.cpp | 156 const MachineInstr *DefMI, unsigned DefOperIdx,
160 return TII->defaultDefLatency(&SchedModel, DefMI);
165 OperLatency = TII->getOperandLatency(&InstrItins, DefMI, DefOperIdx,
169 unsigned DefClass = DefMI->getDesc().getSchedClass();
176 unsigned InstrLatency = TII->getInstrLatency(&InstrItins, DefMI);
184 TII->defaultDefLatency(&SchedModel, DefMI));
188 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI);
189 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx);
212 if (SCDesc->isValid() && !DefMI->getOperand(DefOperIdx).isImplicit()
213 && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef(
[all...] |
| MachineSink.cpp | 131 MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
132 if (DefMI->isCopyLike())
134 DEBUG(dbgs() << "Coalescing: " << *DefMI);
322 MachineInstr *DefMI = MRI->getVRegDef(Reg);
323 if (DefMI->getParent() == MI->getParent())
|
| MachineCSE.cpp | 129 MachineInstr *DefMI = MRI->getVRegDef(Reg);
130 if (!DefMI->isCopy())
132 unsigned SrcReg = DefMI->getOperand(1).getReg();
135 if (DefMI->getOperand(0).getSubReg())
149 if (DefMI->getOperand(1).getSubReg())
154 DEBUG(dbgs() << "Coalescing: " << *DefMI);
158 DefMI->eraseFromParent();
|
| PHIElimination.cpp | 155 MachineInstr *DefMI = *I;
156 unsigned DefReg = DefMI->getOperand(0).getReg();
159 LIS->RemoveMachineInstrFromMaps(DefMI);
160 DefMI->eraseFromParent();
392 if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg))
393 if (DefMI->isImplicitDef())
394 ImpDefs.insert(DefMI);
|
| EarlyIfConversion.cpp | 245 MachineInstr *DefMI = MRI->getVRegDef(Reg);
246 if (!DefMI || DefMI->getParent() != Head)
248 if (InsertAfter.insert(DefMI))
249 DEBUG(dbgs() << "BB#" << MBB->getNumber() << " depends on " << *DefMI);
250 if (DefMI->isTerminator()) {
|
| PeepholeOptimizer.cpp | 754 MachineInstr *DefMI = nullptr;
757 DefMI);
760 // DefMI.
764 LocalMIs.erase(DefMI);
767 DefMI->eraseFromParent();
[all...] |
| TailDuplication.cpp | 250 MachineInstr *DefMI = MRI->getVRegDef(VReg);
252 if (DefMI) {
253 DefBB = DefMI->getParent();
[all...] |
| InlineSpiller.cpp | 114 MachineInstr *DefMI;
125 SpillReg(Reg), SpillVNI(VNI), SpillMBB(nullptr), DefMI(nullptr) {}
128 bool hasDef() const { return DefByOrigPHI || DefMI; }
336 if (SVI.DefMI)
337 OS << " def: " << *SVI.DefMI;
400 DepSV.DefMI = SV.DefMI;
501 return SVI->second.DefMI;
619 SVI->second.DefMI = MI;
640 return SVI->second.DefMI;
[all...] |
| TwoAddressInstructionPass.cpp | 406 MachineInstr *DefMI = &MI;
412 if (!isPlainlyKilled(DefMI, Reg, LIS))
421 DefMI = Begin->getParent();
426 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
[all...] |
| RegisterCoalescer.cpp | 590 MachineInstr *DefMI = LIS->getInstructionFromIndex(AValNo->def);
591 if (!DefMI)
593 if (!DefMI->isCommutable())
595 // If DefMI is a two-address instruction then commuting it will change the
597 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg);
600 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
603 if (!TII->findCommutedOpIndices(DefMI, Op1, Op2))
612 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
637 << *DefMI);
641 MachineBasicBlock *MBB = DefMI->getParent()
[all...] |
| MachineScheduler.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsOptimizePICCall.cpp | 261 MachineInstr *DefMI = MRI.getVRegDef(Reg);
263 assert(DefMI);
265 // See if DefMI is an instruction that loads from a GOT entry that holds the
267 if (!DefMI->mayLoad() || DefMI->getNumOperands() < 3)
270 unsigned Flags = DefMI->getOperand(2).getTargetFlags();
276 assert(DefMI->hasOneMemOperand());
277 Val = (*DefMI->memoperands_begin())->getValue();
279 Val = (*DefMI->memoperands_begin())->getPseudoValue();
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.cpp | 294 const MachineInstr *DefMI = MRI.getVRegDef(VReg);
295 if (!DefMI->isFullCopy())
297 VReg = DefMI->getOperand(1).getReg();
312 const MachineInstr *DefMI = MRI.getVRegDef(VReg);
315 switch (DefMI->getOpcode()) {
319 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1)
325 if (!DefMI->getOperand(2).isImm() || DefMI->getOperand(2).getImm() != 1 ||
326 DefMI->getOperand(3).getImm() != 0)
335 unsigned ZReg = removeCopies(MRI, DefMI->getOperand(1).getReg())
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.cpp | [all...] |
