| /external/llvm/lib/Target/AArch64/ |
| AArch64TargetTransformInfo.cpp | 339 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f32, 1 },
340 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 },
341 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 },
347 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 2 },
348 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 1 },
349 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 1 },
355 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 },
356 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 2 },
361 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 },
362 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2 }
[all...] |
| AArch64ISelLowering.cpp | 183 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
184 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
185 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom);
415 setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand);
533 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Custom);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 263 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 },
265 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 },
267 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 },
281 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 },
283 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 4 },
285 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 8 },
299 { ISD::FP_TO_SINT, MVT::i1, MVT::f32, 2 },
301 { ISD::FP_TO_SINT, MVT::i1, MVT::f64, 2 },
303 { ISD::FP_TO_SINT, MVT::i8, MVT::f32, 2 },
305 { ISD::FP_TO_SINT, MVT::i8, MVT::f64, 2 }
[all...] |
| ARMISelLowering.cpp | 107 setOperationAction(ISD::FP_TO_SINT, VT, Custom);
112 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
530 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
563 setTargetDAGCombine(ISD::FP_TO_SINT);
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 415 FP_TO_SINT,
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 272 case ISD::FP_TO_SINT:
351 case ISD::FP_TO_SINT:
353 return PromoteFP_TO_INT(Op, Op->getOpcode() == ISD::FP_TO_SINT);
424 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewVT)) {
425 NewOpc = ISD::FP_TO_SINT;
[all...] |
| LegalizeFloatTypes.cpp | 629 case ISD::FP_TO_SINT: Res = SoftenFloatOp_FP_TO_SINT(N); break;
694 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_TO_SINT!");
[all...] |
| SelectionDAGDumper.cpp | 235 case ISD::FP_TO_SINT: return "fp_to_sint";
|
| LegalizeVectorTypes.cpp | 88 case ISD::FP_TO_SINT:
604 case ISD::FP_TO_SINT:
[all...] |
| LegalizeDAG.cpp | [all...] |
| LegalizeIntegerTypes.cpp | 99 case ISD::FP_TO_SINT:
387 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
392 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
393 NewOpc = ISD::FP_TO_SINT;
[all...] |
| FastISel.cpp | [all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| R600ISelLowering.cpp | 417 ConversionOp = ISD::FP_TO_SINT;
492 Cond = DAG.getNode(ISD::FP_TO_SINT, DL, MVT::i32,
|
| AMDILISelLowering.cpp | 545 SDValue iq = DAG.getNode(ISD::FP_TO_SINT, DL, INTTY, fq);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600ISelLowering.cpp | 417 ConversionOp = ISD::FP_TO_SINT;
492 Cond = DAG.getNode(ISD::FP_TO_SINT, DL, MVT::i32,
|
| AMDILISelLowering.cpp | 545 SDValue iq = DAG.getNode(ISD::FP_TO_SINT, DL, INTTY, fq);
|
| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 654 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 7 },
655 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 },
[all...] |
| X86ISelLowering.cpp | 367 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
370 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
372 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
373 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
376 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
378 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
380 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
381 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 252 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
253 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
354 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
372 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
378 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
492 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
601 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 257 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
268 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
[all...] |
| MipsSEISelLowering.cpp | 276 setOperationAction(ISD::FP_TO_SINT, Ty, Legal);
[all...] |
| /external/llvm/lib/Target/R600/ |
| AMDGPUISelLowering.cpp | 274 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Expand);
291 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
[all...] |
| /external/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | [all...] |
