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  /prebuilts/gcc/darwin-x86/mips/mips64el-linux-android-4.9/lib/gcc/mips64el-linux-android/4.9/include/
msa.h 43 typedef long long v2i64 __attribute__((vector_size(16), aligned(16))); typedef
59 extern v2i64 __builtin_msa_sll_d(v2i64, v2i64);
67 extern v2i64 __builtin_msa_slli_d(v2i64, unsigned char);
75 extern v2i64 __builtin_msa_sra_d(v2i64, v2i64);
83 extern v2i64 __builtin_msa_srai_d(v2i64, unsigned char)
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  /prebuilts/gcc/linux-x86/mips/mips64el-linux-android-4.9/lib/gcc/mips64el-linux-android/4.9/include/
msa.h 43 typedef long long v2i64 __attribute__((vector_size(16), aligned(16))); typedef
59 extern v2i64 __builtin_msa_sll_d(v2i64, v2i64);
67 extern v2i64 __builtin_msa_slli_d(v2i64, unsigned char);
75 extern v2i64 __builtin_msa_sra_d(v2i64, v2i64);
83 extern v2i64 __builtin_msa_srai_d(v2i64, unsigned char)
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  /external/llvm/lib/Target/X86/
X86TargetTransformInfo.cpp 214 { ISD::SHL, MVT::v2i64, 1 },
215 { ISD::SRL, MVT::v2i64, 1 },
262 { ISD::SHL, MVT::v2i64, 1 }, // psllq.
267 { ISD::SRL, MVT::v2i64, 1 }, // psrlq.
317 { ISD::SHL, MVT::v2i64, 2*10 }, // Scalarized.
323 { ISD::SRL, MVT::v2i64, 2*10 }, // Scalarized.
328 { ISD::SRA, MVT::v2i64, 2*10 }, // Scalarized.
339 { ISD::SDIV, MVT::v2i64, 2*20 },
343 { ISD::UDIV, MVT::v2i64, 2*20 },
362 // A v4i64 multiply is custom lowered as two split v2i64 vectors that the
    [all...]
X86ISelLowering.cpp     [all...]
  /external/llvm/include/llvm/CodeGen/
MachineValueType.h 84 v2i64 = 38, // 2 x i64 enumerator in enum:llvm::MVT::SimpleValueType
212 SimpleTy == MVT::v4i32 || SimpleTy == MVT::v2i64 ||
293 case v2i64:
347 case v2i64:
412 case v2i64:
543 if (NumElements == 2) return MVT::v2i64;
  /external/llvm/lib/Target/AArch64/
AArch64TargetTransformInfo.cpp 310 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 },
313 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 },
318 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 },
321 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 },
341 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 },
344 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 },
346 // Complex, from v2f32: legal type is v2i32 (no cost) or v2i64 (1 ext).
347 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 2 },
350 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 2 },
480 // unaligned v2i64 stores because the negative impact that has shown i
    [all...]
AArch64ISelDAGToDAG.cpp 497 case MVT::v2i64:
508 case MVT::v2i64:
    [all...]
AArch64ISelLowering.cpp 115 addQRTypeForNEON(MVT::v2i64);
432 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom);
433 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Custom);
436 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
486 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i64);
489 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i64);
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  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
AMDILISelLowering.cpp 66 (int)MVT::v2i64
94 (int)MVT::v2i64
122 if (VT != MVT::i64 && VT != MVT::v2i64) {
175 setOperationAction(ISD::MULHU, MVT::v2i64, Expand);
177 setOperationAction(ISD::MULHS, MVT::v2i64, Expand);
178 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
179 setOperationAction(ISD::SREM, MVT::v2i64, Expand);
181 setOperationAction(ISD::SDIV, MVT::v2i64, Expand);
182 setOperationAction(ISD::TRUNCATE, MVT::v2i64, Expand);
183 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Expand)
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  /external/mesa3d/src/gallium/drivers/radeon/
AMDILISelLowering.cpp 66 (int)MVT::v2i64
94 (int)MVT::v2i64
122 if (VT != MVT::i64 && VT != MVT::v2i64) {
175 setOperationAction(ISD::MULHU, MVT::v2i64, Expand);
177 setOperationAction(ISD::MULHS, MVT::v2i64, Expand);
178 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
179 setOperationAction(ISD::SREM, MVT::v2i64, Expand);
181 setOperationAction(ISD::SDIV, MVT::v2i64, Expand);
182 setOperationAction(ISD::TRUNCATE, MVT::v2i64, Expand);
183 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Expand)
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  /external/llvm/lib/Target/ARM/
ARMTargetTransformInfo.cpp 217 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 1 },
218 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i32, 1 },
456 {ISD::VECTOR_SHUFFLE, MVT::v2i64, 1},
478 {ISD::VECTOR_SHUFFLE, MVT::v2i64, 1},
531 { ISD::SDIV, MVT::v2i64, 2 * FunctionCallDivCost},
532 { ISD::UDIV, MVT::v2i64, 2 * FunctionCallDivCost},
533 { ISD::SREM, MVT::v2i64, 2 * FunctionCallDivCost},
534 { ISD::UREM, MVT::v2i64, 2 * FunctionCallDivCost},
564 // the vectorized code. Because we have support for v2i64 but not i64 those
566 // To work around this we increase the cost of v2i64 operations to make the
    [all...]
ARMISelDAGToDAG.cpp     [all...]
ARMISelLowering.cpp 436 addQRTypeForNEON(MVT::v2i64);
510 // Neon does not support some operations on v1i64 and v2i64 types.
515 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
522 setOperationAction(ISD::SETCC, MVT::v2i64, Expand);
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  /external/clang/test/CodeGen/
builtins-mips-msa.c 8 typedef signed long long v2i64 __attribute__ ((vector_size(16))); typedef
27 v2i64 v2i64_a = (v2i64) {0, 1};
28 v2i64 v2i64_b = (v2i64) {1, 2};
29 v2i64 v2i64_r;
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  /external/llvm/lib/IR/
ValueTypes.cpp 156 case MVT::v2i64: return "v2i64";
224 case MVT::v2i64: return VectorType::get(Type::getInt64Ty(Context), 2);
  /external/llvm/lib/Target/PowerPC/
PPCTargetTransformInfo.cpp 394 if (LT.second == MVT::v2f64 || LT.second == MVT::v2i64)
PPCISelLowering.cpp 582 // VSX v2i64 only supports non-arithmetic operations.
583 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
584 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
586 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
587 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
588 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
590 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
592 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
593 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
594 setOperationAction(ISD::STORE, MVT::v2i64, Promote)
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PPCISelDAGToDAG.cpp     [all...]
  /external/llvm/lib/Target/Mips/
MipsSEInstrInfo.cpp 217 else if (RC->hasType(MVT::v2i64) || RC->hasType(MVT::v2f64))
258 else if (RC->hasType(MVT::v2i64) || RC->hasType(MVT::v2f64))
MipsSEISelLowering.cpp 92 addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass);
275 if (Ty == MVT::v4i32 || Ty == MVT::v2i64) {
    [all...]
MipsSEISelDAGToDAG.cpp 841 ViaVecTy = MVT::v2i64;
  /external/llvm/lib/Target/X86/InstPrinter/
X86InstComments.cpp 219 DecodeUNPCKHMask(MVT::v2i64, ShuffleMask);
292 DecodeUNPCKLMask(MVT::v2i64, ShuffleMask);
  /external/llvm/utils/TableGen/
CodeGenTarget.cpp 97 case MVT::v2i64: return "MVT::v2i64";
  /external/llvm/lib/Target/NVPTX/
NVPTXISelLowering.cpp 63 case MVT::v2i64:
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  /external/llvm/lib/Target/R600/
AMDGPUISelLowering.cpp 158 AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v2i64);
178 setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand);
204 AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v2i64);
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