| /external/llvm/lib/Target/XCore/ |
| XCoreFrameLowering.cpp | 106 int Opcode = isImmU6(OpImm) ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
107 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(OpImm);
128 int Opcode = isImmU6(OpImm) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
129 BuildMI(MBB, MBBI, dl, TII.get(Opcode), XCore::SP).addImm(OpImm);
200 int Opcode = isImmU6(Offset) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
201 BuildMI(MBB, MBBI, dl, TII.get(Opcode), SpillList[i].Reg)
261 int Opcode = isImmU6(Adjusted) ? XCore::ENTSP_u6 : XCore::ENTSP_lu6;
263 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opcode));
285 int Opcode = isImmU6(Offset) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
287 BuildMI(MBB, MBBI, dl, TII.get(Opcode))
[all...] |
| /external/llvm/tools/llvm-readobj/ |
| ARMEHABIPrinter.h | 96 uint8_t Opcode = Opcodes[OI++ ^ 3];
97 SW.startLine() << format("0x%02X ; vsp = vsp + %u\n", Opcode,
98 ((Opcode & 0x3f) << 2) + 4);
101 uint8_t Opcode = Opcodes[OI++ ^ 3];
102 SW.startLine() << format("0x%02X ; vsp = vsp - %u\n", Opcode,
103 ((Opcode & 0x3f) << 2) + 4);
119 uint8_t Opcode = Opcodes[OI++ ^ 3];
120 SW.startLine() << format("0x%02X ; reserved (ARM MOVrr)\n", Opcode);
123 uint8_t Opcode = Opcodes[OI++ ^ 3];
124 SW.startLine() << format("0x%02X ; reserved (WiMMX MOVrr)\n", Opcode);
[all...] |
| /external/chromium_org/sandbox/win/src/sidestep/ |
| mini_disassembler_types.h | 15 // This opcode is not used
17 // This disassembler does not recognize this opcode (error)
117 // Everything that's in an Opcode (see below) except the three
118 // alternative opcode structs for different prefixes.
121 // byte in the opcode.
124 // The opcode type
140 struct Opcode {
142 // byte in the opcode.
145 // The opcode type
158 // Alternative opcode info if certain prefixes are specified
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/ |
| radeon_opcodes.h | 243 rc_opcode Opcode;
269 static inline const struct rc_opcode_info * rc_get_opcode_info(rc_opcode opcode)
271 assert((unsigned int)opcode < MAX_RC_OPCODE);
272 assert(rc_opcodes[opcode].Opcode == opcode);
274 return &rc_opcodes[opcode];
|
| /external/chromium_org/third_party/tcmalloc/chromium/src/windows/ |
| mini_disassembler_types.h | 44 // This opcode is not used
46 // This disassembler does not recognize this opcode (error)
156 // Everything that's in an Opcode (see below) except the three
157 // alternative opcode structs for different prefixes.
160 // byte in the opcode.
163 // The opcode type
179 struct Opcode {
181 // byte in the opcode.
184 // The opcode type
197 // Alternative opcode info if certain prefixes are specified
[all...] |
| /external/chromium_org/third_party/tcmalloc/vendor/src/windows/ |
| mini_disassembler_types.h | 44 // This opcode is not used
46 // This disassembler does not recognize this opcode (error)
156 // Everything that's in an Opcode (see below) except the three
157 // alternative opcode structs for different prefixes.
160 // byte in the opcode.
163 // The opcode type
179 struct Opcode {
181 // byte in the opcode.
184 // The opcode type
197 // Alternative opcode info if certain prefixes are specified
[all...] |
| /external/chromium_org/tools/traceline/traceline/sidestep/ |
| mini_disassembler_types.h | 15 // This opcode is not used
17 // This disassembler does not recognize this opcode (error)
117 // Everything that's in an Opcode (see below) except the three
118 // alternative opcode structs for different prefixes.
121 // byte in the opcode.
124 // The opcode type
140 struct Opcode {
142 // byte in the opcode.
145 // The opcode type
158 // Alternative opcode info if certain prefixes are specified
[all...] |
| /external/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | 59 unsigned Opcode = MI->getOpcode();
61 if (Opcode == AArch64::SYSxt)
68 if (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri ||
69 Opcode == AArch64::UBFMXri || Opcode == AArch64::UBFMWri) {
75 bool IsSigned = (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri);
76 bool Is64Bit = (Opcode == AArch64::SBFMXri || Opcode == AArch64::UBFMXri)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMExpandPseudoInsts.cpp | 332 static const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) {
347 std::lower_bound(NEONLdStTable, NEONLdStTable + NumEntries, Opcode);
348 if (I != NEONLdStTable + NumEntries && I->PseudoOpc == Opcode)
[all...] |
| Thumb2SizeReduction.cpp | 44 uint16_t WideOpc; // Wide opcode
45 uint16_t NarrowOpc1; // Narrow opcode to transform to
46 uint16_t NarrowOpc2; // Narrow opcode when it's two-address
107 // FIXME: Clean this up after splitting each Thumb load / store opcode
147 /// ReduceOpcodeMap - Maps wide opcode to index of entry in ReduceTable.
316 /// Old opcode has an optional def of CPSR.
319 // If old opcode does not implicitly define CPSR, then it's not ok since
381 llvm_unreachable("Unexpected Thumb2 load / store opcode!");
616 // source insn opcode. So for now, we hack a local entry record to use.
891 unsigned Opcode = MI->getOpcode()
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelDAGToDAG.cpp | 632 unsigned Opcode = Node->getOpcode();
641 switch(Opcode) {
|
| /external/llvm/lib/Target/R600/ |
| R600ControlFlowFinalizer.cpp | 56 bool requiresWorkAroundForInst(unsigned Opcode);
59 void pushBranch(unsigned Opcode, bool isWQM = false);
78 bool CFStack::requiresWorkAroundForInst(unsigned Opcode) {
79 if (Opcode == AMDGPU::CF_ALU_PUSH_BEFORE && ST.hasCaymanISA() &&
86 switch(Opcode) {
150 void CFStack::pushBranch(unsigned Opcode, bool isWQM) {
152 switch(Opcode) {
235 unsigned Opcode = 0;
239 Opcode = isEg ? AMDGPU::CF_TC_EG : AMDGPU::CF_TC_R600;
242 Opcode = isEg ? AMDGPU::CF_VC_EG : AMDGPU::CF_VC_R600
[all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCCodeEmitter.cpp | 610 /// EmitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix
624 // VEX_R: opcode externsion equivalent to REX.R in
647 // VEX_W: opcode specific (use like REX.W, or used for
648 // opcode extension, or ignored, depending on the opcode byte)
654 // 0b00001: implied 0F leading opcode
655 // 0b00010: implied 0F 38 leading opcode bytes
656 // 0b00011: implied 0F 3A leading opcode bytes
676 // VEX_PP: opcode extension providing equivalent
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| Reassociate.cpp | 235 /// opcode and if it only has one use.
236 static BinaryOperator *isReassociableOp(Value *V, unsigned Opcode) {
238 cast<Instruction>(V)->getOpcode() == Opcode)
349 static void IncorporateWeight(APInt &LHS, const APInt &RHS, unsigned Opcode) {
367 if (Instruction::isIdempotent(Opcode)) {
374 if (Instruction::isNilpotent(Opcode)) {
380 if (Opcode == Instruction::Add) {
386 assert(Opcode == Instruction::Mul && "Unknown associative operation!");
444 /// opcode), or is the same kind of binary operator but has a use which either
501 unsigned Opcode = I->getOpcode()
[all...] |
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_opcodes.h | 243 rc_opcode Opcode;
269 static inline const struct rc_opcode_info * rc_get_opcode_info(rc_opcode opcode)
271 assert((unsigned int)opcode < MAX_RC_OPCODE);
272 assert(rc_opcodes[opcode].Opcode == opcode);
274 return &rc_opcodes[opcode];
|
| /external/llvm/examples/Kaleidoscope/Chapter6/ |
| toy.cpp | 130 char Opcode;
133 UnaryExprAST(char opcode, ExprAST *operand)
134 : Opcode(opcode), Operand(operand) {}
564 Function *F = TheModule->getFunction(std::string("unary")+Opcode);
|
| /external/llvm/examples/Kaleidoscope/Chapter7/ |
| toy.cpp | 135 char Opcode;
138 UnaryExprAST(char opcode, ExprAST *operand)
139 : Opcode(opcode), Operand(operand) {}
642 Function *F = TheModule->getFunction(std::string("unary")+Opcode);
[all...] |
| /external/llvm/examples/Kaleidoscope/MCJIT/cached/ |
| toy-jit.cpp | 153 char Opcode;
156 UnaryExprAST(char opcode, ExprAST *operand)
157 : Opcode(opcode), Operand(operand) {}
659 Function *F = TheHelper->getFunction(MakeLegalFunctionName(std::string("unary")+Opcode));
661 Function *F = TheModule->getFunction(std::string("unary")+Opcode);
[all...] |
| /external/llvm/examples/Kaleidoscope/MCJIT/lazy/ |
| toy-jit.cpp | 138 char Opcode;
141 UnaryExprAST(char opcode, ExprAST *operand)
142 : Opcode(opcode), Operand(operand) {}
644 Function *F = TheHelper->getFunction(MakeLegalFunctionName(std::string("unary")+Opcode));
646 Function *F = TheModule->getFunction(std::string("unary")+Opcode);
[all...] |
| /external/llvm/include/llvm/MC/ |
| MCInstrDesc.h | 139 unsigned short Opcode; // The opcode number
180 /// \brief Return the opcode number for this descriptor.
182 return Opcode;
575 /// or zero if the encoding size cannot be known from the opcode.
|
| /external/llvm/lib/Analysis/ |
| InstructionSimplify.cpp | 124 /// it into "(A op B) op' (A op C)". Here "op" is given by Opcode and "op'" is
128 static Value *ExpandBinOp(unsigned Opcode, Value *LHS, Value *RHS,
142 if (Value *L = SimplifyBinOp(Opcode, A, C, Q, MaxRecurse))
143 if (Value *R = SimplifyBinOp(Opcode, B, C, Q, MaxRecurse)) {
165 if (Value *L = SimplifyBinOp(Opcode, A, B, Q, MaxRecurse))
166 if (Value *R = SimplifyBinOp(Opcode, A, C, Q, MaxRecurse)) {
189 Instruction::BinaryOps Opcode = (Instruction::BinaryOps)Opc;
190 assert(Instruction::isAssociative(Opcode) && "Not an associative operation!");
200 if (Op0 && Op0->getOpcode() == Opcode) {
206 if (Value *V = SimplifyBinOp(Opcode, B, C, Q, MaxRecurse))
[all...] |
| ValueTracking.cpp | 669 unsigned Opcode = LU->getOpcode();
673 if (Opcode == Instruction::Add ||
674 Opcode == Instruction::Sub ||
675 Opcode == Instruction::And ||
676 Opcode == Instruction::Or ||
677 Opcode == Instruction::Mul) {
[all...] |
| /external/llvm/lib/CodeGen/ |
| MachineLICM.cpp | 103 // For each opcode, keep a list of potential CSE instructions.
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGRRList.cpp | 275 /// opcode to determine what register class is being generated.
298 unsigned Opcode = Node->getMachineOpcode();
299 if (Opcode == TargetOpcode::REG_SEQUENCE) {
308 const MCInstrDesc Desc = TII->get(Opcode);
[all...] |
