1 //===- CodeGenRegisters.cpp - Register and RegisterClass Info -------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines structures to encapsulate information gleaned from the 11 // target register and register class definitions. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "CodeGenRegisters.h" 16 #include "CodeGenTarget.h" 17 #include "llvm/ADT/IntEqClasses.h" 18 #include "llvm/ADT/STLExtras.h" 19 #include "llvm/ADT/SmallVector.h" 20 #include "llvm/ADT/StringExtras.h" 21 #include "llvm/ADT/Twine.h" 22 #include "llvm/Support/Debug.h" 23 #include "llvm/TableGen/Error.h" 24 25 using namespace llvm; 26 27 #define DEBUG_TYPE "regalloc-emitter" 28 29 //===----------------------------------------------------------------------===// 30 // CodeGenSubRegIndex 31 //===----------------------------------------------------------------------===// 32 33 CodeGenSubRegIndex::CodeGenSubRegIndex(Record *R, unsigned Enum) 34 : TheDef(R), EnumValue(Enum), LaneMask(0), AllSuperRegsCovered(true) { 35 Name = R->getName(); 36 if (R->getValue("Namespace")) 37 Namespace = R->getValueAsString("Namespace"); 38 Size = R->getValueAsInt("Size"); 39 Offset = R->getValueAsInt("Offset"); 40 } 41 42 CodeGenSubRegIndex::CodeGenSubRegIndex(StringRef N, StringRef Nspace, 43 unsigned Enum) 44 : TheDef(nullptr), Name(N), Namespace(Nspace), Size(-1), Offset(-1), 45 EnumValue(Enum), LaneMask(0), AllSuperRegsCovered(true) { 46 } 47 48 std::string CodeGenSubRegIndex::getQualifiedName() const { 49 std::string N = getNamespace(); 50 if (!N.empty()) 51 N += "::"; 52 N += getName(); 53 return N; 54 } 55 56 void CodeGenSubRegIndex::updateComponents(CodeGenRegBank &RegBank) { 57 if (!TheDef) 58 return; 59 60 std::vector<Record*> Comps = TheDef->getValueAsListOfDefs("ComposedOf"); 61 if (!Comps.empty()) { 62 if (Comps.size() != 2) 63 PrintFatalError(TheDef->getLoc(), 64 "ComposedOf must have exactly two entries"); 65 CodeGenSubRegIndex *A = RegBank.getSubRegIdx(Comps[0]); 66 CodeGenSubRegIndex *B = RegBank.getSubRegIdx(Comps[1]); 67 CodeGenSubRegIndex *X = A->addComposite(B, this); 68 if (X) 69 PrintFatalError(TheDef->getLoc(), "Ambiguous ComposedOf entries"); 70 } 71 72 std::vector<Record*> Parts = 73 TheDef->getValueAsListOfDefs("CoveringSubRegIndices"); 74 if (!Parts.empty()) { 75 if (Parts.size() < 2) 76 PrintFatalError(TheDef->getLoc(), 77 "CoveredBySubRegs must have two or more entries"); 78 SmallVector<CodeGenSubRegIndex*, 8> IdxParts; 79 for (unsigned i = 0, e = Parts.size(); i != e; ++i) 80 IdxParts.push_back(RegBank.getSubRegIdx(Parts[i])); 81 RegBank.addConcatSubRegIndex(IdxParts, this); 82 } 83 } 84 85 unsigned CodeGenSubRegIndex::computeLaneMask() { 86 // Already computed? 87 if (LaneMask) 88 return LaneMask; 89 90 // Recursion guard, shouldn't be required. 91 LaneMask = ~0u; 92 93 // The lane mask is simply the union of all sub-indices. 94 unsigned M = 0; 95 for (CompMap::iterator I = Composed.begin(), E = Composed.end(); I != E; ++I) 96 M |= I->second->computeLaneMask(); 97 assert(M && "Missing lane mask, sub-register cycle?"); 98 LaneMask = M; 99 return LaneMask; 100 } 101 102 //===----------------------------------------------------------------------===// 103 // CodeGenRegister 104 //===----------------------------------------------------------------------===// 105 106 CodeGenRegister::CodeGenRegister(Record *R, unsigned Enum) 107 : TheDef(R), 108 EnumValue(Enum), 109 CostPerUse(R->getValueAsInt("CostPerUse")), 110 CoveredBySubRegs(R->getValueAsBit("CoveredBySubRegs")), 111 NumNativeRegUnits(0), 112 SubRegsComplete(false), 113 SuperRegsComplete(false), 114 TopoSig(~0u) 115 {} 116 117 void CodeGenRegister::buildObjectGraph(CodeGenRegBank &RegBank) { 118 std::vector<Record*> SRIs = TheDef->getValueAsListOfDefs("SubRegIndices"); 119 std::vector<Record*> SRs = TheDef->getValueAsListOfDefs("SubRegs"); 120 121 if (SRIs.size() != SRs.size()) 122 PrintFatalError(TheDef->getLoc(), 123 "SubRegs and SubRegIndices must have the same size"); 124 125 for (unsigned i = 0, e = SRIs.size(); i != e; ++i) { 126 ExplicitSubRegIndices.push_back(RegBank.getSubRegIdx(SRIs[i])); 127 ExplicitSubRegs.push_back(RegBank.getReg(SRs[i])); 128 } 129 130 // Also compute leading super-registers. Each register has a list of 131 // covered-by-subregs super-registers where it appears as the first explicit 132 // sub-register. 133 // 134 // This is used by computeSecondarySubRegs() to find candidates. 135 if (CoveredBySubRegs && !ExplicitSubRegs.empty()) 136 ExplicitSubRegs.front()->LeadingSuperRegs.push_back(this); 137 138 // Add ad hoc alias links. This is a symmetric relationship between two 139 // registers, so build a symmetric graph by adding links in both ends. 140 std::vector<Record*> Aliases = TheDef->getValueAsListOfDefs("Aliases"); 141 for (unsigned i = 0, e = Aliases.size(); i != e; ++i) { 142 CodeGenRegister *Reg = RegBank.getReg(Aliases[i]); 143 ExplicitAliases.push_back(Reg); 144 Reg->ExplicitAliases.push_back(this); 145 } 146 } 147 148 const std::string &CodeGenRegister::getName() const { 149 return TheDef->getName(); 150 } 151 152 namespace { 153 // Iterate over all register units in a set of registers. 154 class RegUnitIterator { 155 CodeGenRegister::Set::const_iterator RegI, RegE; 156 CodeGenRegister::RegUnitList::const_iterator UnitI, UnitE; 157 158 public: 159 RegUnitIterator(const CodeGenRegister::Set &Regs): 160 RegI(Regs.begin()), RegE(Regs.end()), UnitI(), UnitE() { 161 162 if (RegI != RegE) { 163 UnitI = (*RegI)->getRegUnits().begin(); 164 UnitE = (*RegI)->getRegUnits().end(); 165 advance(); 166 } 167 } 168 169 bool isValid() const { return UnitI != UnitE; } 170 171 unsigned operator* () const { assert(isValid()); return *UnitI; } 172 173 const CodeGenRegister *getReg() const { assert(isValid()); return *RegI; } 174 175 /// Preincrement. Move to the next unit. 176 void operator++() { 177 assert(isValid() && "Cannot advance beyond the last operand"); 178 ++UnitI; 179 advance(); 180 } 181 182 protected: 183 void advance() { 184 while (UnitI == UnitE) { 185 if (++RegI == RegE) 186 break; 187 UnitI = (*RegI)->getRegUnits().begin(); 188 UnitE = (*RegI)->getRegUnits().end(); 189 } 190 } 191 }; 192 } // namespace 193 194 // Merge two RegUnitLists maintaining the order and removing duplicates. 195 // Overwrites MergedRU in the process. 196 static void mergeRegUnits(CodeGenRegister::RegUnitList &MergedRU, 197 const CodeGenRegister::RegUnitList &RRU) { 198 CodeGenRegister::RegUnitList LRU = MergedRU; 199 MergedRU.clear(); 200 std::set_union(LRU.begin(), LRU.end(), RRU.begin(), RRU.end(), 201 std::back_inserter(MergedRU)); 202 } 203 204 // Return true of this unit appears in RegUnits. 205 static bool hasRegUnit(CodeGenRegister::RegUnitList &RegUnits, unsigned Unit) { 206 return std::count(RegUnits.begin(), RegUnits.end(), Unit); 207 } 208 209 // Inherit register units from subregisters. 210 // Return true if the RegUnits changed. 211 bool CodeGenRegister::inheritRegUnits(CodeGenRegBank &RegBank) { 212 unsigned OldNumUnits = RegUnits.size(); 213 for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end(); 214 I != E; ++I) { 215 CodeGenRegister *SR = I->second; 216 // Merge the subregister's units into this register's RegUnits. 217 mergeRegUnits(RegUnits, SR->RegUnits); 218 } 219 return OldNumUnits != RegUnits.size(); 220 } 221 222 const CodeGenRegister::SubRegMap & 223 CodeGenRegister::computeSubRegs(CodeGenRegBank &RegBank) { 224 // Only compute this map once. 225 if (SubRegsComplete) 226 return SubRegs; 227 SubRegsComplete = true; 228 229 // First insert the explicit subregs and make sure they are fully indexed. 230 for (unsigned i = 0, e = ExplicitSubRegs.size(); i != e; ++i) { 231 CodeGenRegister *SR = ExplicitSubRegs[i]; 232 CodeGenSubRegIndex *Idx = ExplicitSubRegIndices[i]; 233 if (!SubRegs.insert(std::make_pair(Idx, SR)).second) 234 PrintFatalError(TheDef->getLoc(), "SubRegIndex " + Idx->getName() + 235 " appears twice in Register " + getName()); 236 // Map explicit sub-registers first, so the names take precedence. 237 // The inherited sub-registers are mapped below. 238 SubReg2Idx.insert(std::make_pair(SR, Idx)); 239 } 240 241 // Keep track of inherited subregs and how they can be reached. 242 SmallPtrSet<CodeGenRegister*, 8> Orphans; 243 244 // Clone inherited subregs and place duplicate entries in Orphans. 245 // Here the order is important - earlier subregs take precedence. 246 for (unsigned i = 0, e = ExplicitSubRegs.size(); i != e; ++i) { 247 CodeGenRegister *SR = ExplicitSubRegs[i]; 248 const SubRegMap &Map = SR->computeSubRegs(RegBank); 249 250 for (SubRegMap::const_iterator SI = Map.begin(), SE = Map.end(); SI != SE; 251 ++SI) { 252 if (!SubRegs.insert(*SI).second) 253 Orphans.insert(SI->second); 254 } 255 } 256 257 // Expand any composed subreg indices. 258 // If dsub_2 has ComposedOf = [qsub_1, dsub_0], and this register has a 259 // qsub_1 subreg, add a dsub_2 subreg. Keep growing Indices and process 260 // expanded subreg indices recursively. 261 SmallVector<CodeGenSubRegIndex*, 8> Indices = ExplicitSubRegIndices; 262 for (unsigned i = 0; i != Indices.size(); ++i) { 263 CodeGenSubRegIndex *Idx = Indices[i]; 264 const CodeGenSubRegIndex::CompMap &Comps = Idx->getComposites(); 265 CodeGenRegister *SR = SubRegs[Idx]; 266 const SubRegMap &Map = SR->computeSubRegs(RegBank); 267 268 // Look at the possible compositions of Idx. 269 // They may not all be supported by SR. 270 for (CodeGenSubRegIndex::CompMap::const_iterator I = Comps.begin(), 271 E = Comps.end(); I != E; ++I) { 272 SubRegMap::const_iterator SRI = Map.find(I->first); 273 if (SRI == Map.end()) 274 continue; // Idx + I->first doesn't exist in SR. 275 // Add I->second as a name for the subreg SRI->second, assuming it is 276 // orphaned, and the name isn't already used for something else. 277 if (SubRegs.count(I->second) || !Orphans.erase(SRI->second)) 278 continue; 279 // We found a new name for the orphaned sub-register. 280 SubRegs.insert(std::make_pair(I->second, SRI->second)); 281 Indices.push_back(I->second); 282 } 283 } 284 285 // Now Orphans contains the inherited subregisters without a direct index. 286 // Create inferred indexes for all missing entries. 287 // Work backwards in the Indices vector in order to compose subregs bottom-up. 288 // Consider this subreg sequence: 289 // 290 // qsub_1 -> dsub_0 -> ssub_0 291 // 292 // The qsub_1 -> dsub_0 composition becomes dsub_2, so the ssub_0 register 293 // can be reached in two different ways: 294 // 295 // qsub_1 -> ssub_0 296 // dsub_2 -> ssub_0 297 // 298 // We pick the latter composition because another register may have [dsub_0, 299 // dsub_1, dsub_2] subregs without necessarily having a qsub_1 subreg. The 300 // dsub_2 -> ssub_0 composition can be shared. 301 while (!Indices.empty() && !Orphans.empty()) { 302 CodeGenSubRegIndex *Idx = Indices.pop_back_val(); 303 CodeGenRegister *SR = SubRegs[Idx]; 304 const SubRegMap &Map = SR->computeSubRegs(RegBank); 305 for (SubRegMap::const_iterator SI = Map.begin(), SE = Map.end(); SI != SE; 306 ++SI) 307 if (Orphans.erase(SI->second)) 308 SubRegs[RegBank.getCompositeSubRegIndex(Idx, SI->first)] = SI->second; 309 } 310 311 // Compute the inverse SubReg -> Idx map. 312 for (SubRegMap::const_iterator SI = SubRegs.begin(), SE = SubRegs.end(); 313 SI != SE; ++SI) { 314 if (SI->second == this) { 315 ArrayRef<SMLoc> Loc; 316 if (TheDef) 317 Loc = TheDef->getLoc(); 318 PrintFatalError(Loc, "Register " + getName() + 319 " has itself as a sub-register"); 320 } 321 322 // Compute AllSuperRegsCovered. 323 if (!CoveredBySubRegs) 324 SI->first->AllSuperRegsCovered = false; 325 326 // Ensure that every sub-register has a unique name. 327 DenseMap<const CodeGenRegister*, CodeGenSubRegIndex*>::iterator Ins = 328 SubReg2Idx.insert(std::make_pair(SI->second, SI->first)).first; 329 if (Ins->second == SI->first) 330 continue; 331 // Trouble: Two different names for SI->second. 332 ArrayRef<SMLoc> Loc; 333 if (TheDef) 334 Loc = TheDef->getLoc(); 335 PrintFatalError(Loc, "Sub-register can't have two names: " + 336 SI->second->getName() + " available as " + 337 SI->first->getName() + " and " + Ins->second->getName()); 338 } 339 340 // Derive possible names for sub-register concatenations from any explicit 341 // sub-registers. By doing this before computeSecondarySubRegs(), we ensure 342 // that getConcatSubRegIndex() won't invent any concatenated indices that the 343 // user already specified. 344 for (unsigned i = 0, e = ExplicitSubRegs.size(); i != e; ++i) { 345 CodeGenRegister *SR = ExplicitSubRegs[i]; 346 if (!SR->CoveredBySubRegs || SR->ExplicitSubRegs.size() <= 1) 347 continue; 348 349 // SR is composed of multiple sub-regs. Find their names in this register. 350 SmallVector<CodeGenSubRegIndex*, 8> Parts; 351 for (unsigned j = 0, e = SR->ExplicitSubRegs.size(); j != e; ++j) 352 Parts.push_back(getSubRegIndex(SR->ExplicitSubRegs[j])); 353 354 // Offer this as an existing spelling for the concatenation of Parts. 355 RegBank.addConcatSubRegIndex(Parts, ExplicitSubRegIndices[i]); 356 } 357 358 // Initialize RegUnitList. Because getSubRegs is called recursively, this 359 // processes the register hierarchy in postorder. 360 // 361 // Inherit all sub-register units. It is good enough to look at the explicit 362 // sub-registers, the other registers won't contribute any more units. 363 for (unsigned i = 0, e = ExplicitSubRegs.size(); i != e; ++i) { 364 CodeGenRegister *SR = ExplicitSubRegs[i]; 365 // Explicit sub-registers are usually disjoint, so this is a good way of 366 // computing the union. We may pick up a few duplicates that will be 367 // eliminated below. 368 unsigned N = RegUnits.size(); 369 RegUnits.append(SR->RegUnits.begin(), SR->RegUnits.end()); 370 std::inplace_merge(RegUnits.begin(), RegUnits.begin() + N, RegUnits.end()); 371 } 372 RegUnits.erase(std::unique(RegUnits.begin(), RegUnits.end()), RegUnits.end()); 373 374 // Absent any ad hoc aliasing, we create one register unit per leaf register. 375 // These units correspond to the maximal cliques in the register overlap 376 // graph which is optimal. 377 // 378 // When there is ad hoc aliasing, we simply create one unit per edge in the 379 // undirected ad hoc aliasing graph. Technically, we could do better by 380 // identifying maximal cliques in the ad hoc graph, but cliques larger than 2 381 // are extremely rare anyway (I've never seen one), so we don't bother with 382 // the added complexity. 383 for (unsigned i = 0, e = ExplicitAliases.size(); i != e; ++i) { 384 CodeGenRegister *AR = ExplicitAliases[i]; 385 // Only visit each edge once. 386 if (AR->SubRegsComplete) 387 continue; 388 // Create a RegUnit representing this alias edge, and add it to both 389 // registers. 390 unsigned Unit = RegBank.newRegUnit(this, AR); 391 RegUnits.push_back(Unit); 392 AR->RegUnits.push_back(Unit); 393 } 394 395 // Finally, create units for leaf registers without ad hoc aliases. Note that 396 // a leaf register with ad hoc aliases doesn't get its own unit - it isn't 397 // necessary. This means the aliasing leaf registers can share a single unit. 398 if (RegUnits.empty()) 399 RegUnits.push_back(RegBank.newRegUnit(this)); 400 401 // We have now computed the native register units. More may be adopted later 402 // for balancing purposes. 403 NumNativeRegUnits = RegUnits.size(); 404 405 return SubRegs; 406 } 407 408 // In a register that is covered by its sub-registers, try to find redundant 409 // sub-registers. For example: 410 // 411 // QQ0 = {Q0, Q1} 412 // Q0 = {D0, D1} 413 // Q1 = {D2, D3} 414 // 415 // We can infer that D1_D2 is also a sub-register, even if it wasn't named in 416 // the register definition. 417 // 418 // The explicitly specified registers form a tree. This function discovers 419 // sub-register relationships that would force a DAG. 420 // 421 void CodeGenRegister::computeSecondarySubRegs(CodeGenRegBank &RegBank) { 422 // Collect new sub-registers first, add them later. 423 SmallVector<SubRegMap::value_type, 8> NewSubRegs; 424 425 // Look at the leading super-registers of each sub-register. Those are the 426 // candidates for new sub-registers, assuming they are fully contained in 427 // this register. 428 for (SubRegMap::iterator I = SubRegs.begin(), E = SubRegs.end(); I != E; ++I){ 429 const CodeGenRegister *SubReg = I->second; 430 const CodeGenRegister::SuperRegList &Leads = SubReg->LeadingSuperRegs; 431 for (unsigned i = 0, e = Leads.size(); i != e; ++i) { 432 CodeGenRegister *Cand = const_cast<CodeGenRegister*>(Leads[i]); 433 // Already got this sub-register? 434 if (Cand == this || getSubRegIndex(Cand)) 435 continue; 436 // Check if each component of Cand is already a sub-register. 437 // We know that the first component is I->second, and is present with the 438 // name I->first. 439 SmallVector<CodeGenSubRegIndex*, 8> Parts(1, I->first); 440 assert(!Cand->ExplicitSubRegs.empty() && 441 "Super-register has no sub-registers"); 442 for (unsigned j = 1, e = Cand->ExplicitSubRegs.size(); j != e; ++j) { 443 if (CodeGenSubRegIndex *Idx = getSubRegIndex(Cand->ExplicitSubRegs[j])) 444 Parts.push_back(Idx); 445 else { 446 // Sub-register doesn't exist. 447 Parts.clear(); 448 break; 449 } 450 } 451 // If some Cand sub-register is not part of this register, or if Cand only 452 // has one sub-register, there is nothing to do. 453 if (Parts.size() <= 1) 454 continue; 455 456 // Each part of Cand is a sub-register of this. Make the full Cand also 457 // a sub-register with a concatenated sub-register index. 458 CodeGenSubRegIndex *Concat= RegBank.getConcatSubRegIndex(Parts); 459 NewSubRegs.push_back(std::make_pair(Concat, Cand)); 460 } 461 } 462 463 // Now add all the new sub-registers. 464 for (unsigned i = 0, e = NewSubRegs.size(); i != e; ++i) { 465 // Don't add Cand if another sub-register is already using the index. 466 if (!SubRegs.insert(NewSubRegs[i]).second) 467 continue; 468 469 CodeGenSubRegIndex *NewIdx = NewSubRegs[i].first; 470 CodeGenRegister *NewSubReg = NewSubRegs[i].second; 471 SubReg2Idx.insert(std::make_pair(NewSubReg, NewIdx)); 472 } 473 474 // Create sub-register index composition maps for the synthesized indices. 475 for (unsigned i = 0, e = NewSubRegs.size(); i != e; ++i) { 476 CodeGenSubRegIndex *NewIdx = NewSubRegs[i].first; 477 CodeGenRegister *NewSubReg = NewSubRegs[i].second; 478 for (SubRegMap::const_iterator SI = NewSubReg->SubRegs.begin(), 479 SE = NewSubReg->SubRegs.end(); SI != SE; ++SI) { 480 CodeGenSubRegIndex *SubIdx = getSubRegIndex(SI->second); 481 if (!SubIdx) 482 PrintFatalError(TheDef->getLoc(), "No SubRegIndex for " + 483 SI->second->getName() + " in " + getName()); 484 NewIdx->addComposite(SI->first, SubIdx); 485 } 486 } 487 } 488 489 void CodeGenRegister::computeSuperRegs(CodeGenRegBank &RegBank) { 490 // Only visit each register once. 491 if (SuperRegsComplete) 492 return; 493 SuperRegsComplete = true; 494 495 // Make sure all sub-registers have been visited first, so the super-reg 496 // lists will be topologically ordered. 497 for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end(); 498 I != E; ++I) 499 I->second->computeSuperRegs(RegBank); 500 501 // Now add this as a super-register on all sub-registers. 502 // Also compute the TopoSigId in post-order. 503 TopoSigId Id; 504 for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end(); 505 I != E; ++I) { 506 // Topological signature computed from SubIdx, TopoId(SubReg). 507 // Loops and idempotent indices have TopoSig = ~0u. 508 Id.push_back(I->first->EnumValue); 509 Id.push_back(I->second->TopoSig); 510 511 // Don't add duplicate entries. 512 if (!I->second->SuperRegs.empty() && I->second->SuperRegs.back() == this) 513 continue; 514 I->second->SuperRegs.push_back(this); 515 } 516 TopoSig = RegBank.getTopoSig(Id); 517 } 518 519 void 520 CodeGenRegister::addSubRegsPreOrder(SetVector<const CodeGenRegister*> &OSet, 521 CodeGenRegBank &RegBank) const { 522 assert(SubRegsComplete && "Must precompute sub-registers"); 523 for (unsigned i = 0, e = ExplicitSubRegs.size(); i != e; ++i) { 524 CodeGenRegister *SR = ExplicitSubRegs[i]; 525 if (OSet.insert(SR)) 526 SR->addSubRegsPreOrder(OSet, RegBank); 527 } 528 // Add any secondary sub-registers that weren't part of the explicit tree. 529 for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end(); 530 I != E; ++I) 531 OSet.insert(I->second); 532 } 533 534 // Get the sum of this register's unit weights. 535 unsigned CodeGenRegister::getWeight(const CodeGenRegBank &RegBank) const { 536 unsigned Weight = 0; 537 for (RegUnitList::const_iterator I = RegUnits.begin(), E = RegUnits.end(); 538 I != E; ++I) { 539 Weight += RegBank.getRegUnit(*I).Weight; 540 } 541 return Weight; 542 } 543 544 //===----------------------------------------------------------------------===// 545 // RegisterTuples 546 //===----------------------------------------------------------------------===// 547 548 // A RegisterTuples def is used to generate pseudo-registers from lists of 549 // sub-registers. We provide a SetTheory expander class that returns the new 550 // registers. 551 namespace { 552 struct TupleExpander : SetTheory::Expander { 553 void expand(SetTheory &ST, Record *Def, SetTheory::RecSet &Elts) override { 554 std::vector<Record*> Indices = Def->getValueAsListOfDefs("SubRegIndices"); 555 unsigned Dim = Indices.size(); 556 ListInit *SubRegs = Def->getValueAsListInit("SubRegs"); 557 if (Dim != SubRegs->getSize()) 558 PrintFatalError(Def->getLoc(), "SubRegIndices and SubRegs size mismatch"); 559 if (Dim < 2) 560 PrintFatalError(Def->getLoc(), 561 "Tuples must have at least 2 sub-registers"); 562 563 // Evaluate the sub-register lists to be zipped. 564 unsigned Length = ~0u; 565 SmallVector<SetTheory::RecSet, 4> Lists(Dim); 566 for (unsigned i = 0; i != Dim; ++i) { 567 ST.evaluate(SubRegs->getElement(i), Lists[i], Def->getLoc()); 568 Length = std::min(Length, unsigned(Lists[i].size())); 569 } 570 571 if (Length == 0) 572 return; 573 574 // Precompute some types. 575 Record *RegisterCl = Def->getRecords().getClass("Register"); 576 RecTy *RegisterRecTy = RecordRecTy::get(RegisterCl); 577 StringInit *BlankName = StringInit::get(""); 578 579 // Zip them up. 580 for (unsigned n = 0; n != Length; ++n) { 581 std::string Name; 582 Record *Proto = Lists[0][n]; 583 std::vector<Init*> Tuple; 584 unsigned CostPerUse = 0; 585 for (unsigned i = 0; i != Dim; ++i) { 586 Record *Reg = Lists[i][n]; 587 if (i) Name += '_'; 588 Name += Reg->getName(); 589 Tuple.push_back(DefInit::get(Reg)); 590 CostPerUse = std::max(CostPerUse, 591 unsigned(Reg->getValueAsInt("CostPerUse"))); 592 } 593 594 // Create a new Record representing the synthesized register. This record 595 // is only for consumption by CodeGenRegister, it is not added to the 596 // RecordKeeper. 597 Record *NewReg = new Record(Name, Def->getLoc(), Def->getRecords()); 598 Elts.insert(NewReg); 599 600 // Copy Proto super-classes. 601 ArrayRef<Record *> Supers = Proto->getSuperClasses(); 602 ArrayRef<SMRange> Ranges = Proto->getSuperClassRanges(); 603 for (unsigned i = 0, e = Supers.size(); i != e; ++i) 604 NewReg->addSuperClass(Supers[i], Ranges[i]); 605 606 // Copy Proto fields. 607 for (unsigned i = 0, e = Proto->getValues().size(); i != e; ++i) { 608 RecordVal RV = Proto->getValues()[i]; 609 610 // Skip existing fields, like NAME. 611 if (NewReg->getValue(RV.getNameInit())) 612 continue; 613 614 StringRef Field = RV.getName(); 615 616 // Replace the sub-register list with Tuple. 617 if (Field == "SubRegs") 618 RV.setValue(ListInit::get(Tuple, RegisterRecTy)); 619 620 // Provide a blank AsmName. MC hacks are required anyway. 621 if (Field == "AsmName") 622 RV.setValue(BlankName); 623 624 // CostPerUse is aggregated from all Tuple members. 625 if (Field == "CostPerUse") 626 RV.setValue(IntInit::get(CostPerUse)); 627 628 // Composite registers are always covered by sub-registers. 629 if (Field == "CoveredBySubRegs") 630 RV.setValue(BitInit::get(true)); 631 632 // Copy fields from the RegisterTuples def. 633 if (Field == "SubRegIndices" || 634 Field == "CompositeIndices") { 635 NewReg->addValue(*Def->getValue(Field)); 636 continue; 637 } 638 639 // Some fields get their default uninitialized value. 640 if (Field == "DwarfNumbers" || 641 Field == "DwarfAlias" || 642 Field == "Aliases") { 643 if (const RecordVal *DefRV = RegisterCl->getValue(Field)) 644 NewReg->addValue(*DefRV); 645 continue; 646 } 647 648 // Everything else is copied from Proto. 649 NewReg->addValue(RV); 650 } 651 } 652 } 653 }; 654 } 655 656 //===----------------------------------------------------------------------===// 657 // CodeGenRegisterClass 658 //===----------------------------------------------------------------------===// 659 660 CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R) 661 : TheDef(R), 662 Name(R->getName()), 663 TopoSigs(RegBank.getNumTopoSigs()), 664 EnumValue(-1) { 665 // Rename anonymous register classes. 666 if (R->getName().size() > 9 && R->getName()[9] == '.') { 667 static unsigned AnonCounter = 0; 668 R->setName("AnonRegClass_" + utostr(AnonCounter)); 669 // MSVC2012 ICEs if AnonCounter++ is directly passed to utostr. 670 ++AnonCounter; 671 } 672 673 std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes"); 674 for (unsigned i = 0, e = TypeList.size(); i != e; ++i) { 675 Record *Type = TypeList[i]; 676 if (!Type->isSubClassOf("ValueType")) 677 PrintFatalError("RegTypes list member '" + Type->getName() + 678 "' does not derive from the ValueType class!"); 679 VTs.push_back(getValueType(Type)); 680 } 681 assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!"); 682 683 // Allocation order 0 is the full set. AltOrders provides others. 684 const SetTheory::RecVec *Elements = RegBank.getSets().expand(R); 685 ListInit *AltOrders = R->getValueAsListInit("AltOrders"); 686 Orders.resize(1 + AltOrders->size()); 687 688 // Default allocation order always contains all registers. 689 for (unsigned i = 0, e = Elements->size(); i != e; ++i) { 690 Orders[0].push_back((*Elements)[i]); 691 const CodeGenRegister *Reg = RegBank.getReg((*Elements)[i]); 692 Members.insert(Reg); 693 TopoSigs.set(Reg->getTopoSig()); 694 } 695 696 // Alternative allocation orders may be subsets. 697 SetTheory::RecSet Order; 698 for (unsigned i = 0, e = AltOrders->size(); i != e; ++i) { 699 RegBank.getSets().evaluate(AltOrders->getElement(i), Order, R->getLoc()); 700 Orders[1 + i].append(Order.begin(), Order.end()); 701 // Verify that all altorder members are regclass members. 702 while (!Order.empty()) { 703 CodeGenRegister *Reg = RegBank.getReg(Order.back()); 704 Order.pop_back(); 705 if (!contains(Reg)) 706 PrintFatalError(R->getLoc(), " AltOrder register " + Reg->getName() + 707 " is not a class member"); 708 } 709 } 710 711 // Allow targets to override the size in bits of the RegisterClass. 712 unsigned Size = R->getValueAsInt("Size"); 713 714 Namespace = R->getValueAsString("Namespace"); 715 SpillSize = Size ? Size : MVT(VTs[0]).getSizeInBits(); 716 SpillAlignment = R->getValueAsInt("Alignment"); 717 CopyCost = R->getValueAsInt("CopyCost"); 718 Allocatable = R->getValueAsBit("isAllocatable"); 719 AltOrderSelect = R->getValueAsString("AltOrderSelect"); 720 } 721 722 // Create an inferred register class that was missing from the .td files. 723 // Most properties will be inherited from the closest super-class after the 724 // class structure has been computed. 725 CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, 726 StringRef Name, Key Props) 727 : Members(*Props.Members), 728 TheDef(nullptr), 729 Name(Name), 730 TopoSigs(RegBank.getNumTopoSigs()), 731 EnumValue(-1), 732 SpillSize(Props.SpillSize), 733 SpillAlignment(Props.SpillAlignment), 734 CopyCost(0), 735 Allocatable(true) { 736 for (CodeGenRegister::Set::iterator I = Members.begin(), E = Members.end(); 737 I != E; ++I) 738 TopoSigs.set((*I)->getTopoSig()); 739 } 740 741 // Compute inherited propertied for a synthesized register class. 742 void CodeGenRegisterClass::inheritProperties(CodeGenRegBank &RegBank) { 743 assert(!getDef() && "Only synthesized classes can inherit properties"); 744 assert(!SuperClasses.empty() && "Synthesized class without super class"); 745 746 // The last super-class is the smallest one. 747 CodeGenRegisterClass &Super = *SuperClasses.back(); 748 749 // Most properties are copied directly. 750 // Exceptions are members, size, and alignment 751 Namespace = Super.Namespace; 752 VTs = Super.VTs; 753 CopyCost = Super.CopyCost; 754 Allocatable = Super.Allocatable; 755 AltOrderSelect = Super.AltOrderSelect; 756 757 // Copy all allocation orders, filter out foreign registers from the larger 758 // super-class. 759 Orders.resize(Super.Orders.size()); 760 for (unsigned i = 0, ie = Super.Orders.size(); i != ie; ++i) 761 for (unsigned j = 0, je = Super.Orders[i].size(); j != je; ++j) 762 if (contains(RegBank.getReg(Super.Orders[i][j]))) 763 Orders[i].push_back(Super.Orders[i][j]); 764 } 765 766 bool CodeGenRegisterClass::contains(const CodeGenRegister *Reg) const { 767 return Members.count(Reg); 768 } 769 770 namespace llvm { 771 raw_ostream &operator<<(raw_ostream &OS, const CodeGenRegisterClass::Key &K) { 772 OS << "{ S=" << K.SpillSize << ", A=" << K.SpillAlignment; 773 for (CodeGenRegister::Set::const_iterator I = K.Members->begin(), 774 E = K.Members->end(); I != E; ++I) 775 OS << ", " << (*I)->getName(); 776 return OS << " }"; 777 } 778 } 779 780 // This is a simple lexicographical order that can be used to search for sets. 781 // It is not the same as the topological order provided by TopoOrderRC. 782 bool CodeGenRegisterClass::Key:: 783 operator<(const CodeGenRegisterClass::Key &B) const { 784 assert(Members && B.Members); 785 return std::tie(*Members, SpillSize, SpillAlignment) < 786 std::tie(*B.Members, B.SpillSize, B.SpillAlignment); 787 } 788 789 // Returns true if RC is a strict subclass. 790 // RC is a sub-class of this class if it is a valid replacement for any 791 // instruction operand where a register of this classis required. It must 792 // satisfy these conditions: 793 // 794 // 1. All RC registers are also in this. 795 // 2. The RC spill size must not be smaller than our spill size. 796 // 3. RC spill alignment must be compatible with ours. 797 // 798 static bool testSubClass(const CodeGenRegisterClass *A, 799 const CodeGenRegisterClass *B) { 800 return A->SpillAlignment && B->SpillAlignment % A->SpillAlignment == 0 && 801 A->SpillSize <= B->SpillSize && 802 std::includes(A->getMembers().begin(), A->getMembers().end(), 803 B->getMembers().begin(), B->getMembers().end(), 804 CodeGenRegister::Less()); 805 } 806 807 /// Sorting predicate for register classes. This provides a topological 808 /// ordering that arranges all register classes before their sub-classes. 809 /// 810 /// Register classes with the same registers, spill size, and alignment form a 811 /// clique. They will be ordered alphabetically. 812 /// 813 static int TopoOrderRC(CodeGenRegisterClass *const *PA, 814 CodeGenRegisterClass *const *PB) { 815 const CodeGenRegisterClass *A = *PA; 816 const CodeGenRegisterClass *B = *PB; 817 if (A == B) 818 return 0; 819 820 // Order by ascending spill size. 821 if (A->SpillSize < B->SpillSize) 822 return -1; 823 if (A->SpillSize > B->SpillSize) 824 return 1; 825 826 // Order by ascending spill alignment. 827 if (A->SpillAlignment < B->SpillAlignment) 828 return -1; 829 if (A->SpillAlignment > B->SpillAlignment) 830 return 1; 831 832 // Order by descending set size. Note that the classes' allocation order may 833 // not have been computed yet. The Members set is always vaild. 834 if (A->getMembers().size() > B->getMembers().size()) 835 return -1; 836 if (A->getMembers().size() < B->getMembers().size()) 837 return 1; 838 839 // Finally order by name as a tie breaker. 840 return StringRef(A->getName()).compare(B->getName()); 841 } 842 843 std::string CodeGenRegisterClass::getQualifiedName() const { 844 if (Namespace.empty()) 845 return getName(); 846 else 847 return Namespace + "::" + getName(); 848 } 849 850 // Compute sub-classes of all register classes. 851 // Assume the classes are ordered topologically. 852 void CodeGenRegisterClass::computeSubClasses(CodeGenRegBank &RegBank) { 853 ArrayRef<CodeGenRegisterClass*> RegClasses = RegBank.getRegClasses(); 854 855 // Visit backwards so sub-classes are seen first. 856 for (unsigned rci = RegClasses.size(); rci; --rci) { 857 CodeGenRegisterClass &RC = *RegClasses[rci - 1]; 858 RC.SubClasses.resize(RegClasses.size()); 859 RC.SubClasses.set(RC.EnumValue); 860 861 // Normally, all subclasses have IDs >= rci, unless RC is part of a clique. 862 for (unsigned s = rci; s != RegClasses.size(); ++s) { 863 if (RC.SubClasses.test(s)) 864 continue; 865 CodeGenRegisterClass *SubRC = RegClasses[s]; 866 if (!testSubClass(&RC, SubRC)) 867 continue; 868 // SubRC is a sub-class. Grap all its sub-classes so we won't have to 869 // check them again. 870 RC.SubClasses |= SubRC->SubClasses; 871 } 872 873 // Sweep up missed clique members. They will be immediately preceding RC. 874 for (unsigned s = rci - 1; s && testSubClass(&RC, RegClasses[s - 1]); --s) 875 RC.SubClasses.set(s - 1); 876 } 877 878 // Compute the SuperClasses lists from the SubClasses vectors. 879 for (unsigned rci = 0; rci != RegClasses.size(); ++rci) { 880 const BitVector &SC = RegClasses[rci]->getSubClasses(); 881 for (int s = SC.find_first(); s >= 0; s = SC.find_next(s)) { 882 if (unsigned(s) == rci) 883 continue; 884 RegClasses[s]->SuperClasses.push_back(RegClasses[rci]); 885 } 886 } 887 888 // With the class hierarchy in place, let synthesized register classes inherit 889 // properties from their closest super-class. The iteration order here can 890 // propagate properties down multiple levels. 891 for (unsigned rci = 0; rci != RegClasses.size(); ++rci) 892 if (!RegClasses[rci]->getDef()) 893 RegClasses[rci]->inheritProperties(RegBank); 894 } 895 896 void 897 CodeGenRegisterClass::getSuperRegClasses(CodeGenSubRegIndex *SubIdx, 898 BitVector &Out) const { 899 DenseMap<CodeGenSubRegIndex*, 900 SmallPtrSet<CodeGenRegisterClass*, 8> >::const_iterator 901 FindI = SuperRegClasses.find(SubIdx); 902 if (FindI == SuperRegClasses.end()) 903 return; 904 for (SmallPtrSet<CodeGenRegisterClass*, 8>::const_iterator I = 905 FindI->second.begin(), E = FindI->second.end(); I != E; ++I) 906 Out.set((*I)->EnumValue); 907 } 908 909 // Populate a unique sorted list of units from a register set. 910 void CodeGenRegisterClass::buildRegUnitSet( 911 std::vector<unsigned> &RegUnits) const { 912 std::vector<unsigned> TmpUnits; 913 for (RegUnitIterator UnitI(Members); UnitI.isValid(); ++UnitI) 914 TmpUnits.push_back(*UnitI); 915 std::sort(TmpUnits.begin(), TmpUnits.end()); 916 std::unique_copy(TmpUnits.begin(), TmpUnits.end(), 917 std::back_inserter(RegUnits)); 918 } 919 920 //===----------------------------------------------------------------------===// 921 // CodeGenRegBank 922 //===----------------------------------------------------------------------===// 923 924 CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records) { 925 // Configure register Sets to understand register classes and tuples. 926 Sets.addFieldExpander("RegisterClass", "MemberList"); 927 Sets.addFieldExpander("CalleeSavedRegs", "SaveList"); 928 Sets.addExpander("RegisterTuples", new TupleExpander()); 929 930 // Read in the user-defined (named) sub-register indices. 931 // More indices will be synthesized later. 932 std::vector<Record*> SRIs = Records.getAllDerivedDefinitions("SubRegIndex"); 933 std::sort(SRIs.begin(), SRIs.end(), LessRecord()); 934 for (unsigned i = 0, e = SRIs.size(); i != e; ++i) 935 getSubRegIdx(SRIs[i]); 936 // Build composite maps from ComposedOf fields. 937 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) 938 SubRegIndices[i]->updateComponents(*this); 939 940 // Read in the register definitions. 941 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register"); 942 std::sort(Regs.begin(), Regs.end(), LessRecordRegister()); 943 Registers.reserve(Regs.size()); 944 // Assign the enumeration values. 945 for (unsigned i = 0, e = Regs.size(); i != e; ++i) 946 getReg(Regs[i]); 947 948 // Expand tuples and number the new registers. 949 std::vector<Record*> Tups = 950 Records.getAllDerivedDefinitions("RegisterTuples"); 951 952 std::vector<Record*> TupRegsCopy; 953 for (unsigned i = 0, e = Tups.size(); i != e; ++i) { 954 const std::vector<Record*> *TupRegs = Sets.expand(Tups[i]); 955 TupRegsCopy.reserve(TupRegs->size()); 956 TupRegsCopy.assign(TupRegs->begin(), TupRegs->end()); 957 std::sort(TupRegsCopy.begin(), TupRegsCopy.end(), LessRecordRegister()); 958 for (unsigned j = 0, je = TupRegsCopy.size(); j != je; ++j) 959 getReg((TupRegsCopy)[j]); 960 TupRegsCopy.clear(); 961 } 962 963 // Now all the registers are known. Build the object graph of explicit 964 // register-register references. 965 for (unsigned i = 0, e = Registers.size(); i != e; ++i) 966 Registers[i]->buildObjectGraph(*this); 967 968 // Compute register name map. 969 for (unsigned i = 0, e = Registers.size(); i != e; ++i) 970 RegistersByName.GetOrCreateValue( 971 Registers[i]->TheDef->getValueAsString("AsmName"), 972 Registers[i]); 973 974 // Precompute all sub-register maps. 975 // This will create Composite entries for all inferred sub-register indices. 976 for (unsigned i = 0, e = Registers.size(); i != e; ++i) 977 Registers[i]->computeSubRegs(*this); 978 979 // Infer even more sub-registers by combining leading super-registers. 980 for (unsigned i = 0, e = Registers.size(); i != e; ++i) 981 if (Registers[i]->CoveredBySubRegs) 982 Registers[i]->computeSecondarySubRegs(*this); 983 984 // After the sub-register graph is complete, compute the topologically 985 // ordered SuperRegs list. 986 for (unsigned i = 0, e = Registers.size(); i != e; ++i) 987 Registers[i]->computeSuperRegs(*this); 988 989 // Native register units are associated with a leaf register. They've all been 990 // discovered now. 991 NumNativeRegUnits = RegUnits.size(); 992 993 // Read in register class definitions. 994 std::vector<Record*> RCs = Records.getAllDerivedDefinitions("RegisterClass"); 995 if (RCs.empty()) 996 PrintFatalError("No 'RegisterClass' subclasses defined!"); 997 998 // Allocate user-defined register classes. 999 RegClasses.reserve(RCs.size()); 1000 for (unsigned i = 0, e = RCs.size(); i != e; ++i) 1001 addToMaps(new CodeGenRegisterClass(*this, RCs[i])); 1002 1003 // Infer missing classes to create a full algebra. 1004 computeInferredRegisterClasses(); 1005 1006 // Order register classes topologically and assign enum values. 1007 array_pod_sort(RegClasses.begin(), RegClasses.end(), TopoOrderRC); 1008 for (unsigned i = 0, e = RegClasses.size(); i != e; ++i) 1009 RegClasses[i]->EnumValue = i; 1010 CodeGenRegisterClass::computeSubClasses(*this); 1011 } 1012 1013 // Create a synthetic CodeGenSubRegIndex without a corresponding Record. 1014 CodeGenSubRegIndex* 1015 CodeGenRegBank::createSubRegIndex(StringRef Name, StringRef Namespace) { 1016 CodeGenSubRegIndex *Idx = new CodeGenSubRegIndex(Name, Namespace, 1017 SubRegIndices.size() + 1); 1018 SubRegIndices.push_back(Idx); 1019 return Idx; 1020 } 1021 1022 CodeGenSubRegIndex *CodeGenRegBank::getSubRegIdx(Record *Def) { 1023 CodeGenSubRegIndex *&Idx = Def2SubRegIdx[Def]; 1024 if (Idx) 1025 return Idx; 1026 Idx = new CodeGenSubRegIndex(Def, SubRegIndices.size() + 1); 1027 SubRegIndices.push_back(Idx); 1028 return Idx; 1029 } 1030 1031 CodeGenRegister *CodeGenRegBank::getReg(Record *Def) { 1032 CodeGenRegister *&Reg = Def2Reg[Def]; 1033 if (Reg) 1034 return Reg; 1035 Reg = new CodeGenRegister(Def, Registers.size() + 1); 1036 Registers.push_back(Reg); 1037 return Reg; 1038 } 1039 1040 void CodeGenRegBank::addToMaps(CodeGenRegisterClass *RC) { 1041 RegClasses.push_back(RC); 1042 1043 if (Record *Def = RC->getDef()) 1044 Def2RC.insert(std::make_pair(Def, RC)); 1045 1046 // Duplicate classes are rejected by insert(). 1047 // That's OK, we only care about the properties handled by CGRC::Key. 1048 CodeGenRegisterClass::Key K(*RC); 1049 Key2RC.insert(std::make_pair(K, RC)); 1050 } 1051 1052 // Create a synthetic sub-class if it is missing. 1053 CodeGenRegisterClass* 1054 CodeGenRegBank::getOrCreateSubClass(const CodeGenRegisterClass *RC, 1055 const CodeGenRegister::Set *Members, 1056 StringRef Name) { 1057 // Synthetic sub-class has the same size and alignment as RC. 1058 CodeGenRegisterClass::Key K(Members, RC->SpillSize, RC->SpillAlignment); 1059 RCKeyMap::const_iterator FoundI = Key2RC.find(K); 1060 if (FoundI != Key2RC.end()) 1061 return FoundI->second; 1062 1063 // Sub-class doesn't exist, create a new one. 1064 CodeGenRegisterClass *NewRC = new CodeGenRegisterClass(*this, Name, K); 1065 addToMaps(NewRC); 1066 return NewRC; 1067 } 1068 1069 CodeGenRegisterClass *CodeGenRegBank::getRegClass(Record *Def) { 1070 if (CodeGenRegisterClass *RC = Def2RC[Def]) 1071 return RC; 1072 1073 PrintFatalError(Def->getLoc(), "Not a known RegisterClass!"); 1074 } 1075 1076 CodeGenSubRegIndex* 1077 CodeGenRegBank::getCompositeSubRegIndex(CodeGenSubRegIndex *A, 1078 CodeGenSubRegIndex *B) { 1079 // Look for an existing entry. 1080 CodeGenSubRegIndex *Comp = A->compose(B); 1081 if (Comp) 1082 return Comp; 1083 1084 // None exists, synthesize one. 1085 std::string Name = A->getName() + "_then_" + B->getName(); 1086 Comp = createSubRegIndex(Name, A->getNamespace()); 1087 A->addComposite(B, Comp); 1088 return Comp; 1089 } 1090 1091 CodeGenSubRegIndex *CodeGenRegBank:: 1092 getConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex *, 8> &Parts) { 1093 assert(Parts.size() > 1 && "Need two parts to concatenate"); 1094 1095 // Look for an existing entry. 1096 CodeGenSubRegIndex *&Idx = ConcatIdx[Parts]; 1097 if (Idx) 1098 return Idx; 1099 1100 // None exists, synthesize one. 1101 std::string Name = Parts.front()->getName(); 1102 // Determine whether all parts are contiguous. 1103 bool isContinuous = true; 1104 unsigned Size = Parts.front()->Size; 1105 unsigned LastOffset = Parts.front()->Offset; 1106 unsigned LastSize = Parts.front()->Size; 1107 for (unsigned i = 1, e = Parts.size(); i != e; ++i) { 1108 Name += '_'; 1109 Name += Parts[i]->getName(); 1110 Size += Parts[i]->Size; 1111 if (Parts[i]->Offset != (LastOffset + LastSize)) 1112 isContinuous = false; 1113 LastOffset = Parts[i]->Offset; 1114 LastSize = Parts[i]->Size; 1115 } 1116 Idx = createSubRegIndex(Name, Parts.front()->getNamespace()); 1117 Idx->Size = Size; 1118 Idx->Offset = isContinuous ? Parts.front()->Offset : -1; 1119 return Idx; 1120 } 1121 1122 void CodeGenRegBank::computeComposites() { 1123 // Keep track of TopoSigs visited. We only need to visit each TopoSig once, 1124 // and many registers will share TopoSigs on regular architectures. 1125 BitVector TopoSigs(getNumTopoSigs()); 1126 1127 for (unsigned i = 0, e = Registers.size(); i != e; ++i) { 1128 CodeGenRegister *Reg1 = Registers[i]; 1129 1130 // Skip identical subreg structures already processed. 1131 if (TopoSigs.test(Reg1->getTopoSig())) 1132 continue; 1133 TopoSigs.set(Reg1->getTopoSig()); 1134 1135 const CodeGenRegister::SubRegMap &SRM1 = Reg1->getSubRegs(); 1136 for (CodeGenRegister::SubRegMap::const_iterator i1 = SRM1.begin(), 1137 e1 = SRM1.end(); i1 != e1; ++i1) { 1138 CodeGenSubRegIndex *Idx1 = i1->first; 1139 CodeGenRegister *Reg2 = i1->second; 1140 // Ignore identity compositions. 1141 if (Reg1 == Reg2) 1142 continue; 1143 const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs(); 1144 // Try composing Idx1 with another SubRegIndex. 1145 for (CodeGenRegister::SubRegMap::const_iterator i2 = SRM2.begin(), 1146 e2 = SRM2.end(); i2 != e2; ++i2) { 1147 CodeGenSubRegIndex *Idx2 = i2->first; 1148 CodeGenRegister *Reg3 = i2->second; 1149 // Ignore identity compositions. 1150 if (Reg2 == Reg3) 1151 continue; 1152 // OK Reg1:IdxPair == Reg3. Find the index with Reg:Idx == Reg3. 1153 CodeGenSubRegIndex *Idx3 = Reg1->getSubRegIndex(Reg3); 1154 assert(Idx3 && "Sub-register doesn't have an index"); 1155 1156 // Conflicting composition? Emit a warning but allow it. 1157 if (CodeGenSubRegIndex *Prev = Idx1->addComposite(Idx2, Idx3)) 1158 PrintWarning(Twine("SubRegIndex ") + Idx1->getQualifiedName() + 1159 " and " + Idx2->getQualifiedName() + 1160 " compose ambiguously as " + Prev->getQualifiedName() + 1161 " or " + Idx3->getQualifiedName()); 1162 } 1163 } 1164 } 1165 } 1166 1167 // Compute lane masks. This is similar to register units, but at the 1168 // sub-register index level. Each bit in the lane mask is like a register unit 1169 // class, and two lane masks will have a bit in common if two sub-register 1170 // indices overlap in some register. 1171 // 1172 // Conservatively share a lane mask bit if two sub-register indices overlap in 1173 // some registers, but not in others. That shouldn't happen a lot. 1174 void CodeGenRegBank::computeSubRegIndexLaneMasks() { 1175 // First assign individual bits to all the leaf indices. 1176 unsigned Bit = 0; 1177 // Determine mask of lanes that cover their registers. 1178 CoveringLanes = ~0u; 1179 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) { 1180 CodeGenSubRegIndex *Idx = SubRegIndices[i]; 1181 if (Idx->getComposites().empty()) { 1182 Idx->LaneMask = 1u << Bit; 1183 // Share bit 31 in the unlikely case there are more than 32 leafs. 1184 // 1185 // Sharing bits is harmless; it allows graceful degradation in targets 1186 // with more than 32 vector lanes. They simply get a limited resolution 1187 // view of lanes beyond the 32nd. 1188 // 1189 // See also the comment for getSubRegIndexLaneMask(). 1190 if (Bit < 31) 1191 ++Bit; 1192 else 1193 // Once bit 31 is shared among multiple leafs, the 'lane' it represents 1194 // is no longer covering its registers. 1195 CoveringLanes &= ~(1u << Bit); 1196 } else { 1197 Idx->LaneMask = 0; 1198 } 1199 } 1200 1201 // FIXME: What if ad-hoc aliasing introduces overlaps that aren't represented 1202 // by the sub-register graph? This doesn't occur in any known targets. 1203 1204 // Inherit lanes from composites. 1205 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) { 1206 unsigned Mask = SubRegIndices[i]->computeLaneMask(); 1207 // If some super-registers without CoveredBySubRegs use this index, we can 1208 // no longer assume that the lanes are covering their registers. 1209 if (!SubRegIndices[i]->AllSuperRegsCovered) 1210 CoveringLanes &= ~Mask; 1211 } 1212 } 1213 1214 namespace { 1215 // UberRegSet is a helper class for computeRegUnitWeights. Each UberRegSet is 1216 // the transitive closure of the union of overlapping register 1217 // classes. Together, the UberRegSets form a partition of the registers. If we 1218 // consider overlapping register classes to be connected, then each UberRegSet 1219 // is a set of connected components. 1220 // 1221 // An UberRegSet will likely be a horizontal slice of register names of 1222 // the same width. Nontrivial subregisters should then be in a separate 1223 // UberRegSet. But this property isn't required for valid computation of 1224 // register unit weights. 1225 // 1226 // A Weight field caches the max per-register unit weight in each UberRegSet. 1227 // 1228 // A set of SingularDeterminants flags single units of some register in this set 1229 // for which the unit weight equals the set weight. These units should not have 1230 // their weight increased. 1231 struct UberRegSet { 1232 CodeGenRegister::Set Regs; 1233 unsigned Weight; 1234 CodeGenRegister::RegUnitList SingularDeterminants; 1235 1236 UberRegSet(): Weight(0) {} 1237 }; 1238 } // namespace 1239 1240 // Partition registers into UberRegSets, where each set is the transitive 1241 // closure of the union of overlapping register classes. 1242 // 1243 // UberRegSets[0] is a special non-allocatable set. 1244 static void computeUberSets(std::vector<UberRegSet> &UberSets, 1245 std::vector<UberRegSet*> &RegSets, 1246 CodeGenRegBank &RegBank) { 1247 1248 const std::vector<CodeGenRegister*> &Registers = RegBank.getRegisters(); 1249 1250 // The Register EnumValue is one greater than its index into Registers. 1251 assert(Registers.size() == Registers[Registers.size()-1]->EnumValue && 1252 "register enum value mismatch"); 1253 1254 // For simplicitly make the SetID the same as EnumValue. 1255 IntEqClasses UberSetIDs(Registers.size()+1); 1256 std::set<unsigned> AllocatableRegs; 1257 for (unsigned i = 0, e = RegBank.getRegClasses().size(); i != e; ++i) { 1258 1259 CodeGenRegisterClass *RegClass = RegBank.getRegClasses()[i]; 1260 if (!RegClass->Allocatable) 1261 continue; 1262 1263 const CodeGenRegister::Set &Regs = RegClass->getMembers(); 1264 if (Regs.empty()) 1265 continue; 1266 1267 unsigned USetID = UberSetIDs.findLeader((*Regs.begin())->EnumValue); 1268 assert(USetID && "register number 0 is invalid"); 1269 1270 AllocatableRegs.insert((*Regs.begin())->EnumValue); 1271 for (CodeGenRegister::Set::const_iterator I = std::next(Regs.begin()), 1272 E = Regs.end(); I != E; ++I) { 1273 AllocatableRegs.insert((*I)->EnumValue); 1274 UberSetIDs.join(USetID, (*I)->EnumValue); 1275 } 1276 } 1277 // Combine non-allocatable regs. 1278 for (unsigned i = 0, e = Registers.size(); i != e; ++i) { 1279 unsigned RegNum = Registers[i]->EnumValue; 1280 if (AllocatableRegs.count(RegNum)) 1281 continue; 1282 1283 UberSetIDs.join(0, RegNum); 1284 } 1285 UberSetIDs.compress(); 1286 1287 // Make the first UberSet a special unallocatable set. 1288 unsigned ZeroID = UberSetIDs[0]; 1289 1290 // Insert Registers into the UberSets formed by union-find. 1291 // Do not resize after this. 1292 UberSets.resize(UberSetIDs.getNumClasses()); 1293 for (unsigned i = 0, e = Registers.size(); i != e; ++i) { 1294 const CodeGenRegister *Reg = Registers[i]; 1295 unsigned USetID = UberSetIDs[Reg->EnumValue]; 1296 if (!USetID) 1297 USetID = ZeroID; 1298 else if (USetID == ZeroID) 1299 USetID = 0; 1300 1301 UberRegSet *USet = &UberSets[USetID]; 1302 USet->Regs.insert(Reg); 1303 RegSets[i] = USet; 1304 } 1305 } 1306 1307 // Recompute each UberSet weight after changing unit weights. 1308 static void computeUberWeights(std::vector<UberRegSet> &UberSets, 1309 CodeGenRegBank &RegBank) { 1310 // Skip the first unallocatable set. 1311 for (std::vector<UberRegSet>::iterator I = std::next(UberSets.begin()), 1312 E = UberSets.end(); I != E; ++I) { 1313 1314 // Initialize all unit weights in this set, and remember the max units/reg. 1315 const CodeGenRegister *Reg = nullptr; 1316 unsigned MaxWeight = 0, Weight = 0; 1317 for (RegUnitIterator UnitI(I->Regs); UnitI.isValid(); ++UnitI) { 1318 if (Reg != UnitI.getReg()) { 1319 if (Weight > MaxWeight) 1320 MaxWeight = Weight; 1321 Reg = UnitI.getReg(); 1322 Weight = 0; 1323 } 1324 unsigned UWeight = RegBank.getRegUnit(*UnitI).Weight; 1325 if (!UWeight) { 1326 UWeight = 1; 1327 RegBank.increaseRegUnitWeight(*UnitI, UWeight); 1328 } 1329 Weight += UWeight; 1330 } 1331 if (Weight > MaxWeight) 1332 MaxWeight = Weight; 1333 if (I->Weight != MaxWeight) { 1334 DEBUG( 1335 dbgs() << "UberSet " << I - UberSets.begin() << " Weight " << MaxWeight; 1336 for (CodeGenRegister::Set::iterator 1337 UnitI = I->Regs.begin(), UnitE = I->Regs.end(); 1338 UnitI != UnitE; ++UnitI) { 1339 dbgs() << " " << (*UnitI)->getName(); 1340 } 1341 dbgs() << "\n"); 1342 // Update the set weight. 1343 I->Weight = MaxWeight; 1344 } 1345 1346 // Find singular determinants. 1347 for (CodeGenRegister::Set::iterator RegI = I->Regs.begin(), 1348 RegE = I->Regs.end(); RegI != RegE; ++RegI) { 1349 if ((*RegI)->getRegUnits().size() == 1 1350 && (*RegI)->getWeight(RegBank) == I->Weight) 1351 mergeRegUnits(I->SingularDeterminants, (*RegI)->getRegUnits()); 1352 } 1353 } 1354 } 1355 1356 // normalizeWeight is a computeRegUnitWeights helper that adjusts the weight of 1357 // a register and its subregisters so that they have the same weight as their 1358 // UberSet. Self-recursion processes the subregister tree in postorder so 1359 // subregisters are normalized first. 1360 // 1361 // Side effects: 1362 // - creates new adopted register units 1363 // - causes superregisters to inherit adopted units 1364 // - increases the weight of "singular" units 1365 // - induces recomputation of UberWeights. 1366 static bool normalizeWeight(CodeGenRegister *Reg, 1367 std::vector<UberRegSet> &UberSets, 1368 std::vector<UberRegSet*> &RegSets, 1369 std::set<unsigned> &NormalRegs, 1370 CodeGenRegister::RegUnitList &NormalUnits, 1371 CodeGenRegBank &RegBank) { 1372 bool Changed = false; 1373 if (!NormalRegs.insert(Reg->EnumValue).second) 1374 return Changed; 1375 1376 const CodeGenRegister::SubRegMap &SRM = Reg->getSubRegs(); 1377 for (CodeGenRegister::SubRegMap::const_iterator SRI = SRM.begin(), 1378 SRE = SRM.end(); SRI != SRE; ++SRI) { 1379 if (SRI->second == Reg) 1380 continue; // self-cycles happen 1381 1382 Changed |= normalizeWeight(SRI->second, UberSets, RegSets, 1383 NormalRegs, NormalUnits, RegBank); 1384 } 1385 // Postorder register normalization. 1386 1387 // Inherit register units newly adopted by subregisters. 1388 if (Reg->inheritRegUnits(RegBank)) 1389 computeUberWeights(UberSets, RegBank); 1390 1391 // Check if this register is too skinny for its UberRegSet. 1392 UberRegSet *UberSet = RegSets[RegBank.getRegIndex(Reg)]; 1393 1394 unsigned RegWeight = Reg->getWeight(RegBank); 1395 if (UberSet->Weight > RegWeight) { 1396 // A register unit's weight can be adjusted only if it is the singular unit 1397 // for this register, has not been used to normalize a subregister's set, 1398 // and has not already been used to singularly determine this UberRegSet. 1399 unsigned AdjustUnit = Reg->getRegUnits().front(); 1400 if (Reg->getRegUnits().size() != 1 1401 || hasRegUnit(NormalUnits, AdjustUnit) 1402 || hasRegUnit(UberSet->SingularDeterminants, AdjustUnit)) { 1403 // We don't have an adjustable unit, so adopt a new one. 1404 AdjustUnit = RegBank.newRegUnit(UberSet->Weight - RegWeight); 1405 Reg->adoptRegUnit(AdjustUnit); 1406 // Adopting a unit does not immediately require recomputing set weights. 1407 } 1408 else { 1409 // Adjust the existing single unit. 1410 RegBank.increaseRegUnitWeight(AdjustUnit, UberSet->Weight - RegWeight); 1411 // The unit may be shared among sets and registers within this set. 1412 computeUberWeights(UberSets, RegBank); 1413 } 1414 Changed = true; 1415 } 1416 1417 // Mark these units normalized so superregisters can't change their weights. 1418 mergeRegUnits(NormalUnits, Reg->getRegUnits()); 1419 1420 return Changed; 1421 } 1422 1423 // Compute a weight for each register unit created during getSubRegs. 1424 // 1425 // The goal is that two registers in the same class will have the same weight, 1426 // where each register's weight is defined as sum of its units' weights. 1427 void CodeGenRegBank::computeRegUnitWeights() { 1428 std::vector<UberRegSet> UberSets; 1429 std::vector<UberRegSet*> RegSets(Registers.size()); 1430 computeUberSets(UberSets, RegSets, *this); 1431 // UberSets and RegSets are now immutable. 1432 1433 computeUberWeights(UberSets, *this); 1434 1435 // Iterate over each Register, normalizing the unit weights until reaching 1436 // a fix point. 1437 unsigned NumIters = 0; 1438 for (bool Changed = true; Changed; ++NumIters) { 1439 assert(NumIters <= NumNativeRegUnits && "Runaway register unit weights"); 1440 Changed = false; 1441 for (unsigned i = 0, e = Registers.size(); i != e; ++i) { 1442 CodeGenRegister::RegUnitList NormalUnits; 1443 std::set<unsigned> NormalRegs; 1444 Changed |= normalizeWeight(Registers[i], UberSets, RegSets, 1445 NormalRegs, NormalUnits, *this); 1446 } 1447 } 1448 } 1449 1450 // Find a set in UniqueSets with the same elements as Set. 1451 // Return an iterator into UniqueSets. 1452 static std::vector<RegUnitSet>::const_iterator 1453 findRegUnitSet(const std::vector<RegUnitSet> &UniqueSets, 1454 const RegUnitSet &Set) { 1455 std::vector<RegUnitSet>::const_iterator 1456 I = UniqueSets.begin(), E = UniqueSets.end(); 1457 for(;I != E; ++I) { 1458 if (I->Units == Set.Units) 1459 break; 1460 } 1461 return I; 1462 } 1463 1464 // Return true if the RUSubSet is a subset of RUSuperSet. 1465 static bool isRegUnitSubSet(const std::vector<unsigned> &RUSubSet, 1466 const std::vector<unsigned> &RUSuperSet) { 1467 return std::includes(RUSuperSet.begin(), RUSuperSet.end(), 1468 RUSubSet.begin(), RUSubSet.end()); 1469 } 1470 1471 /// Iteratively prune unit sets. Prune subsets that are close to the superset, 1472 /// but with one or two registers removed. We occasionally have registers like 1473 /// APSR and PC thrown in with the general registers. We also see many 1474 /// special-purpose register subsets, such as tail-call and Thumb 1475 /// encodings. Generating all possible overlapping sets is combinatorial and 1476 /// overkill for modeling pressure. Ideally we could fix this statically in 1477 /// tablegen by (1) having the target define register classes that only include 1478 /// the allocatable registers and marking other classes as non-allocatable and 1479 /// (2) having a way to mark special purpose classes as "don't-care" classes for 1480 /// the purpose of pressure. However, we make an attempt to handle targets that 1481 /// are not nicely defined by merging nearly identical register unit sets 1482 /// statically. This generates smaller tables. Then, dynamically, we adjust the 1483 /// set limit by filtering the reserved registers. 1484 /// 1485 /// Merge sets only if the units have the same weight. For example, on ARM, 1486 /// Q-tuples with ssub index 0 include all S regs but also include D16+. We 1487 /// should not expand the S set to include D regs. 1488 void CodeGenRegBank::pruneUnitSets() { 1489 assert(RegClassUnitSets.empty() && "this invalidates RegClassUnitSets"); 1490 1491 // Form an equivalence class of UnitSets with no significant difference. 1492 std::vector<unsigned> SuperSetIDs; 1493 for (unsigned SubIdx = 0, EndIdx = RegUnitSets.size(); 1494 SubIdx != EndIdx; ++SubIdx) { 1495 const RegUnitSet &SubSet = RegUnitSets[SubIdx]; 1496 unsigned SuperIdx = 0; 1497 for (; SuperIdx != EndIdx; ++SuperIdx) { 1498 if (SuperIdx == SubIdx) 1499 continue; 1500 1501 unsigned UnitWeight = RegUnits[SubSet.Units[0]].Weight; 1502 const RegUnitSet &SuperSet = RegUnitSets[SuperIdx]; 1503 if (isRegUnitSubSet(SubSet.Units, SuperSet.Units) 1504 && (SubSet.Units.size() + 3 > SuperSet.Units.size()) 1505 && UnitWeight == RegUnits[SuperSet.Units[0]].Weight 1506 && UnitWeight == RegUnits[SuperSet.Units.back()].Weight) { 1507 DEBUG(dbgs() << "UnitSet " << SubIdx << " subsumed by " << SuperIdx 1508 << "\n"); 1509 break; 1510 } 1511 } 1512 if (SuperIdx == EndIdx) 1513 SuperSetIDs.push_back(SubIdx); 1514 } 1515 // Populate PrunedUnitSets with each equivalence class's superset. 1516 std::vector<RegUnitSet> PrunedUnitSets(SuperSetIDs.size()); 1517 for (unsigned i = 0, e = SuperSetIDs.size(); i != e; ++i) { 1518 unsigned SuperIdx = SuperSetIDs[i]; 1519 PrunedUnitSets[i].Name = RegUnitSets[SuperIdx].Name; 1520 PrunedUnitSets[i].Units.swap(RegUnitSets[SuperIdx].Units); 1521 } 1522 RegUnitSets.swap(PrunedUnitSets); 1523 } 1524 1525 // Create a RegUnitSet for each RegClass that contains all units in the class 1526 // including adopted units that are necessary to model register pressure. Then 1527 // iteratively compute RegUnitSets such that the union of any two overlapping 1528 // RegUnitSets is repreresented. 1529 // 1530 // RegisterInfoEmitter will map each RegClass to its RegUnitClass and any 1531 // RegUnitSet that is a superset of that RegUnitClass. 1532 void CodeGenRegBank::computeRegUnitSets() { 1533 assert(RegUnitSets.empty() && "dirty RegUnitSets"); 1534 1535 // Compute a unique RegUnitSet for each RegClass. 1536 const ArrayRef<CodeGenRegisterClass*> &RegClasses = getRegClasses(); 1537 unsigned NumRegClasses = RegClasses.size(); 1538 for (unsigned RCIdx = 0, RCEnd = NumRegClasses; RCIdx != RCEnd; ++RCIdx) { 1539 if (!RegClasses[RCIdx]->Allocatable) 1540 continue; 1541 1542 // Speculatively grow the RegUnitSets to hold the new set. 1543 RegUnitSets.resize(RegUnitSets.size() + 1); 1544 RegUnitSets.back().Name = RegClasses[RCIdx]->getName(); 1545 1546 // Compute a sorted list of units in this class. 1547 RegClasses[RCIdx]->buildRegUnitSet(RegUnitSets.back().Units); 1548 1549 // Find an existing RegUnitSet. 1550 std::vector<RegUnitSet>::const_iterator SetI = 1551 findRegUnitSet(RegUnitSets, RegUnitSets.back()); 1552 if (SetI != std::prev(RegUnitSets.end())) 1553 RegUnitSets.pop_back(); 1554 } 1555 1556 DEBUG(dbgs() << "\nBefore pruning:\n"; 1557 for (unsigned USIdx = 0, USEnd = RegUnitSets.size(); 1558 USIdx < USEnd; ++USIdx) { 1559 dbgs() << "UnitSet " << USIdx << " " << RegUnitSets[USIdx].Name 1560 << ":"; 1561 ArrayRef<unsigned> Units = RegUnitSets[USIdx].Units; 1562 for (unsigned i = 0, e = Units.size(); i < e; ++i) 1563 dbgs() << " " << RegUnits[Units[i]].Roots[0]->getName(); 1564 dbgs() << "\n"; 1565 }); 1566 1567 // Iteratively prune unit sets. 1568 pruneUnitSets(); 1569 1570 DEBUG(dbgs() << "\nBefore union:\n"; 1571 for (unsigned USIdx = 0, USEnd = RegUnitSets.size(); 1572 USIdx < USEnd; ++USIdx) { 1573 dbgs() << "UnitSet " << USIdx << " " << RegUnitSets[USIdx].Name 1574 << ":"; 1575 ArrayRef<unsigned> Units = RegUnitSets[USIdx].Units; 1576 for (unsigned i = 0, e = Units.size(); i < e; ++i) 1577 dbgs() << " " << RegUnits[Units[i]].Roots[0]->getName(); 1578 dbgs() << "\n"; 1579 } 1580 dbgs() << "\nUnion sets:\n"); 1581 1582 // Iterate over all unit sets, including new ones added by this loop. 1583 unsigned NumRegUnitSubSets = RegUnitSets.size(); 1584 for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx) { 1585 // In theory, this is combinatorial. In practice, it needs to be bounded 1586 // by a small number of sets for regpressure to be efficient. 1587 // If the assert is hit, we need to implement pruning. 1588 assert(Idx < (2*NumRegUnitSubSets) && "runaway unit set inference"); 1589 1590 // Compare new sets with all original classes. 1591 for (unsigned SearchIdx = (Idx >= NumRegUnitSubSets) ? 0 : Idx+1; 1592 SearchIdx != EndIdx; ++SearchIdx) { 1593 std::set<unsigned> Intersection; 1594 std::set_intersection(RegUnitSets[Idx].Units.begin(), 1595 RegUnitSets[Idx].Units.end(), 1596 RegUnitSets[SearchIdx].Units.begin(), 1597 RegUnitSets[SearchIdx].Units.end(), 1598 std::inserter(Intersection, Intersection.begin())); 1599 if (Intersection.empty()) 1600 continue; 1601 1602 // Speculatively grow the RegUnitSets to hold the new set. 1603 RegUnitSets.resize(RegUnitSets.size() + 1); 1604 RegUnitSets.back().Name = 1605 RegUnitSets[Idx].Name + "+" + RegUnitSets[SearchIdx].Name; 1606 1607 std::set_union(RegUnitSets[Idx].Units.begin(), 1608 RegUnitSets[Idx].Units.end(), 1609 RegUnitSets[SearchIdx].Units.begin(), 1610 RegUnitSets[SearchIdx].Units.end(), 1611 std::inserter(RegUnitSets.back().Units, 1612 RegUnitSets.back().Units.begin())); 1613 1614 // Find an existing RegUnitSet, or add the union to the unique sets. 1615 std::vector<RegUnitSet>::const_iterator SetI = 1616 findRegUnitSet(RegUnitSets, RegUnitSets.back()); 1617 if (SetI != std::prev(RegUnitSets.end())) 1618 RegUnitSets.pop_back(); 1619 else { 1620 DEBUG(dbgs() << "UnitSet " << RegUnitSets.size()-1 1621 << " " << RegUnitSets.back().Name << ":"; 1622 ArrayRef<unsigned> Units = RegUnitSets.back().Units; 1623 for (unsigned i = 0, e = Units.size(); i < e; ++i) 1624 dbgs() << " " << RegUnits[Units[i]].Roots[0]->getName(); 1625 dbgs() << "\n";); 1626 } 1627 } 1628 } 1629 1630 // Iteratively prune unit sets after inferring supersets. 1631 pruneUnitSets(); 1632 1633 DEBUG(dbgs() << "\n"; 1634 for (unsigned USIdx = 0, USEnd = RegUnitSets.size(); 1635 USIdx < USEnd; ++USIdx) { 1636 dbgs() << "UnitSet " << USIdx << " " << RegUnitSets[USIdx].Name 1637 << ":"; 1638 ArrayRef<unsigned> Units = RegUnitSets[USIdx].Units; 1639 for (unsigned i = 0, e = Units.size(); i < e; ++i) 1640 dbgs() << " " << RegUnits[Units[i]].Roots[0]->getName(); 1641 dbgs() << "\n"; 1642 }); 1643 1644 // For each register class, list the UnitSets that are supersets. 1645 RegClassUnitSets.resize(NumRegClasses); 1646 for (unsigned RCIdx = 0, RCEnd = NumRegClasses; RCIdx != RCEnd; ++RCIdx) { 1647 if (!RegClasses[RCIdx]->Allocatable) 1648 continue; 1649 1650 // Recompute the sorted list of units in this class. 1651 std::vector<unsigned> RCRegUnits; 1652 RegClasses[RCIdx]->buildRegUnitSet(RCRegUnits); 1653 1654 // Don't increase pressure for unallocatable regclasses. 1655 if (RCRegUnits.empty()) 1656 continue; 1657 1658 DEBUG(dbgs() << "RC " << RegClasses[RCIdx]->getName() << " Units: \n"; 1659 for (unsigned i = 0, e = RCRegUnits.size(); i < e; ++i) 1660 dbgs() << RegUnits[RCRegUnits[i]].getRoots()[0]->getName() << " "; 1661 dbgs() << "\n UnitSetIDs:"); 1662 1663 // Find all supersets. 1664 for (unsigned USIdx = 0, USEnd = RegUnitSets.size(); 1665 USIdx != USEnd; ++USIdx) { 1666 if (isRegUnitSubSet(RCRegUnits, RegUnitSets[USIdx].Units)) { 1667 DEBUG(dbgs() << " " << USIdx); 1668 RegClassUnitSets[RCIdx].push_back(USIdx); 1669 } 1670 } 1671 DEBUG(dbgs() << "\n"); 1672 assert(!RegClassUnitSets[RCIdx].empty() && "missing unit set for regclass"); 1673 } 1674 1675 // For each register unit, ensure that we have the list of UnitSets that 1676 // contain the unit. Normally, this matches an existing list of UnitSets for a 1677 // register class. If not, we create a new entry in RegClassUnitSets as a 1678 // "fake" register class. 1679 for (unsigned UnitIdx = 0, UnitEnd = NumNativeRegUnits; 1680 UnitIdx < UnitEnd; ++UnitIdx) { 1681 std::vector<unsigned> RUSets; 1682 for (unsigned i = 0, e = RegUnitSets.size(); i != e; ++i) { 1683 RegUnitSet &RUSet = RegUnitSets[i]; 1684 if (std::find(RUSet.Units.begin(), RUSet.Units.end(), UnitIdx) 1685 == RUSet.Units.end()) 1686 continue; 1687 RUSets.push_back(i); 1688 } 1689 unsigned RCUnitSetsIdx = 0; 1690 for (unsigned e = RegClassUnitSets.size(); 1691 RCUnitSetsIdx != e; ++RCUnitSetsIdx) { 1692 if (RegClassUnitSets[RCUnitSetsIdx] == RUSets) { 1693 break; 1694 } 1695 } 1696 RegUnits[UnitIdx].RegClassUnitSetsIdx = RCUnitSetsIdx; 1697 if (RCUnitSetsIdx == RegClassUnitSets.size()) { 1698 // Create a new list of UnitSets as a "fake" register class. 1699 RegClassUnitSets.resize(RCUnitSetsIdx + 1); 1700 RegClassUnitSets[RCUnitSetsIdx].swap(RUSets); 1701 } 1702 } 1703 } 1704 1705 void CodeGenRegBank::computeDerivedInfo() { 1706 computeComposites(); 1707 computeSubRegIndexLaneMasks(); 1708 1709 // Compute a weight for each register unit created during getSubRegs. 1710 // This may create adopted register units (with unit # >= NumNativeRegUnits). 1711 computeRegUnitWeights(); 1712 1713 // Compute a unique set of RegUnitSets. One for each RegClass and inferred 1714 // supersets for the union of overlapping sets. 1715 computeRegUnitSets(); 1716 1717 // Get the weight of each set. 1718 for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx) 1719 RegUnitSets[Idx].Weight = getRegUnitSetWeight(RegUnitSets[Idx].Units); 1720 1721 // Find the order of each set. 1722 RegUnitSetOrder.reserve(RegUnitSets.size()); 1723 for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx) 1724 RegUnitSetOrder.push_back(Idx); 1725 1726 std::stable_sort(RegUnitSetOrder.begin(), RegUnitSetOrder.end(), 1727 [this](unsigned ID1, unsigned ID2) { 1728 return getRegPressureSet(ID1).Units.size() < 1729 getRegPressureSet(ID2).Units.size(); 1730 }); 1731 for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx) { 1732 RegUnitSets[RegUnitSetOrder[Idx]].Order = Idx; 1733 } 1734 } 1735 1736 // 1737 // Synthesize missing register class intersections. 1738 // 1739 // Make sure that sub-classes of RC exists such that getCommonSubClass(RC, X) 1740 // returns a maximal register class for all X. 1741 // 1742 void CodeGenRegBank::inferCommonSubClass(CodeGenRegisterClass *RC) { 1743 for (unsigned rci = 0, rce = RegClasses.size(); rci != rce; ++rci) { 1744 CodeGenRegisterClass *RC1 = RC; 1745 CodeGenRegisterClass *RC2 = RegClasses[rci]; 1746 if (RC1 == RC2) 1747 continue; 1748 1749 // Compute the set intersection of RC1 and RC2. 1750 const CodeGenRegister::Set &Memb1 = RC1->getMembers(); 1751 const CodeGenRegister::Set &Memb2 = RC2->getMembers(); 1752 CodeGenRegister::Set Intersection; 1753 std::set_intersection(Memb1.begin(), Memb1.end(), 1754 Memb2.begin(), Memb2.end(), 1755 std::inserter(Intersection, Intersection.begin()), 1756 CodeGenRegister::Less()); 1757 1758 // Skip disjoint class pairs. 1759 if (Intersection.empty()) 1760 continue; 1761 1762 // If RC1 and RC2 have different spill sizes or alignments, use the 1763 // larger size for sub-classing. If they are equal, prefer RC1. 1764 if (RC2->SpillSize > RC1->SpillSize || 1765 (RC2->SpillSize == RC1->SpillSize && 1766 RC2->SpillAlignment > RC1->SpillAlignment)) 1767 std::swap(RC1, RC2); 1768 1769 getOrCreateSubClass(RC1, &Intersection, 1770 RC1->getName() + "_and_" + RC2->getName()); 1771 } 1772 } 1773 1774 // 1775 // Synthesize missing sub-classes for getSubClassWithSubReg(). 1776 // 1777 // Make sure that the set of registers in RC with a given SubIdx sub-register 1778 // form a register class. Update RC->SubClassWithSubReg. 1779 // 1780 void CodeGenRegBank::inferSubClassWithSubReg(CodeGenRegisterClass *RC) { 1781 // Map SubRegIndex to set of registers in RC supporting that SubRegIndex. 1782 typedef std::map<CodeGenSubRegIndex*, CodeGenRegister::Set, 1783 CodeGenSubRegIndex::Less> SubReg2SetMap; 1784 1785 // Compute the set of registers supporting each SubRegIndex. 1786 SubReg2SetMap SRSets; 1787 for (CodeGenRegister::Set::const_iterator RI = RC->getMembers().begin(), 1788 RE = RC->getMembers().end(); RI != RE; ++RI) { 1789 const CodeGenRegister::SubRegMap &SRM = (*RI)->getSubRegs(); 1790 for (CodeGenRegister::SubRegMap::const_iterator I = SRM.begin(), 1791 E = SRM.end(); I != E; ++I) 1792 SRSets[I->first].insert(*RI); 1793 } 1794 1795 // Find matching classes for all SRSets entries. Iterate in SubRegIndex 1796 // numerical order to visit synthetic indices last. 1797 for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) { 1798 CodeGenSubRegIndex *SubIdx = SubRegIndices[sri]; 1799 SubReg2SetMap::const_iterator I = SRSets.find(SubIdx); 1800 // Unsupported SubRegIndex. Skip it. 1801 if (I == SRSets.end()) 1802 continue; 1803 // In most cases, all RC registers support the SubRegIndex. 1804 if (I->second.size() == RC->getMembers().size()) { 1805 RC->setSubClassWithSubReg(SubIdx, RC); 1806 continue; 1807 } 1808 // This is a real subset. See if we have a matching class. 1809 CodeGenRegisterClass *SubRC = 1810 getOrCreateSubClass(RC, &I->second, 1811 RC->getName() + "_with_" + I->first->getName()); 1812 RC->setSubClassWithSubReg(SubIdx, SubRC); 1813 } 1814 } 1815 1816 // 1817 // Synthesize missing sub-classes of RC for getMatchingSuperRegClass(). 1818 // 1819 // Create sub-classes of RC such that getMatchingSuperRegClass(RC, SubIdx, X) 1820 // has a maximal result for any SubIdx and any X >= FirstSubRegRC. 1821 // 1822 1823 void CodeGenRegBank::inferMatchingSuperRegClass(CodeGenRegisterClass *RC, 1824 unsigned FirstSubRegRC) { 1825 SmallVector<std::pair<const CodeGenRegister*, 1826 const CodeGenRegister*>, 16> SSPairs; 1827 BitVector TopoSigs(getNumTopoSigs()); 1828 1829 // Iterate in SubRegIndex numerical order to visit synthetic indices last. 1830 for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) { 1831 CodeGenSubRegIndex *SubIdx = SubRegIndices[sri]; 1832 // Skip indexes that aren't fully supported by RC's registers. This was 1833 // computed by inferSubClassWithSubReg() above which should have been 1834 // called first. 1835 if (RC->getSubClassWithSubReg(SubIdx) != RC) 1836 continue; 1837 1838 // Build list of (Super, Sub) pairs for this SubIdx. 1839 SSPairs.clear(); 1840 TopoSigs.reset(); 1841 for (CodeGenRegister::Set::const_iterator RI = RC->getMembers().begin(), 1842 RE = RC->getMembers().end(); RI != RE; ++RI) { 1843 const CodeGenRegister *Super = *RI; 1844 const CodeGenRegister *Sub = Super->getSubRegs().find(SubIdx)->second; 1845 assert(Sub && "Missing sub-register"); 1846 SSPairs.push_back(std::make_pair(Super, Sub)); 1847 TopoSigs.set(Sub->getTopoSig()); 1848 } 1849 1850 // Iterate over sub-register class candidates. Ignore classes created by 1851 // this loop. They will never be useful. 1852 for (unsigned rci = FirstSubRegRC, rce = RegClasses.size(); rci != rce; 1853 ++rci) { 1854 CodeGenRegisterClass *SubRC = RegClasses[rci]; 1855 // Topological shortcut: SubRC members have the wrong shape. 1856 if (!TopoSigs.anyCommon(SubRC->getTopoSigs())) 1857 continue; 1858 // Compute the subset of RC that maps into SubRC. 1859 CodeGenRegister::Set SubSet; 1860 for (unsigned i = 0, e = SSPairs.size(); i != e; ++i) 1861 if (SubRC->contains(SSPairs[i].second)) 1862 SubSet.insert(SSPairs[i].first); 1863 if (SubSet.empty()) 1864 continue; 1865 // RC injects completely into SubRC. 1866 if (SubSet.size() == SSPairs.size()) { 1867 SubRC->addSuperRegClass(SubIdx, RC); 1868 continue; 1869 } 1870 // Only a subset of RC maps into SubRC. Make sure it is represented by a 1871 // class. 1872 getOrCreateSubClass(RC, &SubSet, RC->getName() + 1873 "_with_" + SubIdx->getName() + 1874 "_in_" + SubRC->getName()); 1875 } 1876 } 1877 } 1878 1879 1880 // 1881 // Infer missing register classes. 1882 // 1883 void CodeGenRegBank::computeInferredRegisterClasses() { 1884 // When this function is called, the register classes have not been sorted 1885 // and assigned EnumValues yet. That means getSubClasses(), 1886 // getSuperClasses(), and hasSubClass() functions are defunct. 1887 unsigned FirstNewRC = RegClasses.size(); 1888 1889 // Visit all register classes, including the ones being added by the loop. 1890 for (unsigned rci = 0; rci != RegClasses.size(); ++rci) { 1891 CodeGenRegisterClass *RC = RegClasses[rci]; 1892 1893 // Synthesize answers for getSubClassWithSubReg(). 1894 inferSubClassWithSubReg(RC); 1895 1896 // Synthesize answers for getCommonSubClass(). 1897 inferCommonSubClass(RC); 1898 1899 // Synthesize answers for getMatchingSuperRegClass(). 1900 inferMatchingSuperRegClass(RC); 1901 1902 // New register classes are created while this loop is running, and we need 1903 // to visit all of them. I particular, inferMatchingSuperRegClass needs 1904 // to match old super-register classes with sub-register classes created 1905 // after inferMatchingSuperRegClass was called. At this point, 1906 // inferMatchingSuperRegClass has checked SuperRC = [0..rci] with SubRC = 1907 // [0..FirstNewRC). We need to cover SubRC = [FirstNewRC..rci]. 1908 if (rci + 1 == FirstNewRC) { 1909 unsigned NextNewRC = RegClasses.size(); 1910 for (unsigned rci2 = 0; rci2 != FirstNewRC; ++rci2) 1911 inferMatchingSuperRegClass(RegClasses[rci2], FirstNewRC); 1912 FirstNewRC = NextNewRC; 1913 } 1914 } 1915 } 1916 1917 /// getRegisterClassForRegister - Find the register class that contains the 1918 /// specified physical register. If the register is not in a register class, 1919 /// return null. If the register is in multiple classes, and the classes have a 1920 /// superset-subset relationship and the same set of types, return the 1921 /// superclass. Otherwise return null. 1922 const CodeGenRegisterClass* 1923 CodeGenRegBank::getRegClassForRegister(Record *R) { 1924 const CodeGenRegister *Reg = getReg(R); 1925 ArrayRef<CodeGenRegisterClass*> RCs = getRegClasses(); 1926 const CodeGenRegisterClass *FoundRC = nullptr; 1927 for (unsigned i = 0, e = RCs.size(); i != e; ++i) { 1928 const CodeGenRegisterClass &RC = *RCs[i]; 1929 if (!RC.contains(Reg)) 1930 continue; 1931 1932 // If this is the first class that contains the register, 1933 // make a note of it and go on to the next class. 1934 if (!FoundRC) { 1935 FoundRC = &RC; 1936 continue; 1937 } 1938 1939 // If a register's classes have different types, return null. 1940 if (RC.getValueTypes() != FoundRC->getValueTypes()) 1941 return nullptr; 1942 1943 // Check to see if the previously found class that contains 1944 // the register is a subclass of the current class. If so, 1945 // prefer the superclass. 1946 if (RC.hasSubClass(FoundRC)) { 1947 FoundRC = &RC; 1948 continue; 1949 } 1950 1951 // Check to see if the previously found class that contains 1952 // the register is a superclass of the current class. If so, 1953 // prefer the superclass. 1954 if (FoundRC->hasSubClass(&RC)) 1955 continue; 1956 1957 // Multiple classes, and neither is a superclass of the other. 1958 // Return null. 1959 return nullptr; 1960 } 1961 return FoundRC; 1962 } 1963 1964 BitVector CodeGenRegBank::computeCoveredRegisters(ArrayRef<Record*> Regs) { 1965 SetVector<const CodeGenRegister*> Set; 1966 1967 // First add Regs with all sub-registers. 1968 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 1969 CodeGenRegister *Reg = getReg(Regs[i]); 1970 if (Set.insert(Reg)) 1971 // Reg is new, add all sub-registers. 1972 // The pre-ordering is not important here. 1973 Reg->addSubRegsPreOrder(Set, *this); 1974 } 1975 1976 // Second, find all super-registers that are completely covered by the set. 1977 for (unsigned i = 0; i != Set.size(); ++i) { 1978 const CodeGenRegister::SuperRegList &SR = Set[i]->getSuperRegs(); 1979 for (unsigned j = 0, e = SR.size(); j != e; ++j) { 1980 const CodeGenRegister *Super = SR[j]; 1981 if (!Super->CoveredBySubRegs || Set.count(Super)) 1982 continue; 1983 // This new super-register is covered by its sub-registers. 1984 bool AllSubsInSet = true; 1985 const CodeGenRegister::SubRegMap &SRM = Super->getSubRegs(); 1986 for (CodeGenRegister::SubRegMap::const_iterator I = SRM.begin(), 1987 E = SRM.end(); I != E; ++I) 1988 if (!Set.count(I->second)) { 1989 AllSubsInSet = false; 1990 break; 1991 } 1992 // All sub-registers in Set, add Super as well. 1993 // We will visit Super later to recheck its super-registers. 1994 if (AllSubsInSet) 1995 Set.insert(Super); 1996 } 1997 } 1998 1999 // Convert to BitVector. 2000 BitVector BV(Registers.size() + 1); 2001 for (unsigned i = 0, e = Set.size(); i != e; ++i) 2002 BV.set(Set[i]->EnumValue); 2003 return BV; 2004 } 2005