/external/llvm/lib/Target/Hexagon/ |
HexagonMachineScheduler.h | 103 /// Perform platform-specific DAG postprocessing. 134 VLIWMachineScheduler *DAG; 156 DAG(nullptr), SchedModel(nullptr), Available(ID, Name+".A"), 167 void init(VLIWMachineScheduler *dag, const TargetSchedModel *smodel) { 168 DAG = dag; 191 VLIWMachineScheduler *DAG; 207 : DAG(nullptr), SchedModel(nullptr), Top(TopQID, "TopQ"), 210 virtual void initialize(ScheduleDAGMI *dag) override;
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HexagonMachineScheduler.cpp | 23 /// Platform-specific modifications to DAG. 142 /// only includes instructions that have DAG nodes, not scheduling boundaries. 153 // Postprocess the DAG to add platform-specific artificial dependencies. 159 // Initialize the strategy before modifying the DAG. 190 // Notify the scheduling strategy after updating the DAG. 198 void ConvergingVLIWScheduler::initialize(ScheduleDAGMI *dag) { 199 DAG = static_cast<VLIWMachineScheduler*>(dag); 200 SchedModel = DAG->getSchedModel(); 202 Top.init(DAG, SchedModel) [all...] |
/external/llvm/lib/Target/R600/ |
R600MachineScheduler.h | 29 const ScheduleDAGMILive *DAG; 71 DAG(nullptr), TII(nullptr), TRI(nullptr), MRI(nullptr) { 76 void initialize(ScheduleDAGMI *dag) override;
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R600MachineScheduler.cpp | 27 void R600SchedStrategy::initialize(ScheduleDAGMI *dag) { 28 assert(dag->hasVRegLiveness() && "R600SchedStrategy needs vreg liveness"); 29 DAG = static_cast<ScheduleDAGMILive*>(dag); 30 TII = static_cast<const R600InstrInfo*>(DAG->TII); 31 TRI = static_cast<const R600RegisterInfo*>(DAG->TRI); 32 VLIW5 = !DAG->MF.getTarget().getSubtarget<AMDGPUSubtarget>().hasCaymanISA(); 33 MRI = &DAG->MRI; 40 const AMDGPUSubtarget &ST = DAG->TM.getSubtarget<AMDGPUSubtarget>(); 128 SU->dump(DAG); [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
Makefile | 49 $(call tablegen, -gen-dag-isel, AMDGPU.td, $@)
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R600GenRegisterInfo.pl | 60 class RegSet <dag s> { 61 dag set = s;
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/external/llvm/lib/CodeGen/SelectionDAG/ |
ScheduleDAGSDNodes.h | 34 /// the DAG and must be handled explicitly by schedulers. 39 SelectionDAG *DAG; // DAG of the current basic block 51 void Run(SelectionDAG *dag, MachineBasicBlock *bb); 82 /// BuildSchedGraph - Build the SUnit graph from the selection dag that we
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SelectionDAGBuilder.h | 1 //===-- SelectionDAGBuilder.h - Selection-DAG building --------*- C++ -*---===// 344 /// implying one could not create a DAG Combine to move the callinst. 495 SelectionDAG &DAG; 533 /// no subsequent DAG nodes should be created. 539 SelectionDAGBuilder(SelectionDAG &dag, FunctionLoweringInfo &funcinfo, 541 : CurInst(nullptr), SDNodeOrder(LowestSDNodeOrder), TM(dag.getTarget()), 542 DAG(dag), FuncInfo(funcinfo), OptLevel(ol), 565 /// getRoot - Return the current virtual root of the Selection DAG,
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LegalizeTypes.h | 1 //===-- LegalizeTypes.h - DAG Type Legalizer class definition ---*- C++ -*-===// 36 SelectionDAG &DAG; 67 return TLI.getTypeAction(*DAG.getContext(), VT); 72 return TLI.getTypeAction(*DAG.getContext(), VT) == TargetLowering::TypeLegal; 76 return TLI.getSetCCResultType(*DAG.getContext(), VT); 122 explicit DAGTypeLegalizer(SelectionDAG &dag) 123 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 130 /// top-down traversal of the dag, legalizing types as it goes. Return [all...] |
LegalizeVectorOps.cpp | 36 SelectionDAG& DAG; 127 /// \brief Begin legalizer the vector operations in the DAG. 129 VectorLegalizer(SelectionDAG& dag) : 130 DAG(dag), TLI(dag.getTargetLoweringInfo()), Changed(false) {} 136 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 137 E = std::prev(DAG.allnodes_end()); I != std::next(E); ++I) { 159 DAG.AssignTopologicalOrder(); 160 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin() [all...] |
ScheduleDAGSDNodes.cpp | 50 : ScheduleDAG(mf), BB(nullptr), DAG(nullptr), 55 void ScheduleDAGSDNodes::Run(SelectionDAG *dag, MachineBasicBlock *bb) { 57 DAG = dag; 59 // Clear the scheduler's SUnit DAG. 80 const TargetLowering &TLI = DAG->getTargetLoweringInfo(); 136 static void CloneNodeWithValues(SDNode *N, SelectionDAG *DAG, 146 SDVTList VTList = DAG->getVTList(VTs); 156 DAG->MorphNodeTo(N, N->getOpcode(), VTList, Ops); 163 static bool AddGlue(SDNode *N, SDValue Glue, bool AddGlue, SelectionDAG *DAG) { [all...] |
/external/mesa3d/src/gallium/drivers/radeon/ |
Makefile | 49 $(call tablegen, -gen-dag-isel, AMDGPU.td, $@)
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R600GenRegisterInfo.pl | 60 class RegSet <dag s> { 61 dag set = s;
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/external/llvm/utils/vim/ |
tablegen.vim | 17 syn keyword tgKeyword def let in code dag field include defm foreach
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/external/llvm/lib/TableGen/ |
TGLexer.cpp | 273 .Case("dag", tgtok::Dag)
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/ndk/sources/host-tools/nawk-20071023/ |
FIXES | 222 dag-erling smorgrav, des@ofug.org). subject to reversion if 248 portable. thanks to dag-erling smorgrav for code. [all...] |
/external/llvm/include/llvm/CodeGen/ |
MachineScheduler.h | 18 // scheduled. Targets can override the DAG builder and scheduler without 26 // The default scheduler, ScheduleDAGMILive, builds the DAG and drives list 28 // intervals. Most targets don't need to override the DAG builder and list 38 // The DAG builder can also be customized in a sense by adding DAG mutations 39 // that will run after DAG building and before list scheduling. DAG mutations 45 // ScheduleDAGMI *DAG = new ScheduleDAGMI(C, CustomStrategy(C)); 46 // DAG->addMutation(new CustomDependencies(DAG->TII, DAG->TRI)) [all...] |
/external/llvm/ |
llvm-tblgen-rules.mk | 153 $(call transform-td-to-out,dag-isel)
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/prebuilts/eclipse/maven/apache-maven-3.2.1/lib/ |
plexus-utils-3.0.17.jar | |
/prebuilts/eclipse/mavenplugins/tycho/tycho-dependencies-m2repo/org/codehaus/plexus/plexus-utils/2.0.5/ |
plexus-utils-2.0.5.jar | |
/prebuilts/eclipse/mavenplugins/tycho/tycho-dependencies-m2repo/org/codehaus/plexus/plexus-utils/3.0/ |
plexus-utils-3.0.jar | |
/prebuilts/eclipse/mavenplugins/tycho/tycho-dependencies-m2repo/org/codehaus/plexus/plexus-utils/3.0.7/ |
plexus-utils-3.0.7.jar | |
/prebuilts/tools/common/m2/repository/org/codehaus/plexus/plexus-utils/1.5.1/ |
plexus-utils-1.5.1.jar | |
/prebuilts/tools/common/m2/repository/org/codehaus/plexus/plexus-utils/3.0.7/ |
plexus-utils-3.0.7.jar | |
/external/llvm/lib/CodeGen/ |
MachineScheduler.cpp | 76 // DAG subtrees must have at least this many nodes. 291 /// consistent with the DAG builder, which traverses the interior of the 294 /// This design avoids exposing scheduling boundaries to the DAG builder, 295 /// simplifying the DAG builder's support for "special" target instructions. 365 /// handle calls, the DAG builder needs to be modified to create register 403 // boundary at the bottom of the region. The DAG does not include RegionEnd, 644 // Build the DAG. 654 // Initialize the strategy before modifying the DAG. 662 // Initialize ready queues now that the DAG and priority data are finalized. 692 // Notify the scheduling strategy before updating the DAG [all...] |