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    Searched refs:hasSubClassEq (Results 1 - 16 of 16) sorted by null

  /external/llvm/lib/Target/Mips/
MipsSEInstrInfo.cpp 193 if (Mips::GPR32RegClass.hasSubClassEq(RC))
195 else if (Mips::GPR64RegClass.hasSubClassEq(RC))
197 else if (Mips::ACC64RegClass.hasSubClassEq(RC))
199 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
201 else if (Mips::ACC128RegClass.hasSubClassEq(RC))
203 else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
205 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
207 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
209 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
234 if (Mips::GPR32RegClass.hasSubClassEq(RC)
    [all...]
Mips16InstrInfo.cpp 105 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
122 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC))
  /external/llvm/lib/Target/PowerPC/
PPCInstrInfo.cpp 607 if (!PPC::GPRCRegClass.hasSubClassEq(RC) &&
608 !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) &&
609 !PPC::G8RCRegClass.hasSubClassEq(RC) &&
610 !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC))
641 bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) ||
642 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC);
644 PPC::GPRCRegClass.hasSubClassEq(RC) ||
645 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) &&
782 if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
783 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC))
    [all...]
  /external/llvm/lib/Target/AArch64/
AArch64InstrInfo.cpp 311 bool Is64Bit = AArch64::GPR64allRegClass.hasSubClassEq(MRI.getRegClass(VReg));
385 if (AArch64::GPR64allRegClass.hasSubClassEq(RC) ||
386 AArch64::GPR32allRegClass.hasSubClassEq(RC)) {
399 if (AArch64::FPR64RegClass.hasSubClassEq(RC) ||
400 AArch64::FPR32RegClass.hasSubClassEq(RC)) {
647 } else if (!OpRegCstraints->hasSubClassEq(MRI->getRegClass(Reg)) &&
    [all...]
  /external/llvm/include/llvm/Target/
TargetRegisterInfo.h 126 return RC != this && hasSubClassEq(RC);
129 /// hasSubClassEq - Returns true if RC is a sub-class of or equal to this
131 bool hasSubClassEq(const TargetRegisterClass *RC) const {
145 return RC->hasSubClassEq(this);
149 /// The vector is indexed by class IDs, see hasSubClassEq() above for how to
    [all...]
  /external/llvm/lib/Target/Sparc/
SparcInstrInfo.cpp 376 else if (SP::DFPRegsRegClass.hasSubClassEq(RC))
379 else if (SP::QFPRegsRegClass.hasSubClassEq(RC))
413 else if (SP::DFPRegsRegClass.hasSubClassEq(RC))
416 else if (SP::QFPRegsRegClass.hasSubClassEq(RC))
SparcISelLowering.cpp     [all...]
  /external/llvm/lib/Target/ARM/
ARMBaseInstrInfo.cpp 814 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
818 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
826 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
830 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
851 if (ARM::DPairRegClass.hasSubClassEq(RC)) {
868 if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
888 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
910 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
    [all...]
Thumb2InstrInfo.cpp 150 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
191 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
Thumb1RegisterInfo.cpp 48 if (ARM::tGPRRegClass.hasSubClassEq(RC))
  /external/llvm/lib/Target/X86/
X86InstrInfo.cpp     [all...]
  /external/llvm/lib/Target/Hexagon/
HexagonInstrInfo.cpp 490 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
494 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
498 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
    [all...]
  /external/llvm/lib/CodeGen/
MachineFunction.cpp 448 RC->hasSubClassEq(VRegRC))) &&
    [all...]
TargetInstrInfo.cpp 366 if (RC->hasSubClassEq(MRI.getRegClass(LiveReg)))
  /external/llvm/lib/CodeGen/SelectionDAG/
InstrEmitter.cpp 546 if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase)))
    [all...]
  /external/llvm/lib/Target/R600/
SIISelLowering.cpp     [all...]

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