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      1 //===-- MipsSubtarget.cpp - Mips Subtarget Information --------------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file implements the Mips specific subclass of TargetSubtargetInfo.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #include "MipsMachineFunction.h"
     15 #include "Mips.h"
     16 #include "MipsRegisterInfo.h"
     17 #include "MipsSubtarget.h"
     18 #include "MipsTargetMachine.h"
     19 #include "llvm/IR/Attributes.h"
     20 #include "llvm/IR/Function.h"
     21 #include "llvm/Support/CommandLine.h"
     22 #include "llvm/Support/Debug.h"
     23 #include "llvm/Support/TargetRegistry.h"
     24 #include "llvm/Support/raw_ostream.h"
     25 
     26 using namespace llvm;
     27 
     28 #define DEBUG_TYPE "mips-subtarget"
     29 
     30 #define GET_SUBTARGETINFO_TARGET_DESC
     31 #define GET_SUBTARGETINFO_CTOR
     32 #include "MipsGenSubtargetInfo.inc"
     33 
     34 // FIXME: Maybe this should be on by default when Mips16 is specified
     35 //
     36 static cl::opt<bool> Mixed16_32(
     37   "mips-mixed-16-32",
     38   cl::init(false),
     39   cl::desc("Allow for a mixture of Mips16 "
     40            "and Mips32 code in a single source file"),
     41   cl::Hidden);
     42 
     43 static cl::opt<bool> Mips_Os16(
     44   "mips-os16",
     45   cl::init(false),
     46   cl::desc("Compile all functions that don' use "
     47            "floating point as Mips 16"),
     48   cl::Hidden);
     49 
     50 static cl::opt<bool>
     51 Mips16HardFloat("mips16-hard-float", cl::NotHidden,
     52                 cl::desc("MIPS: mips16 hard float enable."),
     53                 cl::init(false));
     54 
     55 static cl::opt<bool>
     56 Mips16ConstantIslands(
     57   "mips16-constant-islands", cl::NotHidden,
     58   cl::desc("MIPS: mips16 constant islands enable."),
     59   cl::init(true));
     60 
     61 /// Select the Mips CPU for the given triple and cpu name.
     62 /// FIXME: Merge with the copy in MipsMCTargetDesc.cpp
     63 static StringRef selectMipsCPU(Triple TT, StringRef CPU) {
     64   if (CPU.empty() || CPU == "generic") {
     65     if (TT.getArch() == Triple::mips || TT.getArch() == Triple::mipsel)
     66       CPU = "mips32";
     67     else
     68       CPU = "mips64";
     69   }
     70   return CPU;
     71 }
     72 
     73 void MipsSubtarget::anchor() { }
     74 
     75 static std::string computeDataLayout(const MipsSubtarget &ST) {
     76   std::string Ret = "";
     77 
     78   // There are both little and big endian mips.
     79   if (ST.isLittle())
     80     Ret += "e";
     81   else
     82     Ret += "E";
     83 
     84   Ret += "-m:m";
     85 
     86   // Pointers are 32 bit on some ABIs.
     87   if (!ST.isABI_N64())
     88     Ret += "-p:32:32";
     89 
     90   // 8 and 16 bit integers only need no have natural alignment, but try to
     91   // align them to 32 bits. 64 bit integers have natural alignment.
     92   Ret += "-i8:8:32-i16:16:32-i64:64";
     93 
     94   // 32 bit registers are always available and the stack is at least 64 bit
     95   // aligned. On N64 64 bit registers are also available and the stack is
     96   // 128 bit aligned.
     97   if (ST.isABI_N64() || ST.isABI_N32())
     98     Ret += "-n32:64-S128";
     99   else
    100     Ret += "-n32-S64";
    101 
    102   return Ret;
    103 }
    104 
    105 MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
    106                              const std::string &FS, bool little,
    107                              Reloc::Model _RM, MipsTargetMachine *_TM)
    108     : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(Mips32),
    109       MipsABI(UnknownABI), IsLittle(little), IsSingleFloat(false),
    110       IsFPXX(false), IsFP64bit(false), UseOddSPReg(true), IsNaN2008bit(false),
    111       IsGP64bit(false), HasVFPU(false), HasCnMips(false), IsLinux(true),
    112       HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false),
    113       HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false),
    114       InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
    115       HasDSPR2(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16),
    116       HasMSA(false), RM(_RM), OverrideMode(NoOverride), TM(_TM),
    117       TargetTriple(TT),
    118       DL(computeDataLayout(initializeSubtargetDependencies(CPU, FS, TM))),
    119       TSInfo(DL), JITInfo(), InstrInfo(MipsInstrInfo::create(*TM)),
    120       FrameLowering(MipsFrameLowering::create(*TM, *this)),
    121       TLInfo(MipsTargetLowering::create(*TM)) {
    122 
    123   PreviousInMips16Mode = InMips16Mode;
    124 
    125   // Don't even attempt to generate code for MIPS-I, MIPS-II, MIPS-III, and
    126   // MIPS-V. They have not been tested and currently exist for the integrated
    127   // assembler only.
    128   if (MipsArchVersion == Mips1)
    129     report_fatal_error("Code generation for MIPS-I is not implemented", false);
    130   if (MipsArchVersion == Mips2)
    131     report_fatal_error("Code generation for MIPS-II is not implemented", false);
    132   if (MipsArchVersion == Mips3)
    133     report_fatal_error("Code generation for MIPS-III is not implemented",
    134                        false);
    135   if (MipsArchVersion == Mips5)
    136     report_fatal_error("Code generation for MIPS-V is not implemented", false);
    137 
    138   // Assert exactly one ABI was chosen.
    139   assert(MipsABI != UnknownABI);
    140   assert((((getFeatureBits() & Mips::FeatureO32) != 0) +
    141           ((getFeatureBits() & Mips::FeatureEABI) != 0) +
    142           ((getFeatureBits() & Mips::FeatureN32) != 0) +
    143           ((getFeatureBits() & Mips::FeatureN64) != 0)) == 1);
    144 
    145   // Check if Architecture and ABI are compatible.
    146   assert(((!isGP64bit() && (isABI_O32() || isABI_EABI())) ||
    147           (isGP64bit() && (isABI_N32() || isABI_N64()))) &&
    148          "Invalid  Arch & ABI pair.");
    149 
    150   if (hasMSA() && !isFP64bit())
    151     report_fatal_error("MSA requires a 64-bit FPU register file (FR=1 mode). "
    152                        "See -mattr=+fp64.",
    153                        false);
    154 
    155   if (!isABI_O32() && !useOddSPReg())
    156     report_fatal_error("-mattr=+nooddspreg is not currently permitted for a "
    157                        "the O32 ABI.",
    158                        false);
    159 
    160   if (hasMips32r6()) {
    161     StringRef ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6";
    162 
    163     assert(isFP64bit());
    164     assert(isNaN2008());
    165     if (hasDSP())
    166       report_fatal_error(ISA + " is not compatible with the DSP ASE", false);
    167   }
    168 
    169   // Is the target system Linux ?
    170   if (TT.find("linux") == std::string::npos)
    171     IsLinux = false;
    172 
    173   // Set UseSmallSection.
    174   // TODO: Investigate the IsLinux check. I suspect it's really checking for
    175   //       bare-metal.
    176   UseSmallSection = !IsLinux && (RM == Reloc::Static);
    177 }
    178 
    179 bool
    180 MipsSubtarget::enablePostRAScheduler(CodeGenOpt::Level OptLevel,
    181                                     TargetSubtargetInfo::AntiDepBreakMode &Mode,
    182                                      RegClassVector &CriticalPathRCs) const {
    183   Mode = TargetSubtargetInfo::ANTIDEP_NONE;
    184   CriticalPathRCs.clear();
    185   CriticalPathRCs.push_back(isGP64bit() ? &Mips::GPR64RegClass
    186                                         : &Mips::GPR32RegClass);
    187   return OptLevel >= CodeGenOpt::Aggressive;
    188 }
    189 
    190 MipsSubtarget &
    191 MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS,
    192                                                const TargetMachine *TM) {
    193   std::string CPUName = selectMipsCPU(TargetTriple, CPU);
    194 
    195   // Parse features string.
    196   ParseSubtargetFeatures(CPUName, FS);
    197   // Initialize scheduling itinerary for the specified CPU.
    198   InstrItins = getInstrItineraryForCPU(CPUName);
    199 
    200   if (InMips16Mode && !TM->Options.UseSoftFloat) {
    201     // Hard float for mips16 means essentially to compile as soft float
    202     // but to use a runtime library for soft float that is written with
    203     // native mips32 floating point instructions (those runtime routines
    204     // run in mips32 hard float mode).
    205     TM->Options.UseSoftFloat = true;
    206     TM->Options.FloatABIType = FloatABI::Soft;
    207     InMips16HardFloat = true;
    208   }
    209 
    210   return *this;
    211 }
    212 
    213 //FIXME: This logic for reseting the subtarget along with
    214 // the helper classes can probably be simplified but there are a lot of
    215 // cases so we will defer rewriting this to later.
    216 //
    217 void MipsSubtarget::resetSubtarget(MachineFunction *MF) {
    218   bool ChangeToMips16 = false, ChangeToNoMips16 = false;
    219   DEBUG(dbgs() << "resetSubtargetFeatures" << "\n");
    220   AttributeSet FnAttrs = MF->getFunction()->getAttributes();
    221   ChangeToMips16 = FnAttrs.hasAttribute(AttributeSet::FunctionIndex,
    222                                         "mips16");
    223   ChangeToNoMips16 = FnAttrs.hasAttribute(AttributeSet::FunctionIndex,
    224                                         "nomips16");
    225   assert (!(ChangeToMips16 & ChangeToNoMips16) &&
    226           "mips16 and nomips16 specified on the same function");
    227   if (ChangeToMips16) {
    228     if (PreviousInMips16Mode)
    229       return;
    230     OverrideMode = Mips16Override;
    231     PreviousInMips16Mode = true;
    232     setHelperClassesMips16();
    233     return;
    234   } else if (ChangeToNoMips16) {
    235     if (!PreviousInMips16Mode)
    236       return;
    237     OverrideMode = NoMips16Override;
    238     PreviousInMips16Mode = false;
    239     setHelperClassesMipsSE();
    240     return;
    241   } else {
    242     if (OverrideMode == NoOverride)
    243       return;
    244     OverrideMode = NoOverride;
    245     DEBUG(dbgs() << "back to default" << "\n");
    246     if (inMips16Mode() && !PreviousInMips16Mode) {
    247       setHelperClassesMips16();
    248       PreviousInMips16Mode = true;
    249     } else if (!inMips16Mode() && PreviousInMips16Mode) {
    250       setHelperClassesMipsSE();
    251       PreviousInMips16Mode = false;
    252     }
    253     return;
    254   }
    255 }
    256 
    257 void MipsSubtarget::setHelperClassesMips16() {
    258   InstrInfoSE.swap(InstrInfo);
    259   FrameLoweringSE.swap(FrameLowering);
    260   TLInfoSE.swap(TLInfo);
    261   if (!InstrInfo16) {
    262     InstrInfo.reset(MipsInstrInfo::create(*TM));
    263     FrameLowering.reset(MipsFrameLowering::create(*TM, *this));
    264     TLInfo.reset(MipsTargetLowering::create(*TM));
    265   } else {
    266     InstrInfo16.swap(InstrInfo);
    267     FrameLowering16.swap(FrameLowering);
    268     TLInfo16.swap(TLInfo);
    269   }
    270   assert(TLInfo && "null target lowering 16");
    271   assert(InstrInfo && "null instr info 16");
    272   assert(FrameLowering && "null frame lowering 16");
    273 }
    274 
    275 void MipsSubtarget::setHelperClassesMipsSE() {
    276   InstrInfo16.swap(InstrInfo);
    277   FrameLowering16.swap(FrameLowering);
    278   TLInfo16.swap(TLInfo);
    279   if (!InstrInfoSE) {
    280     InstrInfo.reset(MipsInstrInfo::create(*TM));
    281     FrameLowering.reset(MipsFrameLowering::create(*TM, *this));
    282     TLInfo.reset(MipsTargetLowering::create(*TM));
    283   } else {
    284     InstrInfoSE.swap(InstrInfo);
    285     FrameLoweringSE.swap(FrameLowering);
    286     TLInfoSE.swap(TLInfo);
    287   }
    288   assert(TLInfo && "null target lowering in SE");
    289   assert(InstrInfo && "null instr info SE");
    290   assert(FrameLowering && "null frame lowering SE");
    291 }
    292 
    293 bool MipsSubtarget::mipsSEUsesSoftFloat() const {
    294   return TM->Options.UseSoftFloat && !InMips16HardFloat;
    295 }
    296 
    297 bool MipsSubtarget::useConstantIslands() {
    298   DEBUG(dbgs() << "use constant islands " << Mips16ConstantIslands << "\n");
    299   return Mips16ConstantIslands;
    300 }
    301