/art/compiler/dex/quick/mips/ |
utility_mips.cc | 25 LIR* MipsMir2Lir::OpFpRegCopy(RegStorage r_dest, RegStorage r_src) { 28 DCHECK_EQ(r_dest.IsDouble(), r_src.IsDouble()); 33 if (r_src.IsSingle()) { 37 RegStorage t_opnd = r_src; 38 r_src = r_dest; 43 DCHECK(r_src.IsSingle()); 47 LIR* res = RawLIR(current_dalvik_offset_, opcode, r_src.GetReg(), r_dest.GetReg()); 48 if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && r_dest == r_src) { 334 LIR* MipsMir2Lir::OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) { 339 LIR* MipsMir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) { [all...] |
int_mips.cc | 163 LIR* MipsMir2Lir::OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) { 168 if (r_src.IsPair()) { 169 r_src = r_src.GetLow(); 171 if (r_dest.IsFloat() || r_src.IsFloat()) 172 return OpFpRegCopy(r_dest, r_src); 174 r_dest.GetReg(), r_src.GetReg()); 175 if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && r_dest == r_src) { 181 void MipsMir2Lir::OpRegCopy(RegStorage r_dest, RegStorage r_src) { 182 if (r_dest != r_src) { [all...] |
codegen_mips.h | 41 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, 43 LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale, 46 LIR* GenAtomic64Store(RegStorage r_base, int displacement, RegStorage r_src); 141 LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src); 147 void OpRegCopy(RegStorage r_dest, RegStorage r_src); 148 LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src); 152 LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type); 153 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src); 164 // TODO: collapse r_src. 165 LIR* StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src, [all...] |
target_mips.cc | 509 LIR* MipsMir2Lir::GenAtomic64Store(RegStorage r_base, int displacement, RegStorage r_src) { 510 DCHECK(!r_src.IsFloat()); // See RegClassForFieldLoadStore(). 511 DCHECK(r_src.IsPair()); 517 OpRegCopyWide(temp_value, r_src);
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/art/compiler/dex/quick/x86/ |
utility_x86.cc | 29 LIR* X86Mir2Lir::OpFpRegCopy(RegStorage r_dest, RegStorage r_src) { 32 DCHECK(r_dest.IsFloat() || r_src.IsFloat()); 33 DCHECK_EQ(r_dest.IsDouble(), r_src.IsDouble()); 38 if (r_src.IsSingle()) { 44 DCHECK(r_src.IsSingle()) << "Raw: 0x" << std::hex << r_src.GetRawBits(); 49 LIR* res = RawLIR(current_dalvik_offset_, opcode, r_dest.GetReg(), r_src.GetReg()); 50 if (r_dest == r_src) { 303 LIR* X86Mir2Lir::OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) { 305 int src = r_src.IsPair() ? r_src.GetLowReg() : r_src.GetReg() [all...] |
int_x86.cc | 123 LIR* X86Mir2Lir::OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) { 128 if (r_src.IsPair()) { 129 r_src = r_src.GetLow(); 131 if (r_dest.IsFloat() || r_src.IsFloat()) 132 return OpFpRegCopy(r_dest, r_src); 134 r_dest.GetReg(), r_src.GetReg()); 135 if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && r_dest == r_src) { 141 void X86Mir2Lir::OpRegCopy(RegStorage r_dest, RegStorage r_src) { 142 if (r_dest != r_src) { [all...] |
codegen_x86.h | 78 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, 80 LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale, 268 LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src) OVERRIDE; 274 void OpRegCopy(RegStorage r_dest, RegStorage r_src) OVERRIDE; 275 LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) OVERRIDE; 279 LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) OVERRIDE; 280 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) OVERRIDE; 413 RegStorage r_src, OpSize size); [all...] |
/art/compiler/dex/quick/arm/ |
utility_arm.cc | 380 LIR* ArmMir2Lir::OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) { 385 LIR* ArmMir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) { 758 LIR* ArmMir2Lir::StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, 760 bool all_low_regs = r_base.Low8() && r_index.Low8() && r_src.Low8(); 766 if (r_src.IsFloat()) { 767 if (r_src.IsSingle()) { 772 DCHECK(r_src.IsDouble()); 774 DCHECK_EQ((r_src.GetReg() & 0x1), 0); 794 store = NewLIR3(opcode, r_src.GetReg(), reg_ptr.GetReg(), 0); 816 store = NewLIR3(opcode, r_src.GetReg(), r_base.GetReg(), r_index.GetReg()) [all...] |
codegen_arm.h | 41 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, 43 LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale, 143 LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src); 150 void OpRegCopy(RegStorage r_dest, RegStorage r_src); 151 LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src); 155 LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type); 156 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src); 165 LIR* StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src, OpSize size); 212 void GenEasyMultiplyTwoOps(RegStorage r_dest, RegStorage r_src, EasyMultiplyOp* ops);
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int_arm.cc | 401 LIR* ArmMir2Lir::OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) { 408 if (r_src.IsPair()) { 409 r_src = r_src.GetLow(); 411 if (r_dest.IsFloat() || r_src.IsFloat()) 412 return OpFpRegCopy(r_dest, r_src); 413 if (r_dest.Low8() && r_src.Low8()) 415 else if (!r_dest.Low8() && !r_src.Low8()) 421 res = RawLIR(current_dalvik_offset_, opcode, r_dest.GetReg(), r_src.GetReg()); 422 if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && r_dest == r_src) { [all...] |
/art/compiler/dex/quick/arm64/ |
utility_arm64.cc | 685 LIR* Arm64Mir2Lir::OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) { 690 LIR* Arm64Mir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) { [all...] |
codegen_arm64.h | 85 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size, 87 LIR* StoreRefDisp(RegStorage r_base, int displacement, RegStorage r_src, VolatileKind is_volatile) 89 LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale, 91 LIR* StoreRefIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale) OVERRIDE; 209 LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src) OVERRIDE; 215 void OpRegCopy(RegStorage r_dest, RegStorage r_src) OVERRIDE; 216 LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) OVERRIDE; 220 LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) OVERRIDE; 221 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) OVERRIDE; 380 LIR* StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src, OpSize size) [all...] |
int_arm64.cc | 301 LIR* Arm64Mir2Lir::OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) { 303 bool src_is_fp = r_src.IsFloat(); 309 DCHECK_EQ(r_dest.Is64Bit(), r_src.Is64Bit()); 320 if (r_dest.Is64Bit() && r_src.Is64Bit()) { 326 bool src_is_double = r_src.IsDouble(); 340 r_src = Check32BitReg(r_src); 344 if (r_src.IsDouble()) { 353 res = RawLIR(current_dalvik_offset_, opcode, r_dest.GetReg(), r_src.GetReg()); 355 if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && r_dest == r_src) { [all...] |
/external/libnl/lib/route/ |
rule.c | 52 nl_addr_put(rule->r_src); 61 if (src->r_src) 62 if (!(dst->r_src = nl_addr_clone(src->r_src))) 117 if (!(rule->r_src = nl_addr_alloc_attr(tb[RTA_SRC], family))) 119 nl_addr_set_prefixlen(rule->r_src, r->rtm_src_len); 182 nl_addr2str(r->r_src, buf, sizeof(buf))); 248 nl_addr2str(rule->r_src, buf, sizeof(buf))); 295 diff |= RULE_DIFF(SRC, nl_addr_cmp(a->r_src, b->r_src)); [all...] |
/art/compiler/dex/quick/ |
mir_to_lir.h | [all...] |
gen_common.cc | 443 RegStorage r_src = AllocTempRef(); local 464 OpRegRegImm(kOpAdd, r_src, TargetPtrReg(kSp), SRegOffset(rl_first.s_reg_low)); 475 LoadBaseIndexed(r_src, r_idx, r_val, 2, k32); [all...] |
/external/libnl/include/ |
netlink-types.h | 295 struct nl_addr *r_src; member in struct:rtnl_rule
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