/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
SIRegisterInfo.cpp | 21 const TargetInstrInfo &tii) 22 : AMDGPURegisterInfo(tm, tii), 24 TII(tii)
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AMDGPURegisterInfo.cpp | 20 const TargetInstrInfo &tii) 23 TII(tii)
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SIRegisterInfo.h | 28 const TargetInstrInfo &TII; 30 SIRegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii);
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R600RegisterInfo.h | 28 const TargetInstrInfo &TII; 30 R600RegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii);
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AMDGPURegisterInfo.h | 33 const TargetInstrInfo &TII; 36 AMDGPURegisterInfo(TargetMachine &tm, const TargetInstrInfo &tii);
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R600RegisterInfo.cpp | 21 const TargetInstrInfo &tii) 22 : AMDGPURegisterInfo(tm, tii), 24 TII(tii)
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AMDILCFGStructurizer.cpp | 1903 const AMDGPUInstrInfo *tii = local 3013 const TargetInstrInfo *tii = passRep->getTargetInstrInfo(); local 3036 const TargetInstrInfo *tii = passRep->getTargetInstrInfo(); local 3050 const TargetInstrInfo *tii = passRep->getTargetInstrInfo(); local 3068 const TargetInstrInfo *tii = passRep->getTargetInstrInfo(); local 3088 const TargetInstrInfo *tii = passRep->getTargetInstrInfo(); local 3104 const TargetInstrInfo *tii = passRep->getTargetInstrInfo(); local 3119 const AMDGPUInstrInfo *tii = local 3132 const AMDGPUInstrInfo *tii = local 3152 const AMDGPUInstrInfo *tii = local [all...] |
/external/mesa3d/src/gallium/drivers/radeon/ |
SIRegisterInfo.cpp | 21 const TargetInstrInfo &tii) 22 : AMDGPURegisterInfo(tm, tii), 24 TII(tii)
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AMDGPURegisterInfo.cpp | 20 const TargetInstrInfo &tii) 23 TII(tii)
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SIRegisterInfo.h | 28 const TargetInstrInfo &TII; 30 SIRegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii);
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R600RegisterInfo.h | 28 const TargetInstrInfo &TII; 30 R600RegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii);
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AMDGPURegisterInfo.h | 33 const TargetInstrInfo &TII; 36 AMDGPURegisterInfo(TargetMachine &tm, const TargetInstrInfo &tii);
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R600RegisterInfo.cpp | 21 const TargetInstrInfo &tii) 22 : AMDGPURegisterInfo(tm, tii), 24 TII(tii)
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AMDILCFGStructurizer.cpp | 1903 const AMDGPUInstrInfo *tii = local 3013 const TargetInstrInfo *tii = passRep->getTargetInstrInfo(); local 3036 const TargetInstrInfo *tii = passRep->getTargetInstrInfo(); local 3050 const TargetInstrInfo *tii = passRep->getTargetInstrInfo(); local 3068 const TargetInstrInfo *tii = passRep->getTargetInstrInfo(); local 3088 const TargetInstrInfo *tii = passRep->getTargetInstrInfo(); local 3104 const TargetInstrInfo *tii = passRep->getTargetInstrInfo(); local 3119 const AMDGPUInstrInfo *tii = local 3132 const AMDGPUInstrInfo *tii = local 3152 const AMDGPUInstrInfo *tii = local [all...] |
/external/llvm/lib/CodeGen/ |
Spiller.cpp | 58 const TargetInstrInfo *tii; member in class:__anon5376::SpillerBase 68 tii = mf.getTarget().getInstrInfo(); 136 tii->loadRegFromStackSlot(*mi->getParent(), miItr, NewVReg, ss, trc, 145 tii->storeRegToStackSlot(*mi->getParent(), std::next(miItr), NewVReg,
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BranchFolding.h | 29 const TargetInstrInfo *tii, 90 const TargetInstrInfo *TII;
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TargetSchedule.cpp | 56 const TargetInstrInfo *tii) { 59 TII = tii; 81 return (UOps >= 0) ? UOps : TII->getNumMicroOps(&InstrItins, MI); 160 return TII->defaultDefLatency(&SchedModel, DefMI); 165 OperLatency = TII->getOperandLatency(&InstrItins, DefMI, DefOperIdx, 176 unsigned InstrLatency = TII->getInstrLatency(&InstrItins, DefMI); 179 // Rather than directly querying InstrItins stage latency, we call a TII 182 // special cases without TII hooks. 184 TII->defaultDefLatency(&SchedModel, DefMI)) [all...] |
RegAllocPBQP.cpp | 127 const TargetInstrInfo *tii; member in class:__anon5345::RegAllocPBQP 536 tii = tm->getInstrInfo();
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BranchFolding.cpp | 156 if (!TII->isUnpredicatedTerminator(I)) 183 const TargetInstrInfo *tii, 186 if (!tii) return false; 190 TII = tii; 207 if (!TII->AnalyzeBranch(*MBB, TBB, FBB, Cond, true)) 405 TII->ReplaceTailWithBranchTo(OldInst, NewDest); 419 if (!TII->isLegalToSplitMBBAt(CurMBB, BBI1)) 467 const TargetInstrInfo *TII) { 474 !TII->AnalyzeBranch(*CurMBB, TBB, FBB, Cond, true)) [all...] |
MachineScheduler.cpp | 374 const TargetInstrInfo *TII, 376 return MI->isCall() || TII->isSchedulingBoundary(MI, MBB, *MF); 381 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo(); 420 isSchedBoundary(std::prev(RegionEnd), MBB, MF, TII, IsPostRA)) { 431 if (isSchedBoundary(std::prev(I), MBB, MF, TII, IsPostRA)) [all...] |
/external/llvm/include/llvm/CodeGen/ |
TargetSchedule.h | 38 const TargetInstrInfo *TII; 44 TargetSchedModel(): STI(nullptr), TII(nullptr) {} 52 const TargetInstrInfo *tii); 58 const TargetInstrInfo *getInstrInfo() const { return TII; } 165 /// present this method falls back to TII->getInstrLatency with an empty
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/external/llvm/lib/Target/AArch64/ |
AArch64RegisterInfo.h | 30 const AArch64InstrInfo *TII; 34 AArch64RegisterInfo(const AArch64InstrInfo *tii, const AArch64Subtarget *sti);
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AArch64RegisterInfo.cpp | 36 AArch64RegisterInfo::AArch64RegisterInfo(const AArch64InstrInfo *tii, 38 : AArch64GenRegisterInfo(AArch64::LR), TII(tii), STI(sti) {} 294 const MCInstrDesc &MCID = TII->get(AArch64::ADDXri); 297 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF)); 315 bool Done = rewriteAArch64FrameIndex(MI, i, BaseReg, Off, TII); 348 if (rewriteAArch64FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII)) 359 emitFrameOffset(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, Offset, TII);
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/external/llvm/lib/CodeGen/SelectionDAG/ |
ScheduleDAGRRList.cpp | 278 const TargetInstrInfo *TII, 308 const MCInstrDesc Desc = TII->get(Opcode); 309 const TargetRegisterClass *RC = TII->getRegClass(Desc, Idx, TRI, MF); 410 const TargetInstrInfo *TII) { 420 if (IsChainDependent(N->getOperand(i).getNode(), Inner, NestLevel, TII)) 427 (unsigned)TII->getCallFrameDestroyOpcode()) { 430 (unsigned)TII->getCallFrameSetupOpcode()) { 460 const TargetInstrInfo *TII) { 472 MyNestLevel, MyMaxNest, TII)) 485 (unsigned)TII->getCallFrameDestroyOpcode()) [all...] |
/external/chromium_org/third_party/libjingle/source/talk/media/testdata/ |
voice.rtpdump | [all...] |