| /external/llvm/examples/Kaleidoscope/MCJIT/lazy/ |
| toy.cpp | 464 int Opc = CurTok;
467 return new UnaryExprAST(Opc, Operand);
[all...] |
| /external/llvm/include/llvm/TableGen/ |
| Record.h | 887 UnaryOp Opc;
890 UnOpInit(UnaryOp opc, Init *lhs, RecTy *Type)
891 : OpInit(IK_UnOpInit, Type), Opc(opc), LHS(lhs) {}
900 static UnOpInit *get(UnaryOp opc, Init *lhs, RecTy *Type);
915 UnaryOp getOpcode() const { return Opc; }
934 BinaryOp Opc;
937 BinOpInit(BinaryOp opc, Init *lhs, Init *rhs, RecTy *Type) :
938 OpInit(IK_BinOpInit, Type), Opc(opc), LHS(lhs), RHS(rhs) {
[all...] |
| /external/llvm/lib/Bitcode/Reader/ |
| BitcodeReader.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGISel.cpp | [all...] |
| TargetLowering.cpp | 618 unsigned Opc = ISD::SHL;
622 Opc = ISD::SRL;
628 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
707 unsigned Opc = ISD::SRL;
711 Opc = ISD::SHL;
716 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
[all...] |
| LegalizeIntegerTypes.cpp | 318 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
319 SDValue Result = DAG.getNode(Opc, dl,
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64FastISel.cpp | 209 unsigned Opc;
212 Opc = AArch64::FMOVDi;
215 Opc = AArch64::FMOVSi;
218 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
234 unsigned Opc = is64bit ? AArch64::LDRDui : AArch64::LDRSui;
236 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
522 unsigned Opc;
533 Opc = UseUnscaled ? AArch64::LDURBBi : AArch64::LDRBBui;
538 Opc = UseUnscaled ? AArch64::LDURHHi : AArch64::LDRHHui;
543 Opc = UseUnscaled ? AArch64::LDURWi : AArch64::LDRWui
[all...] |
| AArch64ISelDAGToDAG.cpp | 140 SDNode *SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, bool isExt);
144 SDNode *SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
146 SDNode *SelectPostLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
148 SDNode *SelectLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
149 SDNode *SelectPostLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
151 SDNode *SelectStore(SDNode *N, unsigned NumVecs, unsigned Opc);
152 SDNode *SelectPostStore(SDNode *N, unsigned NumVecs, unsigned Opc);
153 SDNode *SelectStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
154 SDNode *SelectPostStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
209 static bool isOpcWithIntImmediate(const SDNode *N, unsigned Opc,
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMConstantIslandPass.cpp | 668 int Opc = I->getOpcode();
673 int UOpc = Opc;
674 switch (Opc) {
715 if (Opc == ARM::tPUSH || Opc == ARM::tPOP_RET)
718 if (Opc == ARM::CONSTPOOL_ENTRY)
733 switch (Opc) {
[all...] |
| ARMISelDAGToDAG.cpp | 113 bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc);
116 SDValue &Offset, SDValue &Opc);
118 SDValue &Opc) {
119 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_BASE;
123 SDValue &Opc) {
124 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_SHOP;
128 SDValue &Opc) {
129 SelectAddrMode2Worker(N, Base, Offset, Opc);
130 // return SelectAddrMode2ShOp(N, Base, Offset, Opc);
143 SDValue &Offset, SDValue &Opc);
[all...] |
| ARMLoadStoreOptimizer.cpp | 290 static bool isT1i32Load(unsigned Opc) {
291 return Opc == ARM::tLDRi;
294 static bool isT2i32Load(unsigned Opc) {
295 return Opc == ARM::t2LDRi12 || Opc == ARM::t2LDRi8;
298 static bool isi32Load(unsigned Opc) {
299 return Opc == ARM::LDRi12 || isT1i32Load(Opc) || isT2i32Load(Opc) ;
302 static bool isT1i32Store(unsigned Opc) {
[all...] |
| ARMBaseInstrInfo.cpp | 460 unsigned Opc = MI->getOpcode();
461 if (isUncondBranchOpcode(Opc)) {
462 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
582 unsigned Opc = MI->getOpcode();
583 switch (Opc) {
622 unsigned EntrySize = (Opc == ARM::t2TBB_JT)
623 ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4);
639 unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4;
641 if (Opc == ARM::t2TBB_JT && (NumEntries & 1)
[all...] |
| ARMFastISel.cpp | 476 unsigned Opc;
479 Opc = ARM::FCONSTD;
482 Opc = ARM::FCONSTS;
486 TII.get(Opc), DestReg).addImm(Imm));
501 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
505 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
520 unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16;
525 TII.get(Opc), ImmReg)
536 unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi;
539 TII.get(Opc), ImmReg
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCFastISel.cpp | 110 unsigned FastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm) override;
430 unsigned Opc;
454 Opc = Is32BitInt ? PPC::LBZ : PPC::LBZ8;
457 Opc = (IsZExt ?
462 Opc = (IsZExt ?
465 if ((Opc == PPC::LWA || Opc == PPC::LWA_32) && ((Addr.Offset & 3) != 0))
469 Opc = PPC::LD;
475 Opc = PPC::LFS;
478 Opc = FP64LoadOpc
[all...] |
| PPCISelDAGToDAG.cpp | 341 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
342 return N->getOpcode() == Opc
495 unsigned Opc;
524 Opc = PPC::CMPLW;
529 Opc = PPC::CMPLW;
536 Opc = PPC::CMPW;
567 Opc = PPC::CMPLD;
572 Opc = PPC::CMPLD;
579 Opc = PPC::CMPD;
582 Opc = PPC::FCMPUS
[all...] |
| PPCInstrInfo.cpp | 734 unsigned Opc;
736 Opc = PPC::OR;
738 Opc = PPC::OR8;
740 Opc = PPC::FMR;
742 Opc = PPC::MCRF;
744 Opc = PPC::VOR;
754 Opc = PPC::XXLOR;
756 Opc = PPC::XXLORf;
758 Opc = PPC::CROR;
762 const MCInstrDesc &MCID = get(Opc);
[all...] |
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | [all...] |
| SIInstrInfo.cpp | 81 unsigned Opc = I->getOpcode();
82 if (Opc != TargetOpcode::COPY && Opc != AMDGPU::S_MOV_B32)
[all...] |
| AMDGPUISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | 194 SDNode *SelectGather(SDNode *N, unsigned Opc);
195 SDNode *SelectAtomic64(SDNode *Node, unsigned Opc);
[all...] |
| X86FastISel.cpp | 92 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
367 unsigned Opc = 0;
373 Opc = X86::MOV8rm;
377 Opc = X86::MOV16rm;
381 Opc = X86::MOV32rm;
386 Opc = X86::MOV64rm;
391 Opc = Subtarget->hasAVX() ? X86::VMOVSSrm : X86::MOVSSrm;
394 Opc = X86::LD_Fp32m;
400 Opc = Subtarget->hasAVX() ? X86::VMOVSDrm : X86::MOVSDrm;
403 Opc = X86::LD_Fp64m
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineCasts.cpp | 176 unsigned Opc = I->getOpcode();
177 switch (Opc) {
191 Res = BinaryOperator::Create((Instruction::BinaryOps)Opc, LHS, RHS);
206 Opc == Instruction::SExt);
273 bool InstCombiner::ShouldOptimizeCast(Instruction::CastOps opc, const Value *V,
281 if (isEliminableCastPair(CI, opc, Ty, DL))
286 if (opc == Instruction::SExt && isa<CmpInst>(V) && Ty->isVectorTy())
300 if (Instruction::CastOps opc =
304 return CastInst::Create(opc, CSrc->getOperand(0), CI.getType());
358 unsigned Opc = I->getOpcode()
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| IndVarSimplify.cpp | 570 unsigned Opc = UseInstr->getOpcode();
573 if (Opc == Instruction::Call || Opc == Instruction::Ret)
576 if (Opc == Instruction::PHI) {
589 if (Opc != Instruction::Call && Opc != Instruction::Ret)
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 894 unsigned opc = ISD::ZERO_EXTEND; local
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
