| /external/chromium_org/v8/src/arm/ |
| disasm-arm.cc | 91 void FormatNeonMemory(int Rn, int align, int Rm);
303 if (format[1] == 'n') { // 'rn: Rn register
416 void Decoder::FormatNeonMemory(int Rn, int align, int Rm) {
418 "[r%d", Rn);
712 // Rn field to encode it.
713 Format(instr, "mul'cond's 'rn, 'rm, 'rs");
717 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the
718 // Rn field to encode the Rd register and the Rd field to encode
719 // the Rn register
[all...] |
| simulator-arm.cc | 754 FPSCR_rounding_mode_ = RN;
1532 int rn = instr->RnValue(); local
2009 int rn = instr->RnValue(); local
2086 int rn = instr->RnValue(); local
2267 int rn = instr->RnValue(); local
2490 int rn = instr->RnValue(); local
2554 int rn = instr->RnValue(); local
3346 int rn = instr->RnValue(); local
3383 int rn = instr->RnValue(); local
3403 int rn = instr->RnValue(); local
[all...] |
| /external/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.cpp | 670 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
675 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
678 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
[all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | [all...] |
| /art/disassembler/ |
| disassembler_arm.cc | 311 ArmRegister rn(instruction, 16);
312 if (rn.r == 0xf) {
318 args << "[" << rn << ", #" << offset << "]";
320 args << "[" << rn << ", #" << offset << "]!";
322 args << "[" << rn << "], #" << offset;
326 if (rn.r == 9) {
467 // |111|01|00|op|0|WL| Rn | |
476 ArmRegister Rn(instr, 16);
481 args << Rn << (W == 0 ? "" : "!") << ", ";
483 if (Rn.r != 13)
[all...] |
| /system/core/libpixelflinger/tests/arch-arm64/assembler/ |
| arm64_assembler_test.cpp | 415 uint32_t Rn = 1, uint32_t Rm = 2, uint32_t Rs = 3)
429 regs[Rn] = test.RnValue;
450 case INSTR_ADD: a64asm->ADD(test.cond, test.setFlags, Rd,Rn,op2); break;
451 case INSTR_SUB: a64asm->SUB(test.cond, test.setFlags, Rd,Rn,op2); break;
452 case INSTR_RSB: a64asm->RSB(test.cond, test.setFlags, Rd,Rn,op2); break;
453 case INSTR_AND: a64asm->AND(test.cond, test.setFlags, Rd,Rn,op2); break;
454 case INSTR_ORR: a64asm->ORR(test.cond, test.setFlags, Rd,Rn,op2); break;
455 case INSTR_BIC: a64asm->BIC(test.cond, test.setFlags, Rd,Rn,op2); break;
457 case INSTR_MLA: a64asm->MLA(test.cond, test.setFlags, Rd,Rm,Rs,Rn); break;
458 case INSTR_CMP: a64asm->CMP(test.cond, Rn,op2); break
[all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | [all...] |
| /external/qemu/disas/ |
| arm.c | 1746 int rn = (given >> 16) & 0xf; local
2075 const char *rn = arm_regnames [(given >> 16) & 0xf]; local
2288 int rn = ((given >> 16) & 0xf); local
2318 int rn = ((given >> 16) & 0xf); local
2393 int rn = ((given >> 16) & 0xf); local
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | [all...] |
| /external/lldb/source/Plugins/Instruction/ARM/ |
| EmulateInstructionARM.cpp | 943 // d = UInt(Rdm); n = UInt(Rn); m = UInt(Rdm); setflags = !InITBlock();
956 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = FALSE;
969 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = (S == '1');
[all...] |
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | [all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
