| /external/clang/test/CodeGen/ |
| mips-vector-arg.c | 9 typedef int v4i32 __attribute__ ((__vector_size__ (16))); typedef
24 extern test_v4i32_2(v4i32, int, v4i32);
25 void test_v4i32(v4i32 a1, int a2, v4i32 a3) {
|
| mips-inline-asm-modifiers.c | 8 typedef int v4i32 __attribute__((vector_size(16))); typedef
17 v4i32 v4i32_r;
|
| mips-vector-return.c | 9 typedef int v4i32 __attribute__ ((__vector_size__ (16))); typedef
28 v4i32 test_v4i32(int a) {
29 return (v4i32){0, a, 0, 0};
|
| compound-literal.c | 6 typedef int v4i32 __attribute((vector_size(16))); typedef
7 v4i32 *y = &(v4i32){1,2,3,4};
|
| x86_32-arguments-darwin.c | 224 typedef int v4i32 __attribute__((__vector_size__(16))); typedef
228 v4i32 f55(v4i32 arg) { return arg+arg; }
|
| builtins-mips-msa.c | 7 typedef signed int v4i32 __attribute__ ((vector_size(16))); typedef
24 v4i32 v4i32_a = (v4i32) {0, 1, 2, 3};
25 v4i32 v4i32_b = (v4i32) {1, 2, 3, 4};
26 v4i32 v4i32_r;
[all...] |
| /prebuilts/gcc/darwin-x86/mips/mips64el-linux-android-4.9/lib/gcc/mips64el-linux-android/4.9/include/ |
| msa.h | 39 typedef int v4i32 __attribute__((vector_size(16), aligned(16))); typedef
57 extern v4i32 __builtin_msa_sll_w(v4i32, v4i32);
65 extern v4i32 __builtin_msa_slli_w(v4i32, unsigned char);
73 extern v4i32 __builtin_msa_sra_w(v4i32, v4i32);
81 extern v4i32 __builtin_msa_srai_w(v4i32, unsigned char)
[all...] |
| /prebuilts/gcc/linux-x86/mips/mips64el-linux-android-4.9/lib/gcc/mips64el-linux-android/4.9/include/ |
| msa.h | 39 typedef int v4i32 __attribute__((vector_size(16), aligned(16))); typedef
57 extern v4i32 __builtin_msa_sll_w(v4i32, v4i32);
65 extern v4i32 __builtin_msa_slli_w(v4i32, unsigned char);
73 extern v4i32 __builtin_msa_sra_w(v4i32, v4i32);
81 extern v4i32 __builtin_msa_srai_w(v4i32, unsigned char)
[all...] |
| /external/llvm/lib/Target/R600/ |
| SITypeRewriter.cpp | 38 Type *v4i32; member in class:__anon9828::SITypeRewriter
59 v4i32 = VectorType::get(Type::getInt32Ty(M.getContext()), 4);
88 PointerType::get(v4i32,PtrTy->getPointerAddressSpace()));
112 Args.push_back(Builder.CreateBitCast(Arg, v4i32));
113 Types.push_back(v4i32);
115 Name = Name + ".v4i32";
148 if (I.getDestTy() != v4i32) {
153 if (Op->getSrcTy() == v4i32) {
|
| R600ISelLowering.cpp | 37 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
66 setOperationAction(ISD::SETCC, MVT::v4i32, Expand);
89 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
110 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Expand);
118 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
132 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
137 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
142 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
147 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
[all...] |
| AMDGPUISelLowering.cpp | 146 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
162 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
169 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom);
173 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
192 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
206 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
213 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
284 MVT::v2i32, MVT::v4i32
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 208 { ISD::SHL, MVT::v4i32, 1 },
209 { ISD::SRL, MVT::v4i32, 1 },
210 { ISD::SRA, MVT::v4i32, 1 },
261 { ISD::SHL, MVT::v4i32, 1 }, // pslld
266 { ISD::SRL, MVT::v4i32, 1 }, // psrld.
271 { ISD::SRA, MVT::v4i32, 1 }, // psrad.
275 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence
276 { ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence
282 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41())
294 (VT == MVT::v4i32 && ST->hasSSE41())
[all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 215 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
216 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
219 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 },
220 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 },
239 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
240 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
263 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 },
264 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 },
459 {ISD::VECTOR_SHUFFLE, MVT::v4i32, 2},
482 {ISD::VECTOR_SHUFFLE, MVT::v4i32, 2}
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineValueType.h | 80 v4i32 = 34, // 4 x i32 enumerator in enum:llvm::MVT::SimpleValueType
212 SimpleTy == MVT::v4i32 || SimpleTy == MVT::v2i64 ||
289 case v4i32:
338 case v4i32:
411 case v4i32:
537 if (NumElements == 4) return MVT::v4i32;
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | 467 case MVT::v4i32:
494 case MVT::v4i32:
505 case MVT::v4i32:
[all...] |
| AArch64TargetTransformInfo.cpp | 309 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
312 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
340 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 },
343 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 },
|
| AArch64ISelLowering.cpp | 114 addQRTypeForNEON(MVT::v4i32);
437 setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Legal);
556 addTypeForNEON(VT, MVT::v4i32);
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 62 (int)MVT::v4i32,
90 (int)MVT::v4i32,
504 INTTY = MVT::v4i32;
651 INTTY = MVT::v4i32;
669 INTTY = MVT::v4i32;
|
| R600GenRegisterInfo.pl | 97 def R600_Reg128 : RegisterClass<"AMDGPU", [v4f32, v4i32], 128, (add
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 62 (int)MVT::v4i32,
90 (int)MVT::v4i32,
504 INTTY = MVT::v4i32;
651 INTTY = MVT::v4i32;
669 INTTY = MVT::v4i32;
|
| R600GenRegisterInfo.pl | 97 def R600_Reg128 : RegisterClass<"AMDGPU", [v4f32, v4i32], 128, (add
|
| /external/llvm/lib/IR/ |
| ValueTypes.cpp | 152 case MVT::v4i32: return "v4i32";
220 case MVT::v4i32: return VectorType::get(Type::getInt32Ty(Context), 4);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 415 // We promote all non-typed operations to v4i32.
417 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
419 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
421 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
423 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
425 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
427 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
485 setOperationAction(ISD::AND , MVT::v4i32, Legal);
486 setOperationAction(ISD::OR , MVT::v4i32, Legal);
487 setOperationAction(ISD::XOR , MVT::v4i32, Legal)
[all...] |
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86InstComments.cpp | 96 DecodePSHUFMask(MVT::v4i32,
201 DecodeUNPCKHMask(MVT::v4i32, ShuffleMask);
274 DecodeUNPCKLMask(MVT::v4i32, ShuffleMask);
|
