1 //===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "MCTargetDesc/X86BaseInfo.h" 11 #include "MCTargetDesc/X86FixupKinds.h" 12 #include "llvm/ADT/StringSwitch.h" 13 #include "llvm/MC/MCAsmBackend.h" 14 #include "llvm/MC/MCAssembler.h" 15 #include "llvm/MC/MCELFObjectWriter.h" 16 #include "llvm/MC/MCExpr.h" 17 #include "llvm/MC/MCFixupKindInfo.h" 18 #include "llvm/MC/MCMachObjectWriter.h" 19 #include "llvm/MC/MCObjectWriter.h" 20 #include "llvm/MC/MCSectionCOFF.h" 21 #include "llvm/MC/MCSectionELF.h" 22 #include "llvm/MC/MCSectionMachO.h" 23 #include "llvm/Support/CommandLine.h" 24 #include "llvm/Support/ELF.h" 25 #include "llvm/Support/ErrorHandling.h" 26 #include "llvm/Support/MachO.h" 27 #include "llvm/Support/TargetRegistry.h" 28 #include "llvm/Support/raw_ostream.h" 29 using namespace llvm; 30 31 // Option to allow disabling arithmetic relaxation to workaround PR9807, which 32 // is useful when running bitwise comparison experiments on Darwin. We should be 33 // able to remove this once PR9807 is resolved. 34 static cl::opt<bool> 35 MCDisableArithRelaxation("mc-x86-disable-arith-relaxation", 36 cl::desc("Disable relaxation of arithmetic instruction for X86")); 37 38 static unsigned getFixupKindLog2Size(unsigned Kind) { 39 switch (Kind) { 40 default: 41 llvm_unreachable("invalid fixup kind!"); 42 case FK_PCRel_1: 43 case FK_SecRel_1: 44 case FK_Data_1: 45 return 0; 46 case FK_PCRel_2: 47 case FK_SecRel_2: 48 case FK_Data_2: 49 return 1; 50 case FK_PCRel_4: 51 case X86::reloc_riprel_4byte: 52 case X86::reloc_riprel_4byte_movq_load: 53 case X86::reloc_signed_4byte: 54 case X86::reloc_global_offset_table: 55 case FK_SecRel_4: 56 case FK_Data_4: 57 return 2; 58 case FK_PCRel_8: 59 case FK_SecRel_8: 60 case FK_Data_8: 61 case X86::reloc_global_offset_table8: 62 return 3; 63 } 64 } 65 66 namespace { 67 68 class X86ELFObjectWriter : public MCELFObjectTargetWriter { 69 public: 70 X86ELFObjectWriter(bool is64Bit, uint8_t OSABI, uint16_t EMachine, 71 bool HasRelocationAddend, bool foobar) 72 : MCELFObjectTargetWriter(is64Bit, OSABI, EMachine, HasRelocationAddend) {} 73 }; 74 75 class X86AsmBackend : public MCAsmBackend { 76 const StringRef CPU; 77 bool HasNopl; 78 const uint64_t MaxNopLength; 79 public: 80 X86AsmBackend(const Target &T, StringRef _CPU) 81 : MCAsmBackend(), CPU(_CPU), MaxNopLength(_CPU == "slm" ? 7 : 15) { 82 HasNopl = CPU != "generic" && CPU != "i386" && CPU != "i486" && 83 CPU != "i586" && CPU != "pentium" && CPU != "pentium-mmx" && 84 CPU != "i686" && CPU != "k6" && CPU != "k6-2" && CPU != "k6-3" && 85 CPU != "geode" && CPU != "winchip-c6" && CPU != "winchip2" && 86 CPU != "c3" && CPU != "c3-2"; 87 } 88 89 unsigned getNumFixupKinds() const override { 90 return X86::NumTargetFixupKinds; 91 } 92 93 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override { 94 const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = { 95 { "reloc_riprel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel }, 96 { "reloc_riprel_4byte_movq_load", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel}, 97 { "reloc_signed_4byte", 0, 4 * 8, 0}, 98 { "reloc_global_offset_table", 0, 4 * 8, 0} 99 }; 100 101 if (Kind < FirstTargetFixupKind) 102 return MCAsmBackend::getFixupKindInfo(Kind); 103 104 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 105 "Invalid kind!"); 106 return Infos[Kind - FirstTargetFixupKind]; 107 } 108 109 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, 110 uint64_t Value, bool IsPCRel) const override { 111 unsigned Size = 1 << getFixupKindLog2Size(Fixup.getKind()); 112 113 assert(Fixup.getOffset() + Size <= DataSize && 114 "Invalid fixup offset!"); 115 116 // Check that uppper bits are either all zeros or all ones. 117 // Specifically ignore overflow/underflow as long as the leakage is 118 // limited to the lower bits. This is to remain compatible with 119 // other assemblers. 120 assert(isIntN(Size * 8 + 1, Value) && 121 "Value does not fit in the Fixup field"); 122 123 for (unsigned i = 0; i != Size; ++i) 124 Data[Fixup.getOffset() + i] = uint8_t(Value >> (i * 8)); 125 } 126 127 bool mayNeedRelaxation(const MCInst &Inst) const override; 128 129 bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, 130 const MCRelaxableFragment *DF, 131 const MCAsmLayout &Layout) const override; 132 133 void relaxInstruction(const MCInst &Inst, MCInst &Res) const override; 134 135 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override; 136 }; 137 } // end anonymous namespace 138 139 static unsigned getRelaxedOpcodeBranch(unsigned Op) { 140 switch (Op) { 141 default: 142 return Op; 143 144 case X86::JAE_1: return X86::JAE_4; 145 case X86::JA_1: return X86::JA_4; 146 case X86::JBE_1: return X86::JBE_4; 147 case X86::JB_1: return X86::JB_4; 148 case X86::JE_1: return X86::JE_4; 149 case X86::JGE_1: return X86::JGE_4; 150 case X86::JG_1: return X86::JG_4; 151 case X86::JLE_1: return X86::JLE_4; 152 case X86::JL_1: return X86::JL_4; 153 case X86::JMP_1: return X86::JMP_4; 154 case X86::JNE_1: return X86::JNE_4; 155 case X86::JNO_1: return X86::JNO_4; 156 case X86::JNP_1: return X86::JNP_4; 157 case X86::JNS_1: return X86::JNS_4; 158 case X86::JO_1: return X86::JO_4; 159 case X86::JP_1: return X86::JP_4; 160 case X86::JS_1: return X86::JS_4; 161 } 162 } 163 164 static unsigned getRelaxedOpcodeArith(unsigned Op) { 165 switch (Op) { 166 default: 167 return Op; 168 169 // IMUL 170 case X86::IMUL16rri8: return X86::IMUL16rri; 171 case X86::IMUL16rmi8: return X86::IMUL16rmi; 172 case X86::IMUL32rri8: return X86::IMUL32rri; 173 case X86::IMUL32rmi8: return X86::IMUL32rmi; 174 case X86::IMUL64rri8: return X86::IMUL64rri32; 175 case X86::IMUL64rmi8: return X86::IMUL64rmi32; 176 177 // AND 178 case X86::AND16ri8: return X86::AND16ri; 179 case X86::AND16mi8: return X86::AND16mi; 180 case X86::AND32ri8: return X86::AND32ri; 181 case X86::AND32mi8: return X86::AND32mi; 182 case X86::AND64ri8: return X86::AND64ri32; 183 case X86::AND64mi8: return X86::AND64mi32; 184 185 // OR 186 case X86::OR16ri8: return X86::OR16ri; 187 case X86::OR16mi8: return X86::OR16mi; 188 case X86::OR32ri8: return X86::OR32ri; 189 case X86::OR32mi8: return X86::OR32mi; 190 case X86::OR64ri8: return X86::OR64ri32; 191 case X86::OR64mi8: return X86::OR64mi32; 192 193 // XOR 194 case X86::XOR16ri8: return X86::XOR16ri; 195 case X86::XOR16mi8: return X86::XOR16mi; 196 case X86::XOR32ri8: return X86::XOR32ri; 197 case X86::XOR32mi8: return X86::XOR32mi; 198 case X86::XOR64ri8: return X86::XOR64ri32; 199 case X86::XOR64mi8: return X86::XOR64mi32; 200 201 // ADD 202 case X86::ADD16ri8: return X86::ADD16ri; 203 case X86::ADD16mi8: return X86::ADD16mi; 204 case X86::ADD32ri8: return X86::ADD32ri; 205 case X86::ADD32mi8: return X86::ADD32mi; 206 case X86::ADD64ri8: return X86::ADD64ri32; 207 case X86::ADD64mi8: return X86::ADD64mi32; 208 209 // SUB 210 case X86::SUB16ri8: return X86::SUB16ri; 211 case X86::SUB16mi8: return X86::SUB16mi; 212 case X86::SUB32ri8: return X86::SUB32ri; 213 case X86::SUB32mi8: return X86::SUB32mi; 214 case X86::SUB64ri8: return X86::SUB64ri32; 215 case X86::SUB64mi8: return X86::SUB64mi32; 216 217 // CMP 218 case X86::CMP16ri8: return X86::CMP16ri; 219 case X86::CMP16mi8: return X86::CMP16mi; 220 case X86::CMP32ri8: return X86::CMP32ri; 221 case X86::CMP32mi8: return X86::CMP32mi; 222 case X86::CMP64ri8: return X86::CMP64ri32; 223 case X86::CMP64mi8: return X86::CMP64mi32; 224 225 // PUSH 226 case X86::PUSH32i8: return X86::PUSHi32; 227 case X86::PUSH16i8: return X86::PUSHi16; 228 case X86::PUSH64i8: return X86::PUSH64i32; 229 case X86::PUSH64i16: return X86::PUSH64i32; 230 } 231 } 232 233 static unsigned getRelaxedOpcode(unsigned Op) { 234 unsigned R = getRelaxedOpcodeArith(Op); 235 if (R != Op) 236 return R; 237 return getRelaxedOpcodeBranch(Op); 238 } 239 240 bool X86AsmBackend::mayNeedRelaxation(const MCInst &Inst) const { 241 // Branches can always be relaxed. 242 if (getRelaxedOpcodeBranch(Inst.getOpcode()) != Inst.getOpcode()) 243 return true; 244 245 if (MCDisableArithRelaxation) 246 return false; 247 248 // Check if this instruction is ever relaxable. 249 if (getRelaxedOpcodeArith(Inst.getOpcode()) == Inst.getOpcode()) 250 return false; 251 252 253 // Check if it has an expression and is not RIP relative. 254 bool hasExp = false; 255 bool hasRIP = false; 256 for (unsigned i = 0; i < Inst.getNumOperands(); ++i) { 257 const MCOperand &Op = Inst.getOperand(i); 258 if (Op.isExpr()) 259 hasExp = true; 260 261 if (Op.isReg() && Op.getReg() == X86::RIP) 262 hasRIP = true; 263 } 264 265 // FIXME: Why exactly do we need the !hasRIP? Is it just a limitation on 266 // how we do relaxations? 267 return hasExp && !hasRIP; 268 } 269 270 bool X86AsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, 271 uint64_t Value, 272 const MCRelaxableFragment *DF, 273 const MCAsmLayout &Layout) const { 274 // Relax if the value is too big for a (signed) i8. 275 return int64_t(Value) != int64_t(int8_t(Value)); 276 } 277 278 // FIXME: Can tblgen help at all here to verify there aren't other instructions 279 // we can relax? 280 void X86AsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const { 281 // The only relaxations X86 does is from a 1byte pcrel to a 4byte pcrel. 282 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode()); 283 284 if (RelaxedOp == Inst.getOpcode()) { 285 SmallString<256> Tmp; 286 raw_svector_ostream OS(Tmp); 287 Inst.dump_pretty(OS); 288 OS << "\n"; 289 report_fatal_error("unexpected instruction to relax: " + OS.str()); 290 } 291 292 Res = Inst; 293 Res.setOpcode(RelaxedOp); 294 } 295 296 /// \brief Write a sequence of optimal nops to the output, covering \p Count 297 /// bytes. 298 /// \return - true on success, false on failure 299 bool X86AsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const { 300 static const uint8_t Nops[10][10] = { 301 // nop 302 {0x90}, 303 // xchg %ax,%ax 304 {0x66, 0x90}, 305 // nopl (%[re]ax) 306 {0x0f, 0x1f, 0x00}, 307 // nopl 0(%[re]ax) 308 {0x0f, 0x1f, 0x40, 0x00}, 309 // nopl 0(%[re]ax,%[re]ax,1) 310 {0x0f, 0x1f, 0x44, 0x00, 0x00}, 311 // nopw 0(%[re]ax,%[re]ax,1) 312 {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00}, 313 // nopl 0L(%[re]ax) 314 {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00}, 315 // nopl 0L(%[re]ax,%[re]ax,1) 316 {0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00}, 317 // nopw 0L(%[re]ax,%[re]ax,1) 318 {0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00}, 319 // nopw %cs:0L(%[re]ax,%[re]ax,1) 320 {0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00}, 321 }; 322 323 // This CPU doesn't support long nops. If needed add more. 324 // FIXME: Can we get this from the subtarget somehow? 325 // FIXME: We could generated something better than plain 0x90. 326 if (!HasNopl) { 327 for (uint64_t i = 0; i < Count; ++i) 328 OW->Write8(0x90); 329 return true; 330 } 331 332 // 15 is the longest single nop instruction. Emit as many 15-byte nops as 333 // needed, then emit a nop of the remaining length. 334 do { 335 const uint8_t ThisNopLength = (uint8_t) std::min(Count, MaxNopLength); 336 const uint8_t Prefixes = ThisNopLength <= 10 ? 0 : ThisNopLength - 10; 337 for (uint8_t i = 0; i < Prefixes; i++) 338 OW->Write8(0x66); 339 const uint8_t Rest = ThisNopLength - Prefixes; 340 for (uint8_t i = 0; i < Rest; i++) 341 OW->Write8(Nops[Rest - 1][i]); 342 Count -= ThisNopLength; 343 } while (Count != 0); 344 345 return true; 346 } 347 348 /* *** */ 349 350 namespace { 351 352 class ELFX86AsmBackend : public X86AsmBackend { 353 public: 354 uint8_t OSABI; 355 ELFX86AsmBackend(const Target &T, uint8_t _OSABI, StringRef CPU) 356 : X86AsmBackend(T, CPU), OSABI(_OSABI) {} 357 }; 358 359 class ELFX86_32AsmBackend : public ELFX86AsmBackend { 360 public: 361 ELFX86_32AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU) 362 : ELFX86AsmBackend(T, OSABI, CPU) {} 363 364 MCObjectWriter *createObjectWriter(raw_ostream &OS) const override { 365 return createX86ELFObjectWriter(OS, /*IsELF64*/ false, OSABI, ELF::EM_386); 366 } 367 }; 368 369 class ELFX86_X32AsmBackend : public ELFX86AsmBackend { 370 public: 371 ELFX86_X32AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU) 372 : ELFX86AsmBackend(T, OSABI, CPU) {} 373 374 MCObjectWriter *createObjectWriter(raw_ostream &OS) const override { 375 return createX86ELFObjectWriter(OS, /*IsELF64*/ false, OSABI, 376 ELF::EM_X86_64); 377 } 378 }; 379 380 class ELFX86_64AsmBackend : public ELFX86AsmBackend { 381 public: 382 ELFX86_64AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU) 383 : ELFX86AsmBackend(T, OSABI, CPU) {} 384 385 MCObjectWriter *createObjectWriter(raw_ostream &OS) const override { 386 return createX86ELFObjectWriter(OS, /*IsELF64*/ true, OSABI, ELF::EM_X86_64); 387 } 388 }; 389 390 class WindowsX86AsmBackend : public X86AsmBackend { 391 bool Is64Bit; 392 393 public: 394 WindowsX86AsmBackend(const Target &T, bool is64Bit, StringRef CPU) 395 : X86AsmBackend(T, CPU) 396 , Is64Bit(is64Bit) { 397 } 398 399 MCObjectWriter *createObjectWriter(raw_ostream &OS) const override { 400 return createX86WinCOFFObjectWriter(OS, Is64Bit); 401 } 402 }; 403 404 namespace CU { 405 406 /// Compact unwind encoding values. 407 enum CompactUnwindEncodings { 408 /// [RE]BP based frame where [RE]BP is pused on the stack immediately after 409 /// the return address, then [RE]SP is moved to [RE]BP. 410 UNWIND_MODE_BP_FRAME = 0x01000000, 411 412 /// A frameless function with a small constant stack size. 413 UNWIND_MODE_STACK_IMMD = 0x02000000, 414 415 /// A frameless function with a large constant stack size. 416 UNWIND_MODE_STACK_IND = 0x03000000, 417 418 /// No compact unwind encoding is available. 419 UNWIND_MODE_DWARF = 0x04000000, 420 421 /// Mask for encoding the frame registers. 422 UNWIND_BP_FRAME_REGISTERS = 0x00007FFF, 423 424 /// Mask for encoding the frameless registers. 425 UNWIND_FRAMELESS_STACK_REG_PERMUTATION = 0x000003FF 426 }; 427 428 } // end CU namespace 429 430 class DarwinX86AsmBackend : public X86AsmBackend { 431 const MCRegisterInfo &MRI; 432 433 /// \brief Number of registers that can be saved in a compact unwind encoding. 434 enum { CU_NUM_SAVED_REGS = 6 }; 435 436 mutable unsigned SavedRegs[CU_NUM_SAVED_REGS]; 437 bool Is64Bit; 438 439 unsigned OffsetSize; ///< Offset of a "push" instruction. 440 unsigned PushInstrSize; ///< Size of a "push" instruction. 441 unsigned MoveInstrSize; ///< Size of a "move" instruction. 442 unsigned StackDivide; ///< Amount to adjust stack stize by. 443 protected: 444 /// \brief Implementation of algorithm to generate the compact unwind encoding 445 /// for the CFI instructions. 446 uint32_t 447 generateCompactUnwindEncodingImpl(ArrayRef<MCCFIInstruction> Instrs) const { 448 if (Instrs.empty()) return 0; 449 450 // Reset the saved registers. 451 unsigned SavedRegIdx = 0; 452 memset(SavedRegs, 0, sizeof(SavedRegs)); 453 454 bool HasFP = false; 455 456 // Encode that we are using EBP/RBP as the frame pointer. 457 uint32_t CompactUnwindEncoding = 0; 458 459 unsigned SubtractInstrIdx = Is64Bit ? 3 : 2; 460 unsigned InstrOffset = 0; 461 unsigned StackAdjust = 0; 462 unsigned StackSize = 0; 463 unsigned PrevStackSize = 0; 464 unsigned NumDefCFAOffsets = 0; 465 466 for (unsigned i = 0, e = Instrs.size(); i != e; ++i) { 467 const MCCFIInstruction &Inst = Instrs[i]; 468 469 switch (Inst.getOperation()) { 470 default: 471 // Any other CFI directives indicate a frame that we aren't prepared 472 // to represent via compact unwind, so just bail out. 473 return 0; 474 case MCCFIInstruction::OpDefCfaRegister: { 475 // Defines a frame pointer. E.g. 476 // 477 // movq %rsp, %rbp 478 // L0: 479 // .cfi_def_cfa_register %rbp 480 // 481 HasFP = true; 482 assert(MRI.getLLVMRegNum(Inst.getRegister(), true) == 483 (Is64Bit ? X86::RBP : X86::EBP) && "Invalid frame pointer!"); 484 485 // Reset the counts. 486 memset(SavedRegs, 0, sizeof(SavedRegs)); 487 StackAdjust = 0; 488 SavedRegIdx = 0; 489 InstrOffset += MoveInstrSize; 490 break; 491 } 492 case MCCFIInstruction::OpDefCfaOffset: { 493 // Defines a new offset for the CFA. E.g. 494 // 495 // With frame: 496 // 497 // pushq %rbp 498 // L0: 499 // .cfi_def_cfa_offset 16 500 // 501 // Without frame: 502 // 503 // subq $72, %rsp 504 // L0: 505 // .cfi_def_cfa_offset 80 506 // 507 PrevStackSize = StackSize; 508 StackSize = std::abs(Inst.getOffset()) / StackDivide; 509 ++NumDefCFAOffsets; 510 break; 511 } 512 case MCCFIInstruction::OpOffset: { 513 // Defines a "push" of a callee-saved register. E.g. 514 // 515 // pushq %r15 516 // pushq %r14 517 // pushq %rbx 518 // L0: 519 // subq $120, %rsp 520 // L1: 521 // .cfi_offset %rbx, -40 522 // .cfi_offset %r14, -32 523 // .cfi_offset %r15, -24 524 // 525 if (SavedRegIdx == CU_NUM_SAVED_REGS) 526 // If there are too many saved registers, we cannot use a compact 527 // unwind encoding. 528 return CU::UNWIND_MODE_DWARF; 529 530 unsigned Reg = MRI.getLLVMRegNum(Inst.getRegister(), true); 531 SavedRegs[SavedRegIdx++] = Reg; 532 StackAdjust += OffsetSize; 533 InstrOffset += PushInstrSize; 534 break; 535 } 536 } 537 } 538 539 StackAdjust /= StackDivide; 540 541 if (HasFP) { 542 if ((StackAdjust & 0xFF) != StackAdjust) 543 // Offset was too big for a compact unwind encoding. 544 return CU::UNWIND_MODE_DWARF; 545 546 // Get the encoding of the saved registers when we have a frame pointer. 547 uint32_t RegEnc = encodeCompactUnwindRegistersWithFrame(); 548 if (RegEnc == ~0U) return CU::UNWIND_MODE_DWARF; 549 550 CompactUnwindEncoding |= CU::UNWIND_MODE_BP_FRAME; 551 CompactUnwindEncoding |= (StackAdjust & 0xFF) << 16; 552 CompactUnwindEncoding |= RegEnc & CU::UNWIND_BP_FRAME_REGISTERS; 553 } else { 554 // If the amount of the stack allocation is the size of a register, then 555 // we "push" the RAX/EAX register onto the stack instead of adjusting the 556 // stack pointer with a SUB instruction. We don't support the push of the 557 // RAX/EAX register with compact unwind. So we check for that situation 558 // here. 559 if ((NumDefCFAOffsets == SavedRegIdx + 1 && 560 StackSize - PrevStackSize == 1) || 561 (Instrs.size() == 1 && NumDefCFAOffsets == 1 && StackSize == 2)) 562 return CU::UNWIND_MODE_DWARF; 563 564 SubtractInstrIdx += InstrOffset; 565 ++StackAdjust; 566 567 if ((StackSize & 0xFF) == StackSize) { 568 // Frameless stack with a small stack size. 569 CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IMMD; 570 571 // Encode the stack size. 572 CompactUnwindEncoding |= (StackSize & 0xFF) << 16; 573 } else { 574 if ((StackAdjust & 0x7) != StackAdjust) 575 // The extra stack adjustments are too big for us to handle. 576 return CU::UNWIND_MODE_DWARF; 577 578 // Frameless stack with an offset too large for us to encode compactly. 579 CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IND; 580 581 // Encode the offset to the nnnnnn value in the 'subl $nnnnnn, ESP' 582 // instruction. 583 CompactUnwindEncoding |= (SubtractInstrIdx & 0xFF) << 16; 584 585 // Encode any extra stack stack adjustments (done via push 586 // instructions). 587 CompactUnwindEncoding |= (StackAdjust & 0x7) << 13; 588 } 589 590 // Encode the number of registers saved. (Reverse the list first.) 591 std::reverse(&SavedRegs[0], &SavedRegs[SavedRegIdx]); 592 CompactUnwindEncoding |= (SavedRegIdx & 0x7) << 10; 593 594 // Get the encoding of the saved registers when we don't have a frame 595 // pointer. 596 uint32_t RegEnc = encodeCompactUnwindRegistersWithoutFrame(SavedRegIdx); 597 if (RegEnc == ~0U) return CU::UNWIND_MODE_DWARF; 598 599 // Encode the register encoding. 600 CompactUnwindEncoding |= 601 RegEnc & CU::UNWIND_FRAMELESS_STACK_REG_PERMUTATION; 602 } 603 604 return CompactUnwindEncoding; 605 } 606 607 private: 608 /// \brief Get the compact unwind number for a given register. The number 609 /// corresponds to the enum lists in compact_unwind_encoding.h. 610 int getCompactUnwindRegNum(unsigned Reg) const { 611 static const uint16_t CU32BitRegs[7] = { 612 X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0 613 }; 614 static const uint16_t CU64BitRegs[] = { 615 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 616 }; 617 const uint16_t *CURegs = Is64Bit ? CU64BitRegs : CU32BitRegs; 618 for (int Idx = 1; *CURegs; ++CURegs, ++Idx) 619 if (*CURegs == Reg) 620 return Idx; 621 622 return -1; 623 } 624 625 /// \brief Return the registers encoded for a compact encoding with a frame 626 /// pointer. 627 uint32_t encodeCompactUnwindRegistersWithFrame() const { 628 // Encode the registers in the order they were saved --- 3-bits per 629 // register. The list of saved registers is assumed to be in reverse 630 // order. The registers are numbered from 1 to CU_NUM_SAVED_REGS. 631 uint32_t RegEnc = 0; 632 for (int i = 0, Idx = 0; i != CU_NUM_SAVED_REGS; ++i) { 633 unsigned Reg = SavedRegs[i]; 634 if (Reg == 0) break; 635 636 int CURegNum = getCompactUnwindRegNum(Reg); 637 if (CURegNum == -1) return ~0U; 638 639 // Encode the 3-bit register number in order, skipping over 3-bits for 640 // each register. 641 RegEnc |= (CURegNum & 0x7) << (Idx++ * 3); 642 } 643 644 assert((RegEnc & 0x3FFFF) == RegEnc && 645 "Invalid compact register encoding!"); 646 return RegEnc; 647 } 648 649 /// \brief Create the permutation encoding used with frameless stacks. It is 650 /// passed the number of registers to be saved and an array of the registers 651 /// saved. 652 uint32_t encodeCompactUnwindRegistersWithoutFrame(unsigned RegCount) const { 653 // The saved registers are numbered from 1 to 6. In order to encode the 654 // order in which they were saved, we re-number them according to their 655 // place in the register order. The re-numbering is relative to the last 656 // re-numbered register. E.g., if we have registers {6, 2, 4, 5} saved in 657 // that order: 658 // 659 // Orig Re-Num 660 // ---- ------ 661 // 6 6 662 // 2 2 663 // 4 3 664 // 5 3 665 // 666 for (unsigned i = 0; i != CU_NUM_SAVED_REGS; ++i) { 667 int CUReg = getCompactUnwindRegNum(SavedRegs[i]); 668 if (CUReg == -1) return ~0U; 669 SavedRegs[i] = CUReg; 670 } 671 672 // Reverse the list. 673 std::reverse(&SavedRegs[0], &SavedRegs[CU_NUM_SAVED_REGS]); 674 675 uint32_t RenumRegs[CU_NUM_SAVED_REGS]; 676 for (unsigned i = CU_NUM_SAVED_REGS - RegCount; i < CU_NUM_SAVED_REGS; ++i){ 677 unsigned Countless = 0; 678 for (unsigned j = CU_NUM_SAVED_REGS - RegCount; j < i; ++j) 679 if (SavedRegs[j] < SavedRegs[i]) 680 ++Countless; 681 682 RenumRegs[i] = SavedRegs[i] - Countless - 1; 683 } 684 685 // Take the renumbered values and encode them into a 10-bit number. 686 uint32_t permutationEncoding = 0; 687 switch (RegCount) { 688 case 6: 689 permutationEncoding |= 120 * RenumRegs[0] + 24 * RenumRegs[1] 690 + 6 * RenumRegs[2] + 2 * RenumRegs[3] 691 + RenumRegs[4]; 692 break; 693 case 5: 694 permutationEncoding |= 120 * RenumRegs[1] + 24 * RenumRegs[2] 695 + 6 * RenumRegs[3] + 2 * RenumRegs[4] 696 + RenumRegs[5]; 697 break; 698 case 4: 699 permutationEncoding |= 60 * RenumRegs[2] + 12 * RenumRegs[3] 700 + 3 * RenumRegs[4] + RenumRegs[5]; 701 break; 702 case 3: 703 permutationEncoding |= 20 * RenumRegs[3] + 4 * RenumRegs[4] 704 + RenumRegs[5]; 705 break; 706 case 2: 707 permutationEncoding |= 5 * RenumRegs[4] + RenumRegs[5]; 708 break; 709 case 1: 710 permutationEncoding |= RenumRegs[5]; 711 break; 712 } 713 714 assert((permutationEncoding & 0x3FF) == permutationEncoding && 715 "Invalid compact register encoding!"); 716 return permutationEncoding; 717 } 718 719 public: 720 DarwinX86AsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef CPU, 721 bool Is64Bit) 722 : X86AsmBackend(T, CPU), MRI(MRI), Is64Bit(Is64Bit) { 723 memset(SavedRegs, 0, sizeof(SavedRegs)); 724 OffsetSize = Is64Bit ? 8 : 4; 725 MoveInstrSize = Is64Bit ? 3 : 2; 726 StackDivide = Is64Bit ? 8 : 4; 727 PushInstrSize = 1; 728 } 729 }; 730 731 class DarwinX86_32AsmBackend : public DarwinX86AsmBackend { 732 public: 733 DarwinX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI, 734 StringRef CPU) 735 : DarwinX86AsmBackend(T, MRI, CPU, false) {} 736 737 MCObjectWriter *createObjectWriter(raw_ostream &OS) const override { 738 return createX86MachObjectWriter(OS, /*Is64Bit=*/false, 739 MachO::CPU_TYPE_I386, 740 MachO::CPU_SUBTYPE_I386_ALL); 741 } 742 743 /// \brief Generate the compact unwind encoding for the CFI instructions. 744 uint32_t generateCompactUnwindEncoding( 745 ArrayRef<MCCFIInstruction> Instrs) const override { 746 return generateCompactUnwindEncodingImpl(Instrs); 747 } 748 }; 749 750 class DarwinX86_64AsmBackend : public DarwinX86AsmBackend { 751 const MachO::CPUSubTypeX86 Subtype; 752 public: 753 DarwinX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI, 754 StringRef CPU, MachO::CPUSubTypeX86 st) 755 : DarwinX86AsmBackend(T, MRI, CPU, true), Subtype(st) {} 756 757 MCObjectWriter *createObjectWriter(raw_ostream &OS) const override { 758 return createX86MachObjectWriter(OS, /*Is64Bit=*/true, 759 MachO::CPU_TYPE_X86_64, Subtype); 760 } 761 762 bool doesSectionRequireSymbols(const MCSection &Section) const override { 763 // Temporary labels in the string literals sections require symbols. The 764 // issue is that the x86_64 relocation format does not allow symbol + 765 // offset, and so the linker does not have enough information to resolve the 766 // access to the appropriate atom unless an external relocation is used. For 767 // non-cstring sections, we expect the compiler to use a non-temporary label 768 // for anything that could have an addend pointing outside the symbol. 769 // 770 // See <rdar://problem/4765733>. 771 const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section); 772 return SMO.getType() == MachO::S_CSTRING_LITERALS; 773 } 774 775 bool isSectionAtomizable(const MCSection &Section) const override { 776 const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section); 777 // Fixed sized data sections are uniqued, they cannot be diced into atoms. 778 switch (SMO.getType()) { 779 default: 780 return true; 781 782 case MachO::S_4BYTE_LITERALS: 783 case MachO::S_8BYTE_LITERALS: 784 case MachO::S_16BYTE_LITERALS: 785 case MachO::S_LITERAL_POINTERS: 786 case MachO::S_NON_LAZY_SYMBOL_POINTERS: 787 case MachO::S_LAZY_SYMBOL_POINTERS: 788 case MachO::S_MOD_INIT_FUNC_POINTERS: 789 case MachO::S_MOD_TERM_FUNC_POINTERS: 790 case MachO::S_INTERPOSING: 791 return false; 792 } 793 } 794 795 /// \brief Generate the compact unwind encoding for the CFI instructions. 796 uint32_t generateCompactUnwindEncoding( 797 ArrayRef<MCCFIInstruction> Instrs) const override { 798 return generateCompactUnwindEncodingImpl(Instrs); 799 } 800 }; 801 802 } // end anonymous namespace 803 804 MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T, 805 const MCRegisterInfo &MRI, 806 StringRef TT, 807 StringRef CPU) { 808 Triple TheTriple(TT); 809 810 if (TheTriple.isOSBinFormatMachO()) 811 return new DarwinX86_32AsmBackend(T, MRI, CPU); 812 813 if (TheTriple.isOSWindows() && !TheTriple.isOSBinFormatELF()) 814 return new WindowsX86AsmBackend(T, false, CPU); 815 816 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS()); 817 return new ELFX86_32AsmBackend(T, OSABI, CPU); 818 } 819 820 MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T, 821 const MCRegisterInfo &MRI, 822 StringRef TT, 823 StringRef CPU) { 824 Triple TheTriple(TT); 825 826 if (TheTriple.isOSBinFormatMachO()) { 827 MachO::CPUSubTypeX86 CS = 828 StringSwitch<MachO::CPUSubTypeX86>(TheTriple.getArchName()) 829 .Case("x86_64h", MachO::CPU_SUBTYPE_X86_64_H) 830 .Default(MachO::CPU_SUBTYPE_X86_64_ALL); 831 return new DarwinX86_64AsmBackend(T, MRI, CPU, CS); 832 } 833 834 if (TheTriple.isOSWindows() && !TheTriple.isOSBinFormatELF()) 835 return new WindowsX86AsmBackend(T, true, CPU); 836 837 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS()); 838 839 if (TheTriple.getEnvironment() == Triple::GNUX32) 840 return new ELFX86_X32AsmBackend(T, OSABI, CPU); 841 return new ELFX86_64AsmBackend(T, OSABI, CPU); 842 } 843
