xref: /external/lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp

//===-- EmulateInstructionARM.cpp -------------------------------*- C++ -*-===//
//
//                     The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//

#include <stdlib.h>

#include "EmulateInstructionARM.h"
#include "EmulationStateARM.h"
#include "lldb/Core/ArchSpec.h"
#include "lldb/Core/Address.h"
#include "lldb/Core/ConstString.h"
#include "lldb/Core/PluginManager.h"
#include "lldb/Core/Stream.h"
#include "lldb/Interpreter/OptionValueArray.h"
#include "lldb/Interpreter/OptionValueDictionary.h"
#include "lldb/Symbol/UnwindPlan.h"

#include "Plugins/Process/Utility/ARMDefines.h"
#include "Plugins/Process/Utility/ARMUtils.h"
#include "Utility/ARM_DWARF_Registers.h"

#include "llvm/Support/MathExtras.h" // for SignExtend32 template function
                                     // and countTrailingZeros function

using namespace lldb;
using namespace lldb_private;

// Convenient macro definitions.
#define APSR_C Bit32(m_opcode_cpsr, CPSR_C_POS)
#define APSR_V Bit32(m_opcode_cpsr, CPSR_V_POS)

#define AlignPC(pc_val) (pc_val & 0xFFFFFFFC)

//----------------------------------------------------------------------
//
// ITSession implementation
//
//----------------------------------------------------------------------

// A8.6.50
// Valid return values are {1, 2, 3, 4}, with 0 signifying an error condition.
static uint32_t
CountITSize (uint32_t ITMask) {
    // First count the trailing zeros of the IT mask.
    uint32_t TZ = llvm::countTrailingZeros(ITMask);
    if (TZ > 3)
    {
#ifdef LLDB_CONFIGURATION_DEBUG
        printf("Encoding error: IT Mask '0000'\n");
#endif
        return 0;
    }
    return (4 - TZ);
}

// Init ITState.  Note that at least one bit is always 1 in mask.
bool ITSession::InitIT(uint32_t bits7_0)
{
    ITCounter = CountITSize(Bits32(bits7_0, 3, 0));
    if (ITCounter == 0)
        return false;

    // A8.6.50 IT
    unsigned short FirstCond = Bits32(bits7_0, 7, 4);
    if (FirstCond == 0xF)
    {
#ifdef LLDB_CONFIGURATION_DEBUG
        printf("Encoding error: IT FirstCond '1111'\n");
#endif
        return false;
    }
    if (FirstCond == 0xE && ITCounter != 1)
    {
#ifdef LLDB_CONFIGURATION_DEBUG
        printf("Encoding error: IT FirstCond '1110' && Mask != '1000'\n");
#endif
        return false;
    }

    ITState = bits7_0;
    return true;
}

// Update ITState if necessary.
void ITSession::ITAdvance()
{
    //assert(ITCounter);
    --ITCounter;
    if (ITCounter == 0)
        ITState = 0;
    else
    {
        unsigned short NewITState4_0 = Bits32(ITState, 4, 0) << 1;
        SetBits32(ITState, 4, 0, NewITState4_0);
    }
}

// Return true if we're inside an IT Block.
bool ITSession::InITBlock()
{
    return ITCounter != 0;
}

// Return true if we're the last instruction inside an IT Block.
bool ITSession::LastInITBlock()
{
    return ITCounter == 1;
}

// Get condition bits for the current thumb instruction.
uint32_t ITSession::GetCond()
{
    if (InITBlock())
        return Bits32(ITState, 7, 4);
    else
        return COND_AL;
}

// ARM constants used during decoding
#define REG_RD          0
#define LDM_REGLIST     1
#define SP_REG          13
#define LR_REG          14
#define PC_REG          15
#define PC_REGLIST_BIT  0x8000

#define ARMv4     (1u << 0)
#define ARMv4T    (1u << 1)
#define ARMv5T    (1u << 2)
#define ARMv5TE   (1u << 3)
#define ARMv5TEJ  (1u << 4)
#define ARMv6     (1u << 5)
#define ARMv6K    (1u << 6)
#define ARMv6T2   (1u << 7)
#define ARMv7     (1u << 8)
#define ARMv7S    (1u << 9)
#define ARMv8     (1u << 10)
#define ARMvAll   (0xffffffffu)

#define ARMV4T_ABOVE  (ARMv4T|ARMv5T|ARMv5TE|ARMv5TEJ|ARMv6|ARMv6K|ARMv6T2|ARMv7|ARMv7S|ARMv8)
#define ARMV5_ABOVE   (ARMv5T|ARMv5TE|ARMv5TEJ|ARMv6|ARMv6K|ARMv6T2|ARMv7|ARMv7S|ARMv8)
#define ARMV5TE_ABOVE (ARMv5TE|ARMv5TEJ|ARMv6|ARMv6K|ARMv6T2|ARMv7|ARMv7S|ARMv8)
#define ARMV5J_ABOVE  (ARMv5TEJ|ARMv6|ARMv6K|ARMv6T2|ARMv7|ARMv7S|ARMv8)
#define ARMV6_ABOVE   (ARMv6|ARMv6K|ARMv6T2|ARMv7|ARMv7S|ARMv8)
#define ARMV6T2_ABOVE (ARMv6T2|ARMv7|ARMv7S|ARMv8)
#define ARMV7_ABOVE   (ARMv7|ARMv7S|ARMv8)

#define No_VFP  0
#define VFPv1   (1u << 1)
#define VFPv2   (1u << 2)
#define VFPv3   (1u << 3)
#define AdvancedSIMD (1u << 4)

#define VFPv1_ABOVE (VFPv1 | VFPv2 | VFPv3 | AdvancedSIMD)
#define VFPv2_ABOVE (VFPv2 | VFPv3 | AdvancedSIMD)
#define VFPv2v3     (VFPv2 | VFPv3)

//----------------------------------------------------------------------
//
// EmulateInstructionARM implementation
//
//----------------------------------------------------------------------

void
EmulateInstructionARM::Initialize ()
{
    PluginManager::RegisterPlugin (GetPluginNameStatic (),
                                   GetPluginDescriptionStatic (),
                                   CreateInstance);
}

void
EmulateInstructionARM::Terminate ()
{
    PluginManager::UnregisterPlugin (CreateInstance);
}

ConstString
EmulateInstructionARM::GetPluginNameStatic ()
{
    static ConstString g_name("arm");
    return g_name;
}

const char *
EmulateInstructionARM::GetPluginDescriptionStatic ()
{
    return "Emulate instructions for the ARM architecture.";
}

EmulateInstruction *
EmulateInstructionARM::CreateInstance (const ArchSpec &arch, InstructionType inst_type)
{
    if (EmulateInstructionARM::SupportsEmulatingIntructionsOfTypeStatic(inst_type))
    {
        if (arch.GetTriple().getArch() == llvm::Triple::arm)
        {
            std::unique_ptr<EmulateInstructionARM> emulate_insn_ap (new EmulateInstructionARM (arch));

            if (emulate_insn_ap.get())
                return emulate_insn_ap.release();
        }
        else if (arch.GetTriple().getArch() == llvm::Triple::thumb)
        {
            std::unique_ptr<EmulateInstructionARM> emulate_insn_ap (new EmulateInstructionARM (arch));

            if (emulate_insn_ap.get())
                return emulate_insn_ap.release();
        }
    }

    return NULL;
}

bool
EmulateInstructionARM::SetTargetTriple (const ArchSpec &arch)
{
    if (arch.GetTriple().getArch () == llvm::Triple::arm)
        return true;
    else if (arch.GetTriple().getArch () == llvm::Triple::thumb)
        return true;

    return false;
}

// Write "bits (32) UNKNOWN" to memory address "address".  Helper function for many ARM instructions.
bool
EmulateInstructionARM::WriteBits32UnknownToMemory (addr_t address)
{
    EmulateInstruction::Context context;
    context.type = EmulateInstruction::eContextWriteMemoryRandomBits;
    context.SetNoArgs ();

    uint32_t random_data = rand ();
    const uint32_t addr_byte_size = GetAddressByteSize();

    if (!MemAWrite (context, address, random_data, addr_byte_size))
        return false;

    return true;
}

// Write "bits (32) UNKNOWN" to register n.  Helper function for many ARM instructions.
bool
EmulateInstructionARM::WriteBits32Unknown (int n)
{
    EmulateInstruction::Context context;
    context.type = EmulateInstruction::eContextWriteRegisterRandomBits;
    context.SetNoArgs ();

    bool success;
    uint32_t data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);

    if (!success)
        return false;

    if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, data))
        return false;

    return true;
}

bool
EmulateInstructionARM::GetRegisterInfo (uint32_t reg_kind, uint32_t reg_num, RegisterInfo &reg_info)
{
    if (reg_kind == eRegisterKindGeneric)
    {
        switch (reg_num)
        {
            case LLDB_REGNUM_GENERIC_PC:    reg_kind = eRegisterKindDWARF; reg_num = dwarf_pc; break;
            case LLDB_REGNUM_GENERIC_SP:    reg_kind = eRegisterKindDWARF; reg_num = dwarf_sp; break;
            case LLDB_REGNUM_GENERIC_FP:    reg_kind = eRegisterKindDWARF; reg_num = dwarf_r7; break;
            case LLDB_REGNUM_GENERIC_RA:    reg_kind = eRegisterKindDWARF; reg_num = dwarf_lr; break;
            case LLDB_REGNUM_GENERIC_FLAGS: reg_kind = eRegisterKindDWARF; reg_num = dwarf_cpsr; break;
            default: return false;
        }
    }

    if (reg_kind == eRegisterKindDWARF)
        return GetARMDWARFRegisterInfo(reg_num, reg_info);
    return false;
}

uint32_t
EmulateInstructionARM::GetFramePointerRegisterNumber () const
{
    if (m_opcode_mode == eModeThumb)
    {
        switch (m_arch.GetTriple().getOS())
        {
            case llvm::Triple::Darwin:
            case llvm::Triple::MacOSX:
            case llvm::Triple::IOS:
                return 7;
            default:
                break;
        }
    }
    return 11;
}

uint32_t
EmulateInstructionARM::GetFramePointerDWARFRegisterNumber () const
{
    if (m_opcode_mode == eModeThumb)
    {
        switch (m_arch.GetTriple().getOS())
        {
            case llvm::Triple::Darwin:
            case llvm::Triple::MacOSX:
            case llvm::Triple::IOS:
                return dwarf_r7;
            default:
                break;
        }
    }
    return dwarf_r11;
}

// Push Multiple Registers stores multiple registers to the stack, storing to
// consecutive memory locations ending just below the address in SP, and updates
// SP to point to the start of the stored data.
bool
EmulateInstructionARM::EmulatePUSH (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    // ARM pseudo code...
    if (ConditionPassed())
    {
        EncodingSpecificOperations();
        NullCheckIfThumbEE(13);
        address = SP - 4*BitCount(registers);

        for (i = 0 to 14)
        {
            if (registers<i> == '1')
            {
                if i == 13 && i != LowestSetBit(registers) // Only possible for encoding A1
                    MemA[address,4] = bits(32) UNKNOWN;
                else
                    MemA[address,4] = R[i];
                address = address + 4;
            }
        }

        if (registers<15> == '1') // Only possible for encoding A1 or A2
            MemA[address,4] = PCStoreValue();

        SP = SP - 4*BitCount(registers);
    }
#endif

    bool conditional = false;
    bool success = false;
    if (ConditionPassed(opcode, &conditional))
    {
        const uint32_t addr_byte_size = GetAddressByteSize();
        const addr_t sp = ReadCoreReg (SP_REG, &success);
        if (!success)
            return false;
        uint32_t registers = 0;
        uint32_t Rt; // the source register
        switch (encoding) {
        case eEncodingT1:
            registers = Bits32(opcode, 7, 0);
            // The M bit represents LR.
            if (Bit32(opcode, 8))
                registers |= (1u << 14);
            // if BitCount(registers) < 1 then UNPREDICTABLE;
            if (BitCount(registers) < 1)
                return false;
            break;
        case eEncodingT2:
            // Ignore bits 15 & 13.
            registers = Bits32(opcode, 15, 0) & ~0xa000;
            // if BitCount(registers) < 2 then UNPREDICTABLE;
            if (BitCount(registers) < 2)
                return false;
            break;
        case eEncodingT3:
            Rt = Bits32(opcode, 15, 12);
            // if BadReg(t) then UNPREDICTABLE;
            if (BadReg(Rt))
                return false;
            registers = (1u << Rt);
            break;
        case eEncodingA1:
            registers = Bits32(opcode, 15, 0);
            // Instead of return false, let's handle the following case as well,
            // which amounts to pushing one reg onto the full descending stacks.
            // if BitCount(register_list) < 2 then SEE STMDB / STMFD;
            break;
        case eEncodingA2:
            Rt = Bits32(opcode, 15, 12);
            // if t == 13 then UNPREDICTABLE;
            if (Rt == dwarf_sp)
                return false;
            registers = (1u << Rt);
            break;
        default:
            return false;
        }
        addr_t sp_offset = addr_byte_size * BitCount (registers);
        addr_t addr = sp - sp_offset;
        uint32_t i;

        EmulateInstruction::Context context;
        if (conditional)
            context.type = EmulateInstruction::eContextRegisterStore;
        else
            context.type = EmulateInstruction::eContextPushRegisterOnStack;
        RegisterInfo reg_info;
        RegisterInfo sp_reg;
        GetRegisterInfo (eRegisterKindDWARF, dwarf_sp, sp_reg);
        for (i=0; i<15; ++i)
        {
            if (BitIsSet (registers, i))
            {
                GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + i, reg_info);
                context.SetRegisterToRegisterPlusOffset (reg_info, sp_reg, addr - sp);
                uint32_t reg_value = ReadCoreReg(i, &success);
                if (!success)
                    return false;
                if (!MemAWrite (context, addr, reg_value, addr_byte_size))
                    return false;
                addr += addr_byte_size;
            }
        }

        if (BitIsSet (registers, 15))
        {
            GetRegisterInfo (eRegisterKindDWARF, dwarf_pc, reg_info);
            context.SetRegisterToRegisterPlusOffset (reg_info, sp_reg, addr - sp);
            const uint32_t pc = ReadCoreReg(PC_REG, &success);
            if (!success)
                return false;
            if (!MemAWrite (context, addr, pc, addr_byte_size))
                return false;
        }

        context.type = EmulateInstruction::eContextAdjustStackPointer;
        context.SetImmediateSigned (-sp_offset);

        if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, sp - sp_offset))
            return false;
    }
    return true;
}

// Pop Multiple Registers loads multiple registers from the stack, loading from
// consecutive memory locations staring at the address in SP, and updates
// SP to point just above the loaded data.
bool
EmulateInstructionARM::EmulatePOP (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    // ARM pseudo code...
    if (ConditionPassed())
    {
        EncodingSpecificOperations(); NullCheckIfThumbEE(13);
        address = SP;
        for i = 0 to 14
            if registers<i> == '1' then
                R[i] = if UnalignedAllowed then MemU[address,4] else MemA[address,4]; address = address + 4;
        if registers<15> == '1' then
            if UnalignedAllowed then
                LoadWritePC(MemU[address,4]);
            else
                LoadWritePC(MemA[address,4]);
        if registers<13> == '0' then SP = SP + 4*BitCount(registers);
        if registers<13> == '1' then SP = bits(32) UNKNOWN;
    }
#endif

    bool success = false;

    bool conditional = false;
    if (ConditionPassed(opcode, &conditional))
    {
        const uint32_t addr_byte_size = GetAddressByteSize();
        const addr_t sp = ReadCoreReg (SP_REG, &success);
        if (!success)
            return false;
        uint32_t registers = 0;
        uint32_t Rt; // the destination register
        switch (encoding) {
        case eEncodingT1:
            registers = Bits32(opcode, 7, 0);
            // The P bit represents PC.
            if (Bit32(opcode, 8))
                registers |= (1u << 15);
            // if BitCount(registers) < 1 then UNPREDICTABLE;
            if (BitCount(registers) < 1)
                return false;
            break;
        case eEncodingT2:
            // Ignore bit 13.
            registers = Bits32(opcode, 15, 0) & ~0x2000;
            // if BitCount(registers) < 2 || (P == '1' && M == '1') then UNPREDICTABLE;
            if (BitCount(registers) < 2 || (Bit32(opcode, 15) && Bit32(opcode, 14)))
                return false;
            // if registers<15> == '1' && InITBlock() && !LastInITBlock() then UNPREDICTABLE;
            if (BitIsSet(registers, 15) && InITBlock() && !LastInITBlock())
                return false;
            break;
        case eEncodingT3:
            Rt = Bits32(opcode, 15, 12);
            // if t == 13 || (t == 15 && InITBlock() && !LastInITBlock()) then UNPREDICTABLE;
            if (Rt == 13)
                return false;
            if (Rt == 15 && InITBlock() && !LastInITBlock())
                return false;
            registers = (1u << Rt);
            break;
        case eEncodingA1:
            registers = Bits32(opcode, 15, 0);
            // Instead of return false, let's handle the following case as well,
            // which amounts to popping one reg from the full descending stacks.
            // if BitCount(register_list) < 2 then SEE LDM / LDMIA / LDMFD;

            // if registers<13> == '1' && ArchVersion() >= 7 then UNPREDICTABLE;
            if (BitIsSet(opcode, 13) && ArchVersion() >= ARMv7)
                return false;
            break;
        case eEncodingA2:
            Rt = Bits32(opcode, 15, 12);
            // if t == 13 then UNPREDICTABLE;
            if (Rt == dwarf_sp)
                return false;
            registers = (1u << Rt);
            break;
        default:
            return false;
        }
        addr_t sp_offset = addr_byte_size * BitCount (registers);
        addr_t addr = sp;
        uint32_t i, data;

        EmulateInstruction::Context context;
        if (conditional)
            context.type = EmulateInstruction::eContextRegisterLoad;
        else
            context.type = EmulateInstruction::eContextPopRegisterOffStack;

        RegisterInfo sp_reg;
        GetRegisterInfo (eRegisterKindDWARF, dwarf_sp, sp_reg);

        for (i=0; i<15; ++i)
        {
            if (BitIsSet (registers, i))
            {
                context.SetRegisterPlusOffset (sp_reg, addr - sp);
                data = MemARead(context, addr, 4, 0, &success);
                if (!success)
                    return false;
                if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + i, data))
                    return false;
                addr += addr_byte_size;
            }
        }

        if (BitIsSet (registers, 15))
        {
            context.SetRegisterPlusOffset (sp_reg, addr - sp);
            data = MemARead(context, addr, 4, 0, &success);
            if (!success)
                return false;
            // In ARMv5T and above, this is an interworking branch.
            if (!LoadWritePC(context, data))
                return false;
            //addr += addr_byte_size;
        }

        context.type = EmulateInstruction::eContextAdjustStackPointer;
        context.SetImmediateSigned (sp_offset);

        if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, sp + sp_offset))
            return false;
    }
    return true;
}

// Set r7 or ip to point to saved value residing within the stack.
// ADD (SP plus immediate)
bool
EmulateInstructionARM::EmulateADDRdSPImm (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    // ARM pseudo code...
    if (ConditionPassed())
    {
        EncodingSpecificOperations();
        (result, carry, overflow) = AddWithCarry(SP, imm32, '0');
        if d == 15 then
           ALUWritePC(result); // setflags is always FALSE here
        else
            R[d] = result;
            if setflags then
                APSR.N = result<31>;
                APSR.Z = IsZeroBit(result);
                APSR.C = carry;
                APSR.V = overflow;
    }
#endif

    bool success = false;

    if (ConditionPassed(opcode))
    {
        const addr_t sp = ReadCoreReg (SP_REG, &success);
        if (!success)
            return false;
        uint32_t Rd; // the destination register
        uint32_t imm32;
        switch (encoding) {
        case eEncodingT1:
            Rd = 7;
            imm32 = Bits32(opcode, 7, 0) << 2; // imm32 = ZeroExtend(imm8:'00', 32)
            break;
        case eEncodingA1:
            Rd = Bits32(opcode, 15, 12);
            imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
            break;
        default:
            return false;
        }
        addr_t sp_offset = imm32;
        addr_t addr = sp + sp_offset; // a pointer to the stack area

        EmulateInstruction::Context context;
        context.type = eContextSetFramePointer;
        RegisterInfo sp_reg;
        GetRegisterInfo (eRegisterKindDWARF, dwarf_sp, sp_reg);
        context.SetRegisterPlusOffset (sp_reg, sp_offset);

        if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rd, addr))
            return false;
    }
    return true;
}

// Set r7 or ip to the current stack pointer.
// MOV (register)
bool
EmulateInstructionARM::EmulateMOVRdSP (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    // ARM pseudo code...
    if (ConditionPassed())
    {
        EncodingSpecificOperations();
        result = R[m];
        if d == 15 then
            ALUWritePC(result); // setflags is always FALSE here
        else
            R[d] = result;
            if setflags then
                APSR.N = result<31>;
                APSR.Z = IsZeroBit(result);
                // APSR.C unchanged
                // APSR.V unchanged
    }
#endif

    bool success = false;

    if (ConditionPassed(opcode))
    {
        const addr_t sp = ReadCoreReg (SP_REG, &success);
        if (!success)
            return false;
        uint32_t Rd; // the destination register
        switch (encoding) {
        case eEncodingT1:
            Rd = 7;
            break;
        case eEncodingA1:
            Rd = 12;
            break;
        default:
            return false;
        }

        EmulateInstruction::Context context;
        if (Rd == GetFramePointerRegisterNumber())
            context.type = EmulateInstruction::eContextSetFramePointer;
        else
            context.type = EmulateInstruction::eContextRegisterPlusOffset;
        RegisterInfo sp_reg;
        GetRegisterInfo (eRegisterKindDWARF, dwarf_sp, sp_reg);
        context.SetRegisterPlusOffset (sp_reg, 0);

        if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rd, sp))
            return false;
    }
    return true;
}

// Move from high register (r8-r15) to low register (r0-r7).
// MOV (register)
bool
EmulateInstructionARM::EmulateMOVLowHigh (const uint32_t opcode, const ARMEncoding encoding)
{
    return EmulateMOVRdRm (opcode, encoding);
}

// Move from register to register.
// MOV (register)
bool
EmulateInstructionARM::EmulateMOVRdRm (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    // ARM pseudo code...
    if (ConditionPassed())
    {
        EncodingSpecificOperations();
        result = R[m];
        if d == 15 then
            ALUWritePC(result); // setflags is always FALSE here
        else
            R[d] = result;
            if setflags then
                APSR.N = result<31>;
                APSR.Z = IsZeroBit(result);
                // APSR.C unchanged
                // APSR.V unchanged
    }
#endif

    bool success = false;

    if (ConditionPassed(opcode))
    {
        uint32_t Rm; // the source register
        uint32_t Rd; // the destination register
        bool setflags;
        switch (encoding) {
        case eEncodingT1:
            Rd = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0);
            Rm = Bits32(opcode, 6, 3);
            setflags = false;
            if (Rd == 15 && InITBlock() && !LastInITBlock())
                return false;
            break;
        case eEncodingT2:
            Rd = Bits32(opcode, 2, 0);
            Rm = Bits32(opcode, 5, 3);
            setflags = true;
            if (InITBlock())
                return false;
            break;
        case eEncodingT3:
            Rd = Bits32(opcode, 11, 8);
            Rm = Bits32(opcode, 3, 0);
            setflags = BitIsSet(opcode, 20);
            // if setflags && (BadReg(d) || BadReg(m)) then UNPREDICTABLE;
            if (setflags && (BadReg(Rd) || BadReg(Rm)))
                return false;
            // if !setflags && (d == 15 || m == 15 || (d == 13 && m == 13)) then UNPREDICTABLE;
            if (!setflags && (Rd == 15 || Rm == 15 || (Rd == 13 && Rm == 13)))
                return false;
            break;
        case eEncodingA1:
            Rd = Bits32(opcode, 15, 12);
            Rm = Bits32(opcode, 3, 0);
            setflags = BitIsSet(opcode, 20);

            // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
            if (Rd == 15 && setflags)
                return EmulateSUBSPcLrEtc (opcode, encoding);
            break;
        default:
            return false;
        }
        uint32_t result = ReadCoreReg(Rm, &success);
        if (!success)
            return false;

        // The context specifies that Rm is to be moved into Rd.
        EmulateInstruction::Context context;
        context.type = EmulateInstruction::eContextRegisterLoad;
        RegisterInfo dwarf_reg;
        GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rm, dwarf_reg);
        context.SetRegister (dwarf_reg);

        if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags))
            return false;
    }
    return true;
}

// Move (immediate) writes an immediate value to the destination register.  It
// can optionally update the condition flags based on the value.
// MOV (immediate)
bool
EmulateInstructionARM::EmulateMOVRdImm (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    // ARM pseudo code...
    if (ConditionPassed())
    {
        EncodingSpecificOperations();
        result = imm32;
        if d == 15 then         // Can only occur for ARM encoding
            ALUWritePC(result); // setflags is always FALSE here
        else
            R[d] = result;
            if setflags then
                APSR.N = result<31>;
                APSR.Z = IsZeroBit(result);
                APSR.C = carry;
                // APSR.V unchanged
    }
#endif

    if (ConditionPassed(opcode))
    {
        uint32_t Rd; // the destination register
        uint32_t imm32; // the immediate value to be written to Rd
        uint32_t carry = 0; // the carry bit after ThumbExpandImm_C or ARMExpandImm_C.
                            // for setflags == false, this value is a don't care
                            // initialized to 0 to silence the static analyzer
        bool setflags;
        switch (encoding) {
            case eEncodingT1:
                Rd = Bits32(opcode, 10, 8);
                setflags = !InITBlock();
                imm32 = Bits32(opcode, 7, 0); // imm32 = ZeroExtend(imm8, 32)
                carry = APSR_C;

                break;

            case eEncodingT2:
                Rd = Bits32(opcode, 11, 8);
                setflags = BitIsSet(opcode, 20);
                imm32 = ThumbExpandImm_C(opcode, APSR_C, carry);
                if (BadReg(Rd))
                  return false;

                break;

            case eEncodingT3:
            {
                // d = UInt(Rd); setflags = FALSE; imm32 = ZeroExtend(imm4:i:imm3:imm8, 32);
                Rd = Bits32 (opcode, 11, 8);
                setflags = false;
                uint32_t imm4 = Bits32 (opcode, 19, 16);
                uint32_t imm3 = Bits32 (opcode, 14, 12);
                uint32_t i = Bit32 (opcode, 26);
                uint32_t imm8 = Bits32 (opcode, 7, 0);
                imm32 = (imm4 << 12) | (i << 11) | (imm3 << 8) | imm8;

                // if BadReg(d) then UNPREDICTABLE;
                if (BadReg (Rd))
                    return false;
            }
                break;

            case eEncodingA1:
                // d = UInt(Rd); setflags = (S == 1); (imm32, carry) = ARMExpandImm_C(imm12, APSR.C);
                Rd = Bits32 (opcode, 15, 12);
                setflags = BitIsSet (opcode, 20);
                imm32 = ARMExpandImm_C (opcode, APSR_C, carry);

                // if Rd == 1111 && S == 1 then SEE SUBS PC, LR and related instructions;
                if ((Rd == 15) && setflags)
                    return EmulateSUBSPcLrEtc (opcode, encoding);

                break;

            case eEncodingA2:
            {
                // d = UInt(Rd); setflags = FALSE; imm32 = ZeroExtend(imm4:imm12, 32);
                Rd = Bits32 (opcode, 15, 12);
                setflags = false;
                uint32_t imm4 = Bits32 (opcode, 19, 16);
                uint32_t imm12 = Bits32 (opcode, 11, 0);
                imm32 = (imm4 << 12) | imm12;

                // if d == 15 then UNPREDICTABLE;
                if (Rd == 15)
                    return false;
            }
                break;

            default:
                return false;
        }
        uint32_t result = imm32;

        // The context specifies that an immediate is to be moved into Rd.
        EmulateInstruction::Context context;
        context.type = EmulateInstruction::eContextImmediate;
        context.SetNoArgs ();

        if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
            return false;
    }
    return true;
}

// MUL multiplies two register values.  The least significant 32 bits of the result are written to the destination
// register.  These 32 bits do not depend on whether the source register values are considered to be signed values or
// unsigned values.
//
// Optionally, it can update the condition flags based on the result.  In the Thumb instruction set, this option is
// limited to only a few forms of the instruction.
bool
EmulateInstructionARM::EmulateMUL (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    if ConditionPassed() then
        EncodingSpecificOperations();
        operand1 = SInt(R[n]); // operand1 = UInt(R[n]) produces the same final results
        operand2 = SInt(R[m]); // operand2 = UInt(R[m]) produces the same final results
        result = operand1 * operand2;
        R[d] = result<31:0>;
        if setflags then
            APSR.N = result<31>;
            APSR.Z = IsZeroBit(result);
            if ArchVersion() == 4 then
                APSR.C = bit UNKNOWN;
            // else APSR.C unchanged
            // APSR.V always unchanged
#endif

    if (ConditionPassed(opcode))
    {
        uint32_t d;
        uint32_t n;
        uint32_t m;
        bool setflags;

        // EncodingSpecificOperations();
        switch (encoding)
        {
            case eEncodingT1:
                // d = UInt(Rdm); n = UInt(Rn); m = UInt(Rdm); setflags = !InITBlock();
                d = Bits32 (opcode, 2, 0);
                n = Bits32 (opcode, 5, 3);
                m = Bits32 (opcode, 2, 0);
                setflags = !InITBlock();

                // if ArchVersion() < 6 && d == n then UNPREDICTABLE;
                if ((ArchVersion() < ARMv6) && (d == n))
                    return false;

                break;

            case eEncodingT2:
                // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = FALSE;
                d = Bits32 (opcode, 11, 8);
                n = Bits32 (opcode, 19, 16);
                m = Bits32 (opcode, 3, 0);
                setflags = false;

                // if BadReg(d) || BadReg(n) || BadReg(m) then UNPREDICTABLE;
                if (BadReg (d) || BadReg (n) || BadReg (m))
                    return false;

                break;

            case eEncodingA1:
                // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = (S == '1');
                d = Bits32 (opcode, 19, 16);
                n = Bits32 (opcode, 3, 0);
                m = Bits32 (opcode, 11, 8);
                setflags = BitIsSet (opcode, 20);

                // if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;
                if ((d == 15) ||  (n == 15) || (m == 15))
                    return false;

                // if ArchVersion() < 6 && d == n then UNPREDICTABLE;
                if ((ArchVersion() < ARMv6) && (d == n))
                    return false;

                break;

            default:
                return false;
        }

        bool success = false;

        // operand1 = SInt(R[n]); // operand1 = UInt(R[n]) produces the same final results
        uint64_t operand1 = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
        if (!success)
            return false;

        // operand2 = SInt(R[m]); // operand2 = UInt(R[m]) produces the same final results
        uint64_t operand2 = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
        if (!success)
            return false;

        // result = operand1 * operand2;
        uint64_t result = operand1 * operand2;

        // R[d] = result<31:0>;
        RegisterInfo op1_reg;
        RegisterInfo op2_reg;
        GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, op1_reg);
        GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + m, op2_reg);

        EmulateInstruction::Context context;
        context.type = eContextArithmetic;
        context.SetRegisterRegisterOperands (op1_reg, op2_reg);

        if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + d, (0x0000ffff & result)))
            return false;

        // if setflags then
        if (setflags)
        {
            // APSR.N = result<31>;
            // APSR.Z = IsZeroBit(result);
            m_new_inst_cpsr = m_opcode_cpsr;
            SetBit32 (m_new_inst_cpsr, CPSR_N_POS, Bit32 (result, 31));
            SetBit32 (m_new_inst_cpsr, CPSR_Z_POS, result == 0 ? 1 : 0);
            if (m_new_inst_cpsr != m_opcode_cpsr)
            {
                if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_FLAGS, m_new_inst_cpsr))
                    return false;
            }

            // if ArchVersion() == 4 then
                // APSR.C = bit UNKNOWN;
        }
    }
    return true;
}

// Bitwise NOT (immediate) writes the bitwise inverse of an immediate value to the destination register.
// It can optionally update the condition flags based on the value.
bool
EmulateInstructionARM::EmulateMVNImm (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    // ARM pseudo code...
    if (ConditionPassed())
    {
        EncodingSpecificOperations();
        result = NOT(imm32);
        if d == 15 then         // Can only occur for ARM encoding
            ALUWritePC(result); // setflags is always FALSE here
        else
            R[d] = result;
            if setflags then
                APSR.N = result<31>;
                APSR.Z = IsZeroBit(result);
                APSR.C = carry;
                // APSR.V unchanged
    }
#endif

    if (ConditionPassed(opcode))
    {
        uint32_t Rd; // the destination register
        uint32_t imm32; // the output after ThumbExpandImm_C or ARMExpandImm_C
        uint32_t carry; // the carry bit after ThumbExpandImm_C or ARMExpandImm_C
        bool setflags;
        switch (encoding) {
        case eEncodingT1:
            Rd = Bits32(opcode, 11, 8);
            setflags = BitIsSet(opcode, 20);
            imm32 = ThumbExpandImm_C(opcode, APSR_C, carry);
            break;
        case eEncodingA1:
            Rd = Bits32(opcode, 15, 12);
            setflags = BitIsSet(opcode, 20);
            imm32 = ARMExpandImm_C(opcode, APSR_C, carry);

            // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
            if (Rd == 15 && setflags)
                return EmulateSUBSPcLrEtc (opcode, encoding);
            break;
        default:
            return false;
        }
        uint32_t result = ~imm32;

        // The context specifies that an immediate is to be moved into Rd.
        EmulateInstruction::Context context;
        context.type = EmulateInstruction::eContextImmediate;
        context.SetNoArgs ();

        if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
            return false;
    }
    return true;
}

// Bitwise NOT (register) writes the bitwise inverse of a register value to the destination register.
// It can optionally update the condition flags based on the result.
bool
EmulateInstructionARM::EmulateMVNReg (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    // ARM pseudo code...
    if (ConditionPassed())
    {
        EncodingSpecificOperations();
        (shifted, carry) = Shift_C(R[m], shift_t, shift_n, APSR.C);
        result = NOT(shifted);
        if d == 15 then         // Can only occur for ARM encoding
            ALUWritePC(result); // setflags is always FALSE here
        else
            R[d] = result;
            if setflags then
                APSR.N = result<31>;
                APSR.Z = IsZeroBit(result);
                APSR.C = carry;
                // APSR.V unchanged
    }
#endif

    if (ConditionPassed(opcode))
    {
        uint32_t Rm; // the source register
        uint32_t Rd; // the destination register
        ARM_ShifterType shift_t;
        uint32_t shift_n; // the shift applied to the value read from Rm
        bool setflags;
        uint32_t carry; // the carry bit after the shift operation
        switch (encoding) {
        case eEncodingT1:
            Rd = Bits32(opcode, 2, 0);
            Rm = Bits32(opcode, 5, 3);
            setflags = !InITBlock();
            shift_t = SRType_LSL;
            shift_n = 0;
            if (InITBlock())
                return false;
            break;
        case eEncodingT2:
            Rd = Bits32(opcode, 11, 8);
            Rm = Bits32(opcode, 3, 0);
            setflags = BitIsSet(opcode, 20);
            shift_n = DecodeImmShiftThumb(opcode, shift_t);
            // if (BadReg(d) || BadReg(m)) then UNPREDICTABLE;
            if (BadReg(Rd) || BadReg(Rm))
                return false;
            break;
        case eEncodingA1:
            Rd = Bits32(opcode, 15, 12);
            Rm = Bits32(opcode, 3, 0);
            setflags = BitIsSet(opcode, 20);
            shift_n = DecodeImmShiftARM(opcode, shift_t);
            break;
        default:
            return false;
        }
        bool success = false;
        uint32_t value = ReadCoreReg(Rm, &success);
        if (!success)
            return false;

        uint32_t shifted = Shift_C(value, shift_t, shift_n, APSR_C, carry, &success);
        if (!success)
            return false;
        uint32_t result = ~shifted;

        // The context specifies that an immediate is to be moved into Rd.
        EmulateInstruction::Context context;
        context.type = EmulateInstruction::eContextImmediate;
        context.SetNoArgs ();

        if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
            return false;
    }
    return true;
}

// PC relative immediate load into register, possibly followed by ADD (SP plus register).
// LDR (literal)
bool
EmulateInstructionARM::EmulateLDRRtPCRelative (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    // ARM pseudo code...
    if (ConditionPassed())
    {
        EncodingSpecificOperations(); NullCheckIfThumbEE(15);
        base = Align(PC,4);
        address = if add then (base + imm32) else (base - imm32);
        data = MemU[address,4];
        if t == 15 then
            if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE;
        elsif UnalignedSupport() || address<1:0> = '00' then
            R[t] = data;
        else // Can only apply before ARMv7
            if CurrentInstrSet() == InstrSet_ARM then
                R[t] = ROR(data, 8*UInt(address<1:0>));
            else
                R[t] = bits(32) UNKNOWN;
    }
#endif

    if (ConditionPassed(opcode))
    {
        bool success = false;
        const uint32_t pc = ReadCoreReg(PC_REG, &success);
        if (!success)
            return false;

        // PC relative immediate load context
        EmulateInstruction::Context context;
        context.type = EmulateInstruction::eContextRegisterPlusOffset;
        RegisterInfo pc_reg;
        GetRegisterInfo (eRegisterKindDWARF, dwarf_pc, pc_reg);
        context.SetRegisterPlusOffset (pc_reg, 0);

        uint32_t Rt;    // the destination register
        uint32_t imm32; // immediate offset from the PC
        bool add;       // +imm32 or -imm32?
        addr_t base;    // the base address
        addr_t address; // the PC relative address
        uint32_t data;  // the literal data value from the PC relative load
        switch (encoding) {
        case eEncodingT1:
            Rt = Bits32(opcode, 10, 8);
            imm32 = Bits32(opcode, 7, 0) << 2; // imm32 = ZeroExtend(imm8:'00', 32);
            add = true;
            break;
        case eEncodingT2:
            Rt = Bits32(opcode, 15, 12);
            imm32 = Bits32(opcode, 11, 0) << 2; // imm32 = ZeroExtend(imm12, 32);
            add = BitIsSet(opcode, 23);
            if (Rt == 15 && InITBlock() && !LastInITBlock())
                return false;
            break;
        default:
            return false;
        }

        base = Align(pc, 4);
        if (add)
            address = base + imm32;
        else
            address = base - imm32;

        context.SetRegisterPlusOffset(pc_reg, address - base);
        data = MemURead(context, address, 4, 0, &success);
        if (!success)
            return false;

        if (Rt == 15)
        {
            if (Bits32(address, 1, 0) == 0)
            {
                // In ARMv5T and above, this is an interworking branch.
                if (!LoadWritePC(context, data))
                    return false;
            }
            else
                return false;
        }
        else if (UnalignedSupport() || Bits32(address, 1, 0) == 0)
        {
            if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rt, data))
                return false;
        }
        else // We don't handle ARM for now.
            return false;

    }
    return true;
}

// An add operation to adjust the SP.
// ADD (SP plus immediate)
bool
EmulateInstructionARM::EmulateADDSPImm (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    // ARM pseudo code...
    if (ConditionPassed())
    {
        EncodingSpecificOperations();
        (result, carry, overflow) = AddWithCarry(SP, imm32, '0');
        if d == 15 then // Can only occur for ARM encoding
            ALUWritePC(result); // setflags is always FALSE here
        else
            R[d] = result;
            if setflags then
                APSR.N = result<31>;
                APSR.Z = IsZeroBit(result);
                APSR.C = carry;
                APSR.V = overflow;
    }
#endif

    bool success = false;

    if (ConditionPassed(opcode))
    {
        const addr_t sp = ReadCoreReg (SP_REG, &success);
        if (!success)
            return false;
        uint32_t imm32; // the immediate operand
        uint32_t d;
        //bool setflags = false; // Add this back if/when support eEncodingT3 eEncodingA1
        switch (encoding)
        {
            case eEncodingT1:
                // d = UInt(Rd); setflags = FALSE; imm32 = ZeroExtend(imm8:'00', 32);
                d = Bits32 (opcode, 10, 8);
                imm32 = (Bits32 (opcode, 7, 0) << 2);

                break;

            case eEncodingT2:
                // d = 13; setflags = FALSE; imm32 = ZeroExtend(imm7:'00', 32);
                d = 13;
                imm32 = ThumbImm7Scaled(opcode); // imm32 = ZeroExtend(imm7:'00', 32)

                break;

            default:
                return false;
        }
        addr_t sp_offset = imm32;
        addr_t addr = sp + sp_offset; // the adjusted stack pointer value

        EmulateInstruction::Context context;
        context.type = EmulateInstruction::eContextAdjustStackPointer;
        RegisterInfo sp_reg;
        GetRegisterInfo (eRegisterKindDWARF, dwarf_sp, sp_reg);
        context.SetRegisterPlusOffset (sp_reg, sp_offset);

        if (d == 15)
        {
            if (!ALUWritePC (context, addr))
                return false;
        }
        else
        {
            if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + d, addr))
                return false;

            // Add this back if/when support eEncodingT3 eEncodingA1
            //if (setflags)
            //{
            //    APSR.N = result<31>;
            //    APSR.Z = IsZeroBit(result);
            //    APSR.C = carry;
            //    APSR.V = overflow;
            //}
        }
    }
    return true;
}

// An add operation to adjust the SP.
// ADD (SP plus register)
bool
EmulateInstructionARM::EmulateADDSPRm (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    // ARM pseudo code...
    if (ConditionPassed())
    {
        EncodingSpecificOperations();
        shifted = Shift(R[m], shift_t, shift_n, APSR.C);
        (result, carry, overflow) = AddWithCarry(SP, shifted, '0');
        if d == 15 then
            ALUWritePC(result); // setflags is always FALSE here
        else
            R[d] = result;
            if setflags then
                APSR.N = result<31>;
                APSR.Z = IsZeroBit(result);
                APSR.C = carry;
                APSR.V = overflow;
    }
#endif

    bool success = false;

    if (ConditionPassed(opcode))
    {
        const addr_t sp = ReadCoreReg (SP_REG, &success);
        if (!success)
            return false;
        uint32_t Rm; // the second operand
        switch (encoding) {
        case eEncodingT2:
            Rm = Bits32(opcode, 6, 3);
            break;
        default:
            return false;
        }
        int32_t reg_value = ReadCoreReg(Rm, &success);
        if (!success)
            return false;

        addr_t addr = (int32_t)sp + reg_value; // the adjusted stack pointer value

        EmulateInstruction::Context context;
        context.type = eContextArithmetic;
        RegisterInfo sp_reg;
        GetRegisterInfo (eRegisterKindDWARF, dwarf_sp, sp_reg);

        RegisterInfo other_reg;
        GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rm, other_reg);
        context.SetRegisterRegisterOperands (sp_reg, other_reg);

        if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, addr))
            return false;
    }
    return true;
}

// Branch with Link and Exchange Instruction Sets (immediate) calls a subroutine
// at a PC-relative address, and changes instruction set from ARM to Thumb, or
// from Thumb to ARM.
// BLX (immediate)
bool
EmulateInstructionARM::EmulateBLXImmediate (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    // ARM pseudo code...
    if (ConditionPassed())
    {
        EncodingSpecificOperations();
        if CurrentInstrSet() == InstrSet_ARM then
            LR = PC - 4;
        else
            LR = PC<31:1> : '1';
        if targetInstrSet == InstrSet_ARM then
            targetAddress = Align(PC,4) + imm32;
        else
            targetAddress = PC + imm32;
        SelectInstrSet(targetInstrSet);
        BranchWritePC(targetAddress);
    }
#endif

    bool success = true;

    if (ConditionPassed(opcode))
    {
        EmulateInstruction::Context context;
        context.type = EmulateInstruction::eContextRelativeBranchImmediate;
        const uint32_t pc = ReadCoreReg(PC_REG, &success);
        if (!success)
            return false;
        addr_t lr; // next instruction address
        addr_t target; // target address
        int32_t imm32; // PC-relative offset
        switch (encoding) {
        case eEncodingT1:
            {
            lr = pc | 1u; // return address
            uint32_t S = Bit32(opcode, 26);
            uint32_t imm10 = Bits32(opcode, 25, 16);
            uint32_t J1 = Bit32(opcode, 13);
            uint32_t J2 = Bit32(opcode, 11);
            uint32_t imm11 = Bits32(opcode, 10, 0);
            uint32_t I1 = !(J1 ^ S);
            uint32_t I2 = !(J2 ^ S);
            uint32_t imm25 = (S << 24) | (I1 << 23) | (I2 << 22) | (imm10 << 12) | (imm11 << 1);
            imm32 = llvm::SignExtend32<25>(imm25);
            target = pc + imm32;
            context.SetISAAndImmediateSigned (eModeThumb, 4 + imm32);
            if (InITBlock() && !LastInITBlock())
                return false;
            break;
            }
        case eEncodingT2:
            {
            lr = pc | 1u; // return address
            uint32_t S = Bit32(opcode, 26);
            uint32_t imm10H = Bits32(opcode, 25, 16);
            uint32_t J1 = Bit32(opcode, 13);
            uint32_t J2 = Bit32(opcode, 11);
            uint32_t imm10L = Bits32(opcode, 10, 1);
            uint32_t I1 = !(J1 ^ S);
            uint32_t I2 = !(J2 ^ S);
            uint32_t imm25 = (S << 24) | (I1 << 23) | (I2 << 22) | (imm10H << 12) | (imm10L << 2);
            imm32 = llvm::SignExtend32<25>(imm25);
            target = Align(pc, 4) + imm32;
            context.SetISAAndImmediateSigned (eModeARM, 4 + imm32);
            if (InITBlock() && !LastInITBlock())
                return false;
            break;
            }
        case eEncodingA1:
            lr = pc - 4; // return address
            imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2);
            target = Align(pc, 4) + imm32;
            context.SetISAAndImmediateSigned (eModeARM, 8 + imm32);
            break;
        case eEncodingA2:
            lr = pc - 4; // return address
            imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2 | Bits32(opcode, 24, 24) << 1);
            target = pc + imm32;
            context.SetISAAndImmediateSigned (eModeThumb, 8 + imm32);
            break;
        default:
            return false;
        }
        if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA, lr))
            return false;
        if (!BranchWritePC(context, target))
            return false;
    }
    return true;
}

// Branch with Link and Exchange (register) calls a subroutine at an address and
// instruction set specified by a register.
// BLX (register)
bool
EmulateInstructionARM::EmulateBLXRm (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    // ARM pseudo code...
    if (ConditionPassed())
    {
        EncodingSpecificOperations();
        target = R[m];
        if CurrentInstrSet() == InstrSet_ARM then
            next_instr_addr = PC - 4;
            LR = next_instr_addr;
        else
            next_instr_addr = PC - 2;
            LR = next_instr_addr<31:1> : '1';
        BXWritePC(target);
    }
#endif

    bool success = false;

    if (ConditionPassed(opcode))
    {
        EmulateInstruction::Context context;
        context.type = EmulateInstruction::eContextAbsoluteBranchRegister;
        const uint32_t pc = ReadCoreReg(PC_REG, &success);
        addr_t lr; // next instruction address
        if (!success)
            return false;
        uint32_t Rm; // the register with the target address
        switch (encoding) {
        case eEncodingT1:
            lr = (pc - 2) | 1u; // return address
            Rm = Bits32(opcode, 6, 3);
            // if m == 15 then UNPREDICTABLE;
            if (Rm == 15)
                return false;
            if (InITBlock() && !LastInITBlock())
                return false;
            break;
        case eEncodingA1:
            lr = pc - 4; // return address
            Rm = Bits32(opcode, 3, 0);
            // if m == 15 then UNPREDICTABLE;
            if (Rm == 15)
                return false;
            break;
        default:
            return false;
        }
        addr_t target = ReadCoreReg (Rm, &success);
        if (!success)
            return false;
        RegisterInfo dwarf_reg;
        GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rm, dwarf_reg);
        context.SetRegister (dwarf_reg);
        if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA, lr))
            return false;
        if (!BXWritePC(context, target))
            return false;
    }
    return true;
}

// Branch and Exchange causes a branch to an address and instruction set specified by a register.
bool
EmulateInstructionARM::EmulateBXRm (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    // ARM pseudo code...
    if (ConditionPassed())
    {
        EncodingSpecificOperations();
        BXWritePC(R[m]);
    }
#endif

    if (ConditionPassed(opcode))
    {
        EmulateInstruction::Context context;
        context.type = EmulateInstruction::eContextAbsoluteBranchRegister;
        uint32_t Rm; // the register with the target address
        switch (encoding) {
        case eEncodingT1:
            Rm = Bits32(opcode, 6, 3);
            if (InITBlock() && !LastInITBlock())
                return false;
            break;
        case eEncodingA1:
            Rm = Bits32(opcode, 3, 0);
            break;
        default:
            return false;
        }
        bool success = false;
        addr_t target = ReadCoreReg (Rm, &success);
        if (!success)
            return false;

        RegisterInfo dwarf_reg;
        GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rm, dwarf_reg);
        context.SetRegister (dwarf_reg);
        if (!BXWritePC(context, target))
            return false;
    }
    return true;
}

// Branch and Exchange Jazelle attempts to change to Jazelle state. If the attempt fails, it branches to an
// address and instruction set specified by a register as though it were a BX instruction.
//
// TODO: Emulate Jazelle architecture?
//       We currently assume that switching to Jazelle state fails, thus treating BXJ as a BX operation.
bool
EmulateInstructionARM::EmulateBXJRm (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    // ARM pseudo code...
    if (ConditionPassed())
    {
        EncodingSpecificOperations();
        if JMCR.JE == '0' || CurrentInstrSet() == InstrSet_ThumbEE then
            BXWritePC(R[m]);
        else
            if JazelleAcceptsExecution() then
                SwitchToJazelleExecution();
            else
                SUBARCHITECTURE_DEFINED handler call;
    }
#endif

    if (ConditionPassed(opcode))
    {
        EmulateInstruction::Context context;
        context.type = EmulateInstruction::eContextAbsoluteBranchRegister;
        uint32_t Rm; // the register with the target address
        switch (encoding) {
        case eEncodingT1:
            Rm = Bits32(opcode, 19, 16);
            if (BadReg(Rm))
                return false;
            if (InITBlock() && !LastInITBlock())
                return false;
            break;
        case eEncodingA1:
            Rm = Bits32(opcode, 3, 0);
            if (Rm == 15)
                return false;
            break;
        default:
            return false;
        }
        bool success = false;
        addr_t target = ReadCoreReg (Rm, &success);
        if (!success)
            return false;

        RegisterInfo dwarf_reg;
        GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rm, dwarf_reg);
        context.SetRegister (dwarf_reg);
        if (!BXWritePC(context, target))
            return false;
    }
    return true;
}

// Set r7 to point to some ip offset.
// SUB (immediate)
bool
EmulateInstructionARM::EmulateSUBR7IPImm (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    // ARM pseudo code...
    if (ConditionPassed())
    {
        EncodingSpecificOperations();
        (result, carry, overflow) = AddWithCarry(SP, NOT(imm32), '1');
        if d == 15 then // Can only occur for ARM encoding
           ALUWritePC(result); // setflags is always FALSE here
        else
            R[d] = result;
            if setflags then
                APSR.N = result<31>;
                APSR.Z = IsZeroBit(result);
                APSR.C = carry;
                APSR.V = overflow;
    }
#endif

    if (ConditionPassed(opcode))
    {
        bool success = false;
        const addr_t ip = ReadCoreReg (12, &success);
        if (!success)
            return false;
        uint32_t imm32;
        switch (encoding) {
        case eEncodingA1:
            imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
            break;
        default:
            return false;
        }
        addr_t ip_offset = imm32;
        addr_t addr = ip - ip_offset; // the adjusted ip value

        EmulateInstruction::Context context;
        context.type = EmulateInstruction::eContextRegisterPlusOffset;
        RegisterInfo dwarf_reg;
        GetRegisterInfo (eRegisterKindDWARF, dwarf_r12, dwarf_reg);
        context.SetRegisterPlusOffset (dwarf_reg, -ip_offset);

        if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r7, addr))
            return false;
    }
    return true;
}

// Set ip to point to some stack offset.
// SUB (SP minus immediate)
bool
EmulateInstructionARM::EmulateSUBIPSPImm (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    // ARM pseudo code...
    if (ConditionPassed())
    {
        EncodingSpecificOperations();
        (result, carry, overflow) = AddWithCarry(SP, NOT(imm32), '1');
        if d == 15 then // Can only occur for ARM encoding
           ALUWritePC(result); // setflags is always FALSE here
        else
            R[d] = result;
            if setflags then
                APSR.N = result<31>;
                APSR.Z = IsZeroBit(result);
                APSR.C = carry;
                APSR.V = overflow;
    }
#endif

    if (ConditionPassed(opcode))
    {
        bool success = false;
        const addr_t sp = ReadCoreReg (SP_REG, &success);
        if (!success)
            return false;
        uint32_t imm32;
        switch (encoding) {
        case eEncodingA1:
            imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
            break;
        default:
            return false;
        }
        addr_t sp_offset = imm32;
        addr_t addr = sp - sp_offset; // the adjusted stack pointer value

        EmulateInstruction::Context context;
        context.type = EmulateInstruction::eContextRegisterPlusOffset;
        RegisterInfo dwarf_reg;
        GetRegisterInfo (eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, dwarf_reg);
        context.SetRegisterPlusOffset (dwarf_reg, -sp_offset);

        if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r12, addr))
            return false;
    }
    return true;
}

// This instruction subtracts an immediate value from the SP value, and writes
// the result to the destination register.
//
// If Rd == 13 => A sub operation to adjust the SP -- allocate space for local storage.
bool
EmulateInstructionARM::EmulateSUBSPImm (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    // ARM pseudo code...
    if (ConditionPassed())
    {
        EncodingSpecificOperations();
        (result, carry, overflow) = AddWithCarry(SP, NOT(imm32), '1');
        if d == 15 then        // Can only occur for ARM encoding
           ALUWritePC(result); // setflags is always FALSE here
        else
            R[d] = result;
            if setflags then
                APSR.N = result<31>;
                APSR.Z = IsZeroBit(result);
                APSR.C = carry;
                APSR.V = overflow;
    }
#endif

    bool success = false;
    if (ConditionPassed(opcode))
    {
        const addr_t sp = ReadCoreReg (SP_REG, &success);
        if (!success)
            return false;

        uint32_t Rd;
        bool setflags;
        uint32_t imm32;
        switch (encoding) {
        case eEncodingT1:
            Rd = 13;
            setflags = false;
            imm32 = ThumbImm7Scaled(opcode); // imm32 = ZeroExtend(imm7:'00', 32)
            break;
        case eEncodingT2:
            Rd = Bits32(opcode, 11, 8);
            setflags = BitIsSet(opcode, 20);
            imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
            if (Rd == 15 && setflags)
                return EmulateCMPImm(opcode, eEncodingT2);
            if (Rd == 15 && !setflags)
                return false;
            break;
        case eEncodingT3:
            Rd = Bits32(opcode, 11, 8);
            setflags = false;
            imm32 = ThumbImm12(opcode); // imm32 = ZeroExtend(i:imm3:imm8, 32)
            if (Rd == 15)
                return false;
            break;
        case eEncodingA1:
            Rd = Bits32(opcode, 15, 12);
            setflags = BitIsSet(opcode, 20);
            imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)

            // if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
            if (Rd == 15 && setflags)
                return EmulateSUBSPcLrEtc (opcode, encoding);
            break;
        default:
            return false;
        }
        AddWithCarryResult res = AddWithCarry(sp, ~imm32, 1);

        EmulateInstruction::Context context;
        if (Rd == 13)
        {
            uint64_t imm64 = imm32;  // Need to expand it to 64 bits before attempting to negate it, or the wrong
                                     // value gets passed down to context.SetImmediateSigned.
            context.type = EmulateInstruction::eContextAdjustStackPointer;
            context.SetImmediateSigned (-imm64); // the stack pointer offset
        }
        else
        {
            context.type = EmulateInstruction::eContextImmediate;
            context.SetNoArgs ();
        }

        if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow))
            return false;
    }
    return true;
}

// A store operation to the stack that also updates the SP.
bool
EmulateInstructionARM::EmulateSTRRtSP (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    // ARM pseudo code...
    if (ConditionPassed())
    {
        EncodingSpecificOperations();
        offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
        address = if index then offset_addr else R[n];
        MemU[address,4] = if t == 15 then PCStoreValue() else R[t];
        if wback then R[n] = offset_addr;
    }
#endif

    bool conditional = false;
    bool success = false;
    if (ConditionPassed(opcode, &conditional))
    {
        const uint32_t addr_byte_size = GetAddressByteSize();
        const addr_t sp = ReadCoreReg (SP_REG, &success);
        if (!success)
            return false;
        uint32_t Rt; // the source register
        uint32_t imm12;
        uint32_t Rn;  // This function assumes Rn is the SP, but we should verify that.

        bool index;
        bool add;
        bool wback;
        switch (encoding) {
        case eEncodingA1:
            Rt = Bits32(opcode, 15, 12);
            imm12 = Bits32(opcode, 11, 0);
            Rn = Bits32 (opcode, 19, 16);

            if (Rn != 13) // 13 is the SP reg on ARM.  Verify that Rn == SP.
                return false;

            index = BitIsSet (opcode, 24);
            add = BitIsSet (opcode, 23);
            wback = (BitIsClear (opcode, 24) || BitIsSet (opcode, 21));

            if (wback && ((Rn == 15) || (Rn == Rt)))
                return false;
            break;
        default:
            return false;
        }
        addr_t offset_addr;
        if (add)
            offset_addr = sp + imm12;
        else
            offset_addr = sp - imm12;

        addr_t addr;
        if (index)
            addr = offset_addr;
        else
            addr = sp;

        EmulateInstruction::Context context;
        if (conditional)
            context.type = EmulateInstruction::eContextRegisterStore;
        else
            context.type = EmulateInstruction::eContextPushRegisterOnStack;
        RegisterInfo sp_reg;
        RegisterInfo dwarf_reg;

        GetRegisterInfo (eRegisterKindDWARF, dwarf_sp, sp_reg);
        GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rt, dwarf_reg);
        context.SetRegisterToRegisterPlusOffset ( dwarf_reg, sp_reg, addr - sp);
        if (Rt != 15)
        {
            uint32_t reg_value = ReadCoreReg(Rt, &success);
            if (!success)
                return false;
            if (!MemUWrite (context, addr, reg_value, addr_byte_size))
                return false;
        }
        else
        {
            const uint32_t pc = ReadCoreReg(PC_REG, &success);
            if (!success)
                return false;
            if (!MemUWrite (context, addr, pc, addr_byte_size))
                return false;
        }


        if (wback)
        {
            context.type = EmulateInstruction::eContextAdjustStackPointer;
            context.SetImmediateSigned (addr - sp);
            if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, offset_addr))
                return false;
        }
    }
    return true;
}

// Vector Push stores multiple extension registers to the stack.
// It also updates SP to point to the start of the stored data.
bool
EmulateInstructionARM::EmulateVPUSH (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    // ARM pseudo code...
    if (ConditionPassed())
    {
        EncodingSpecificOperations(); CheckVFPEnabled(TRUE); NullCheckIfThumbEE(13);
        address = SP - imm32;
        SP = SP - imm32;
        if single_regs then
            for r = 0 to regs-1
                MemA[address,4] = S[d+r]; address = address+4;
        else
            for r = 0 to regs-1
                // Store as two word-aligned words in the correct order for current endianness.
                MemA[address,4] = if BigEndian() then D[d+r]<63:32> else D[d+r]<31:0>;
                MemA[address+4,4] = if BigEndian() then D[d+r]<31:0> else D[d+r]<63:32>;
                address = address+8;
    }
#endif

    bool success = false;
    bool conditional = false;
    if (ConditionPassed(opcode, &conditional))
    {
        const uint32_t addr_byte_size = GetAddressByteSize();
        const addr_t sp = ReadCoreReg (SP_REG, &success);
        if (!success)
            return false;
        bool single_regs;
        uint32_t d;     // UInt(D:Vd) or UInt(Vd:D) starting register
        uint32_t imm32; // stack offset
        uint32_t regs;  // number of registers
        switch (encoding) {
        case eEncodingT1:
        case eEncodingA1:
            single_regs = false;
            d = Bit32(opcode, 22) << 4 | Bits32(opcode, 15, 12);
            imm32 = Bits32(opcode, 7, 0) * addr_byte_size;
            // If UInt(imm8) is odd, see "FSTMX".
            regs = Bits32(opcode, 7, 0) / 2;
            // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE;
            if (regs == 0 || regs > 16 || (d + regs) > 32)
                return false;
            break;
        case eEncodingT2:
        case eEncodingA2:
            single_regs = true;
            d = Bits32(opcode, 15, 12) << 1 | Bit32(opcode, 22);
            imm32 = Bits32(opcode, 7, 0) * addr_byte_size;
            regs = Bits32(opcode, 7, 0);
            // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE;
            if (regs == 0 || regs > 16 || (d + regs) > 32)
                return false;
            break;
        default:
            return false;
        }
        uint32_t start_reg = single_regs ? dwarf_s0 : dwarf_d0;
        uint32_t reg_byte_size = single_regs ? addr_byte_size : addr_byte_size * 2;
        addr_t sp_offset = imm32;
        addr_t addr = sp - sp_offset;
        uint32_t i;

        EmulateInstruction::Context context;
        if (conditional)
            context.type = EmulateInstruction::eContextRegisterStore;
        else
            context.type = EmulateInstruction::eContextPushRegisterOnStack;
        RegisterInfo dwarf_reg;
        RegisterInfo sp_reg;
        GetRegisterInfo (eRegisterKindDWARF, dwarf_sp, sp_reg);
        for (i=0; i<regs; ++i)
        {
            GetRegisterInfo (eRegisterKindDWARF, start_reg + d + i, dwarf_reg);
            context.SetRegisterToRegisterPlusOffset ( dwarf_reg, sp_reg, addr - sp);
            // uint64_t to accommodate 64-bit registers.
            uint64_t reg_value = ReadRegisterUnsigned (&dwarf_reg, 0, &success);
            if (!success)
                return false;
            if (!MemAWrite (context, addr, reg_value, reg_byte_size))
                return false;
            addr += reg_byte_size;
        }

        context.type = EmulateInstruction::eContextAdjustStackPointer;
        context.SetImmediateSigned (-sp_offset);

        if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, sp - sp_offset))
            return false;
    }
    return true;
}

// Vector Pop loads multiple extension registers from the stack.
// It also updates SP to point just above the loaded data.
bool
EmulateInstructionARM::EmulateVPOP (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    // ARM pseudo code...
    if (ConditionPassed())
    {
        EncodingSpecificOperations(); CheckVFPEnabled(TRUE); NullCheckIfThumbEE(13);
        address = SP;
        SP = SP + imm32;
        if single_regs then
            for r = 0 to regs-1
                S[d+r] = MemA[address,4]; address = address+4;
        else
            for r = 0 to regs-1
                word1 = MemA[address,4]; word2 = MemA[address+4,4]; address = address+8;
                // Combine the word-aligned words in the correct order for current endianness.
                D[d+r] = if BigEndian() then word1:word2 else word2:word1;
    }
#endif

    bool success = false;
    bool conditional = false;
    if (ConditionPassed(opcode, &conditional))
    {
        const uint32_t addr_byte_size = GetAddressByteSize();
        const addr_t sp = ReadCoreReg (SP_REG, &success);
        if (!success)
            return false;
        bool single_regs;
        uint32_t d;     // UInt(D:Vd) or UInt(Vd:D) starting register
        uint32_t imm32; // stack offset
        uint32_t regs;  // number of registers
        switch (encoding) {
        case eEncodingT1:
        case eEncodingA1:
            single_regs = false;
            d = Bit32(opcode, 22) << 4 | Bits32(opcode, 15, 12);
            imm32 = Bits32(opcode, 7, 0) * addr_byte_size;
            // If UInt(imm8) is odd, see "FLDMX".
            regs = Bits32(opcode, 7, 0) / 2;
            // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE;
            if (regs == 0 || regs > 16 || (d + regs) > 32)
                return false;
            break;
        case eEncodingT2:
        case eEncodingA2:
            single_regs = true;
            d = Bits32(opcode, 15, 12) << 1 | Bit32(opcode, 22);
            imm32 = Bits32(opcode, 7, 0) * addr_byte_size;
            regs = Bits32(opcode, 7, 0);
            // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE;
            if (regs == 0 || regs > 16 || (d + regs) > 32)
                return false;
            break;
        default:
            return false;
        }
        uint32_t start_reg = single_regs ? dwarf_s0 : dwarf_d0;
        uint32_t reg_byte_size = single_regs ? addr_byte_size : addr_byte_size * 2;
        addr_t sp_offset = imm32;
        addr_t addr = sp;
        uint32_t i;
        uint64_t data; // uint64_t to accomodate 64-bit registers.

        EmulateInstruction::Context context;
        if (conditional)
            context.type = EmulateInstruction::eContextRegisterLoad;
        else
            context.type = EmulateInstruction::eContextPopRegisterOffStack;
        RegisterInfo dwarf_reg;
        RegisterInfo sp_reg;
        GetRegisterInfo (eRegisterKindDWARF, dwarf_sp, sp_reg);
        for (i=0; i<regs; ++i)
        {
            GetRegisterInfo (eRegisterKindDWARF, start_reg + d + i, dwarf_reg);
            context.SetRegisterPlusOffset (sp_reg, addr - sp);
            data = MemARead(context, addr, reg_byte_size, 0, &success);
            if (!success)
                return false;
            if (!WriteRegisterUnsigned(context, &dwarf_reg, data))
                return false;
            addr += reg_byte_size;
        }

        context.type = EmulateInstruction::eContextAdjustStackPointer;
        context.SetImmediateSigned (sp_offset);

        if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, sp + sp_offset))
            return false;
    }
    return true;
}

// SVC (previously SWI)
bool
EmulateInstructionARM::EmulateSVC (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    // ARM pseudo code...
    if (ConditionPassed())
    {
        EncodingSpecificOperations();
        CallSupervisor();
    }
#endif

    bool success = false;

    if (ConditionPassed(opcode))
    {
        const uint32_t pc = ReadCoreReg(PC_REG, &success);
        addr_t lr; // next instruction address
        if (!success)
            return false;
        uint32_t imm32; // the immediate constant
        uint32_t mode;  // ARM or Thumb mode
        switch (encoding) {
        case eEncodingT1:
            lr = (pc + 2) | 1u; // return address
            imm32 = Bits32(opcode, 7, 0);
            mode = eModeThumb;
            break;
        case eEncodingA1:
            lr = pc + 4; // return address
            imm32 = Bits32(opcode, 23, 0);
            mode = eModeARM;
            break;
        default:
            return false;
        }

        EmulateInstruction::Context context;
        context.type = EmulateInstruction::eContextSupervisorCall;
        context.SetISAAndImmediate (mode, imm32);
        if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA, lr))
            return false;
    }
    return true;
}

// If Then makes up to four following instructions (the IT block) conditional.
bool
EmulateInstructionARM::EmulateIT (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    // ARM pseudo code...
    EncodingSpecificOperations();
    ITSTATE.IT<7:0> = firstcond:mask;
#endif

    m_it_session.InitIT(Bits32(opcode, 7, 0));
    return true;
}

bool
EmulateInstructionARM::EmulateNop (const uint32_t opcode, const ARMEncoding encoding)
{
    // NOP, nothing to do...
    return true;
}

// Branch causes a branch to a target address.
bool
EmulateInstructionARM::EmulateB (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    // ARM pseudo code...
    if (ConditionPassed())
    {
        EncodingSpecificOperations();
        BranchWritePC(PC + imm32);
    }
#endif

    bool success = false;

    if (ConditionPassed(opcode))
    {
        EmulateInstruction::Context context;
        context.type = EmulateInstruction::eContextRelativeBranchImmediate;
        const uint32_t pc = ReadCoreReg(PC_REG, &success);
        if (!success)
            return false;
        addr_t target; // target address
        int32_t imm32; // PC-relative offset
        switch (encoding) {
        case eEncodingT1:
            // The 'cond' field is handled in EmulateInstructionARM::CurrentCond().
            imm32 = llvm::SignExtend32<9>(Bits32(opcode, 7, 0) << 1);
            target = pc + imm32;
            context.SetISAAndImmediateSigned (eModeThumb, 4 + imm32);
            break;
        case eEncodingT2:
            imm32 = llvm::SignExtend32<12>(Bits32(opcode, 10, 0));
            target = pc + imm32;
            context.SetISAAndImmediateSigned (eModeThumb, 4 + imm32);
            break;
        case eEncodingT3:
            // The 'cond' field is handled in EmulateInstructionARM::CurrentCond().
            {
            uint32_t S = Bit32(opcode, 26);
            uint32_t imm6 = Bits32(opcode, 21, 16);
            uint32_t J1 = Bit32(opcode, 13);
            uint32_t J2 = Bit32(opcode, 11);
            uint32_t imm11 = Bits32(opcode, 10, 0);
            uint32_t imm21 = (S << 20) | (J2 << 19) | (J1 << 18) | (imm6 << 12) | (imm11 << 1);
            imm32 = llvm::SignExtend32<21>(imm21);
            target = pc + imm32;
            context.SetISAAndImmediateSigned (eModeThumb, 4 + imm32);
            break;
            }
        case eEncodingT4:
            {
            uint32_t S = Bit32(opcode, 26);
            uint32_t imm10 = Bits32(opcode, 25, 16);
            uint32_t J1 = Bit32(opcode, 13);
            uint32_t J2 = Bit32(opcode, 11);
            uint32_t imm11 = Bits32(opcode, 10, 0);
            uint32_t I1 = !(J1 ^ S);
            uint32_t I2 = !(J2 ^ S);
            uint32_t imm25 = (S << 24) | (I1 << 23) | (I2 << 22) | (imm10 << 12) | (imm11 << 1);
            imm32 = llvm::SignExtend32<25>(imm25);
            target = pc + imm32;
            context.SetISAAndImmediateSigned (eModeThumb, 4 + imm32);
            break;
            }
        case eEncodingA1:
            imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2);
            target = pc + imm32;
            context.SetISAAndImmediateSigned (eModeARM, 8 + imm32);
            break;
        default:
            return false;
        }
        if (!BranchWritePC(context, target))
            return false;
    }
    return true;
}

// Compare and Branch on Nonzero and Compare and Branch on Zero compare the value in a register with
// zero and conditionally branch forward a constant value.  They do not affect the condition flags.
// CBNZ, CBZ
bool
EmulateInstructionARM::EmulateCB (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    // ARM pseudo code...
    EncodingSpecificOperations();
    if nonzero ^ IsZero(R[n]) then
        BranchWritePC(PC + imm32);
#endif

    bool success = false;

    // Read the register value from the operand register Rn.
    uint32_t reg_val = ReadCoreReg(Bits32(opcode, 2, 0), &success);
    if (!success)
        return false;

    EmulateInstruction::Context context;
    context.type = EmulateInstruction::eContextRelativeBranchImmediate;
    const uint32_t pc = ReadCoreReg(PC_REG, &success);
    if (!success)
        return false;

    addr_t target;  // target address
    uint32_t imm32; // PC-relative offset to branch forward
    bool nonzero;
    switch (encoding) {
    case eEncodingT1:
        imm32 = Bit32(opcode, 9) << 6 | Bits32(opcode, 7, 3) << 1;
        nonzero = BitIsSet(opcode, 11);
        target = pc + imm32;
        context.SetISAAndImmediateSigned (eModeThumb, 4 + imm32);
        break;
    default:
        return false;
    }
    if (nonzero ^ (reg_val == 0))
        if (!BranchWritePC(context, target))
            return false;

    return true;
}

// Table Branch Byte causes a PC-relative forward branch using a table of single byte offsets.
// A base register provides a pointer to the table, and a second register supplies an index into the table.
// The branch length is twice the value of the byte returned from the table.
//
// Table Branch Halfword causes a PC-relative forward branch using a table of single halfword offsets.
// A base register provides a pointer to the table, and a second register supplies an index into the table.
// The branch length is twice the value of the halfword returned from the table.
// TBB, TBH
bool
EmulateInstructionARM::EmulateTB (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    // ARM pseudo code...
    EncodingSpecificOperations(); NullCheckIfThumbEE(n);
    if is_tbh then
        halfwords = UInt(MemU[R[n]+LSL(R[m],1), 2]);
    else
        halfwords = UInt(MemU[R[n]+R[m], 1]);
    BranchWritePC(PC + 2*halfwords);
#endif

    bool success = false;

    uint32_t Rn;     // the base register which contains the address of the table of branch lengths
    uint32_t Rm;     // the index register which contains an integer pointing to a byte/halfword in the table
    bool is_tbh;     // true if table branch halfword
    switch (encoding) {
    case eEncodingT1:
        Rn = Bits32(opcode, 19, 16);
        Rm = Bits32(opcode, 3, 0);
        is_tbh = BitIsSet(opcode, 4);
        if (Rn == 13 || BadReg(Rm))
            return false;
        if (InITBlock() && !LastInITBlock())
            return false;
        break;
    default:
        return false;
    }

    // Read the address of the table from the operand register Rn.
    // The PC can be used, in which case the table immediately follows this instruction.
    uint32_t base = ReadCoreReg(Rm, &success);
    if (!success)
        return false;

    // the table index
    uint32_t index = ReadCoreReg(Rm, &success);
    if (!success)
        return false;

    // the offsetted table address
    addr_t addr = base + (is_tbh ? index*2 : index);

    // PC-relative offset to branch forward
    EmulateInstruction::Context context;
    context.type = EmulateInstruction::eContextTableBranchReadMemory;
    uint32_t offset = MemURead(context, addr, is_tbh ? 2 : 1, 0, &success) * 2;
    if (!success)
        return false;

    const uint32_t pc = ReadCoreReg(PC_REG, &success);
    if (!success)
        return false;

    // target address
    addr_t target = pc + offset;
    context.type = EmulateInstruction::eContextRelativeBranchImmediate;
    context.SetISAAndImmediateSigned (eModeThumb, 4 + offset);

    if (!BranchWritePC(context, target))
        return false;

    return true;
}

// This instruction adds an immediate value to a register value, and writes the result to the destination register.
// It can optionally update the condition flags based on the result.
bool
EmulateInstructionARM::EmulateADDImmThumb (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    if ConditionPassed() then
        EncodingSpecificOperations();
        (result, carry, overflow) = AddWithCarry(R[n], imm32, '0');
        R[d] = result;
        if setflags then
            APSR.N = result<31>;
            APSR.Z = IsZeroBit(result);
            APSR.C = carry;
            APSR.V = overflow;
#endif

    bool success = false;

    if (ConditionPassed(opcode))
    {
        uint32_t d;
        uint32_t n;
        bool setflags;
        uint32_t imm32;
        uint32_t carry_out;

        //EncodingSpecificOperations();
        switch (encoding)
        {
            case eEncodingT1:
                // d = UInt(Rd); n = UInt(Rn); setflags = !InITBlock(); imm32 = ZeroExtend(imm3, 32);
                d = Bits32 (opcode, 2, 0);
                n = Bits32 (opcode, 5, 3);
                setflags = !InITBlock();
                imm32 = Bits32 (opcode, 8,6);

                break;

            case eEncodingT2:
                // d = UInt(Rdn); n = UInt(Rdn); setflags = !InITBlock(); imm32 = ZeroExtend(imm8, 32);
                d = Bits32 (opcode, 10, 8);
                n = Bits32 (opcode, 10, 8);
                setflags = !InITBlock();
                imm32 = Bits32 (opcode, 7, 0);

                break;

            case eEncodingT3:
                // if Rd == '1111' && S == '1' then SEE CMN (immediate);
                // if Rn == '1101' then SEE ADD (SP plus immediate);
                // d = UInt(Rd); n = UInt(Rn); setflags = (S == '1'); imm32 = ThumbExpandImm(i:imm3:imm8);
                d = Bits32 (opcode, 11, 8);
                n = Bits32 (opcode, 19, 16);
                setflags = BitIsSet (opcode, 20);
                imm32 = ThumbExpandImm_C (opcode, APSR_C, carry_out);

                // if BadReg(d) || n == 15 then UNPREDICTABLE;
                if (BadReg (d) || (n == 15))
                    return false;

                break;

            case eEncodingT4:
            {
                // if Rn == '1111' then SEE ADR;
                // if Rn == '1101' then SEE ADD (SP plus immediate);
                // d = UInt(Rd); n = UInt(Rn); setflags = FALSE; imm32 = ZeroExtend(i:imm3:imm8, 32);
                d = Bits32 (opcode, 11, 8);
                n = Bits32 (opcode, 19, 16);
                setflags = false;
                uint32_t i = Bit32 (opcode, 26);
                uint32_t imm3 = Bits32 (opcode, 14, 12);
                uint32_t imm8 = Bits32 (opcode, 7, 0);
                imm32 = (i << 11) | (imm3 << 8) | imm8;

                // if BadReg(d) then UNPREDICTABLE;
                if (BadReg (d))
                    return false;

                break;
            }
            default:
                return false;
        }

        uint64_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
        if (!success)
            return false;

        //(result, carry, overflow) = AddWithCarry(R[n], imm32, '0');
        AddWithCarryResult res = AddWithCarry (Rn, imm32, 0);

        RegisterInfo reg_n;
        GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, reg_n);

        EmulateInstruction::Context context;
        context.type = eContextArithmetic;
        context.SetRegisterPlusOffset (reg_n, imm32);

        //R[d] = result;
        //if setflags then
            //APSR.N = result<31>;
            //APSR.Z = IsZeroBit(result);
            //APSR.C = carry;
            //APSR.V = overflow;
        if (!WriteCoreRegOptionalFlags (context, res.result, d, setflags, res.carry_out, res.overflow))
            return false;

    }
    return true;
}

// This instruction adds an immediate value to a register value, and writes the result to the destination
// register.  It can optionally update the condition flags based on the result.
bool
EmulateInstructionARM::EmulateADDImmARM (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    // ARM pseudo code...
    if ConditionPassed() then
        EncodingSpecificOperations();
        (result, carry, overflow) = AddWithCarry(R[n], imm32, '0');
        if d == 15 then
            ALUWritePC(result); // setflags is always FALSE here
        else
            R[d] = result;
            if setflags then
                APSR.N = result<31>;
                APSR.Z = IsZeroBit(result);
                APSR.C = carry;
                APSR.V = overflow;
#endif

    bool success = false;

    if (ConditionPassed(opcode))
    {
        uint32_t Rd, Rn;
        uint32_t imm32; // the immediate value to be added to the value obtained from Rn
        bool setflags;
        switch (encoding)
        {
        case eEncodingA1:
            Rd = Bits32(opcode, 15, 12);
            Rn = Bits32(opcode, 19, 16);
            setflags = BitIsSet(opcode, 20);
            imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
            break;
        default:
            return false;
        }

        // Read the first operand.
        uint32_t val1 = ReadCoreReg(Rn, &success);
        if (!success)
            return false;

        AddWithCarryResult res = AddWithCarry(val1, imm32, 0);

        EmulateInstruction::Context context;
        context.type = eContextArithmetic;
        RegisterInfo dwarf_reg;
        GetRegisterInfo (eRegisterKindDWARF, Rn, dwarf_reg);
        context.SetRegisterPlusOffset (dwarf_reg, imm32);

        if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow))
            return false;
    }
    return true;
}

// This instruction adds a register value and an optionally-shifted register value, and writes the result
// to the destination register. It can optionally update the condition flags based on the result.
bool
EmulateInstructionARM::EmulateADDReg (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    // ARM pseudo code...
    if ConditionPassed() then
        EncodingSpecificOperations();
        shifted = Shift(R[m], shift_t, shift_n, APSR.C);
        (result, carry, overflow) = AddWithCarry(R[n], shifted, '0');
        if d == 15 then
            ALUWritePC(result); // setflags is always FALSE here
        else
            R[d] = result;
            if setflags then
                APSR.N = result<31>;
                APSR.Z = IsZeroBit(result);
                APSR.C = carry;
                APSR.V = overflow;
#endif

    bool success = false;

    if (ConditionPassed(opcode))
    {
        uint32_t Rd, Rn, Rm;
        ARM_ShifterType shift_t;
        uint32_t shift_n; // the shift applied to the value read from Rm
        bool setflags;
        switch (encoding)
        {
        case eEncodingT1:
            Rd = Bits32(opcode, 2, 0);
            Rn = Bits32(opcode, 5, 3);
            Rm = Bits32(opcode, 8, 6);
            setflags = !InITBlock();
            shift_t = SRType_LSL;
            shift_n = 0;
            break;
        case eEncodingT2:
            Rd = Rn = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0);
            Rm = Bits32(opcode, 6, 3);
            setflags = false;
            shift_t = SRType_LSL;
            shift_n = 0;
            if (Rn == 15 && Rm == 15)
                return false;
            if (Rd == 15 && InITBlock() && !LastInITBlock())
                return false;
            break;
        case eEncodingA1:
            Rd = Bits32(opcode, 15, 12);
            Rn = Bits32(opcode, 19, 16);
            Rm = Bits32(opcode, 3, 0);
            setflags = BitIsSet(opcode, 20);
            shift_n = DecodeImmShiftARM(opcode, shift_t);
            break;
        default:
            return false;
        }

        // Read the first operand.
        uint32_t val1 = ReadCoreReg(Rn, &success);
        if (!success)
            return false;

        // Read the second operand.
        uint32_t val2 = ReadCoreReg(Rm, &success);
        if (!success)
            return false;

        uint32_t shifted = Shift(val2, shift_t, shift_n, APSR_C, &success);
        if (!success)
            return false;
        AddWithCarryResult res = AddWithCarry(val1, shifted, 0);

        EmulateInstruction::Context context;
        context.type = eContextArithmetic;
        RegisterInfo op1_reg;
        RegisterInfo op2_reg;
        GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rn, op1_reg);
        GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rm, op2_reg);
        context.SetRegisterRegisterOperands (op1_reg, op2_reg);

        if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow))
            return false;
    }
    return true;
}

// Compare Negative (immediate) adds a register value and an immediate value.
// It updates the condition flags based on the result, and discards the result.
bool
EmulateInstructionARM::EmulateCMNImm (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    // ARM pseudo code...
    if ConditionPassed() then
        EncodingSpecificOperations();
        (result, carry, overflow) = AddWithCarry(R[n], imm32, '0');
        APSR.N = result<31>;
        APSR.Z = IsZeroBit(result);
        APSR.C = carry;
        APSR.V = overflow;
#endif

    bool success = false;

    uint32_t Rn; // the first operand
    uint32_t imm32; // the immediate value to be compared with
    switch (encoding) {
    case eEncodingT1:
        Rn = Bits32(opcode, 19, 16);
        imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
        if (Rn == 15)
            return false;
        break;
    case eEncodingA1:
        Rn = Bits32(opcode, 19, 16);
        imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
        break;
    default:
        return false;
    }
    // Read the register value from the operand register Rn.
    uint32_t reg_val = ReadCoreReg(Rn, &success);
    if (!success)
        return false;

    AddWithCarryResult res = AddWithCarry(reg_val, imm32, 0);

    EmulateInstruction::Context context;
    context.type = EmulateInstruction::eContextImmediate;
    context.SetNoArgs ();
    if (!WriteFlags(context, res.result, res.carry_out, res.overflow))
        return false;

    return true;
}

// Compare Negative (register) adds a register value and an optionally-shifted register value.
// It updates the condition flags based on the result, and discards the result.
bool
EmulateInstructionARM::EmulateCMNReg (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    // ARM pseudo code...
    if ConditionPassed() then
        EncodingSpecificOperations();
        shifted = Shift(R[m], shift_t, shift_n, APSR.C);
        (result, carry, overflow) = AddWithCarry(R[n], shifted, '0');
        APSR.N = result<31>;
        APSR.Z = IsZeroBit(result);
        APSR.C = carry;
        APSR.V = overflow;
#endif

    bool success = false;

    uint32_t Rn; // the first operand
    uint32_t Rm; // the second operand
    ARM_ShifterType shift_t;
    uint32_t shift_n; // the shift applied to the value read from Rm
    switch (encoding) {
    case eEncodingT1:
        Rn = Bits32(opcode, 2, 0);
        Rm = Bits32(opcode, 5, 3);
        shift_t = SRType_LSL;
        shift_n = 0;
        break;
    case eEncodingT2:
        Rn = Bits32(opcode, 19, 16);
        Rm = Bits32(opcode, 3, 0);
        shift_n = DecodeImmShiftThumb(opcode, shift_t);
        // if n == 15 || BadReg(m) then UNPREDICTABLE;
        if (Rn == 15 || BadReg(Rm))
            return false;
        break;
    case eEncodingA1:
        Rn = Bits32(opcode, 19, 16);
        Rm = Bits32(opcode, 3, 0);
        shift_n = DecodeImmShiftARM(opcode, shift_t);
        break;
    default:
        return false;
    }
    // Read the register value from register Rn.
    uint32_t val1 = ReadCoreReg(Rn, &success);
    if (!success)
        return false;

    // Read the register value from register Rm.
    uint32_t val2 = ReadCoreReg(Rm, &success);
    if (!success)
        return false;

    uint32_t shifted = Shift(val2, shift_t, shift_n, APSR_C, &success);
    if (!success)
        return false;
    AddWithCarryResult res = AddWithCarry(val1, shifted, 0);

    EmulateInstruction::Context context;
    context.type = EmulateInstruction::eContextImmediate;
    context.SetNoArgs();
    if (!WriteFlags(context, res.result, res.carry_out, res.overflow))
        return false;

    return true;
}

// Compare (immediate) subtracts an immediate value from a register value.
// It updates the condition flags based on the result, and discards the result.
bool
EmulateInstructionARM::EmulateCMPImm (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    // ARM pseudo code...
    if ConditionPassed() then
        EncodingSpecificOperations();
        (result, carry, overflow) = AddWithCarry(R[n], NOT(imm32), '1');
        APSR.N = result<31>;
        APSR.Z = IsZeroBit(result);
        APSR.C = carry;
        APSR.V = overflow;
#endif

    bool success = false;

    uint32_t Rn; // the first operand
    uint32_t imm32; // the immediate value to be compared with
    switch (encoding) {
    case eEncodingT1:
        Rn = Bits32(opcode, 10, 8);
        imm32 = Bits32(opcode, 7, 0);
        break;
    case eEncodingT2:
        Rn = Bits32(opcode, 19, 16);
        imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
        if (Rn == 15)
            return false;
        break;
    case eEncodingA1:
        Rn = Bits32(opcode, 19, 16);
        imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
        break;
    default:
        return false;
    }
    // Read the register value from the operand register Rn.
    uint32_t reg_val = ReadCoreReg(Rn, &success);
    if (!success)
        return false;

    AddWithCarryResult res = AddWithCarry(reg_val, ~imm32, 1);

    EmulateInstruction::Context context;
    context.type = EmulateInstruction::eContextImmediate;
    context.SetNoArgs ();
    if (!WriteFlags(context, res.result, res.carry_out, res.overflow))
        return false;

    return true;
}

// Compare (register) subtracts an optionally-shifted register value from a register value.
// It updates the condition flags based on the result, and discards the result.
bool
EmulateInstructionARM::EmulateCMPReg (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    // ARM pseudo code...
    if ConditionPassed() then
        EncodingSpecificOperations();
        shifted = Shift(R[m], shift_t, shift_n, APSR.C);
        (result, carry, overflow) = AddWithCarry(R[n], NOT(shifted), '1');
        APSR.N = result<31>;
        APSR.Z = IsZeroBit(result);
        APSR.C = carry;
        APSR.V = overflow;
#endif

    bool success = false;

    uint32_t Rn; // the first operand
    uint32_t Rm; // the second operand
    ARM_ShifterType shift_t;
    uint32_t shift_n; // the shift applied to the value read from Rm
    switch (encoding) {
    case eEncodingT1:
        Rn = Bits32(opcode, 2, 0);
        Rm = Bits32(opcode, 5, 3);
        shift_t = SRType_LSL;
        shift_n = 0;
        break;
    case eEncodingT2:
        Rn = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0);
        Rm = Bits32(opcode, 6, 3);
        shift_t = SRType_LSL;
        shift_n = 0;
        if (Rn < 8 && Rm < 8)
            return false;
        if (Rn == 15 || Rm == 15)
            return false;
        break;
    case eEncodingA1:
        Rn = Bits32(opcode, 19, 16);
        Rm = Bits32(opcode, 3, 0);
        shift_n = DecodeImmShiftARM(opcode, shift_t);
        break;
    default:
        return false;
    }
    // Read the register value from register Rn.
    uint32_t val1 = ReadCoreReg(Rn, &success);
    if (!success)
        return false;

    // Read the register value from register Rm.
    uint32_t val2 = ReadCoreReg(Rm, &success);
    if (!success)
        return false;

    uint32_t shifted = Shift(val2, shift_t, shift_n, APSR_C, &success);
    if (!success)
        return false;
    AddWithCarryResult res = AddWithCarry(val1, ~shifted, 1);

    EmulateInstruction::Context context;
    context.type = EmulateInstruction::eContextImmediate;
    context.SetNoArgs();
    if (!WriteFlags(context, res.result, res.carry_out, res.overflow))
        return false;

    return true;
}

// Arithmetic Shift Right (immediate) shifts a register value right by an immediate number of bits,
// shifting in copies of its sign bit, and writes the result to the destination register.  It can
// optionally update the condition flags based on the result.
bool
EmulateInstructionARM::EmulateASRImm (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    // ARM pseudo code...
    if ConditionPassed() then
        EncodingSpecificOperations();
        (result, carry) = Shift_C(R[m], SRType_ASR, shift_n, APSR.C);
        if d == 15 then         // Can only occur for ARM encoding
            ALUWritePC(result); // setflags is always FALSE here
        else
            R[d] = result;
            if setflags then
                APSR.N = result<31>;
                APSR.Z = IsZeroBit(result);
                APSR.C = carry;
                // APSR.V unchanged
#endif

    return EmulateShiftImm (opcode, encoding, SRType_ASR);
}

// Arithmetic Shift Right (register) shifts a register value right by a variable number of bits,
// shifting in copies of its sign bit, and writes the result to the destination register.
// The variable number of bits is read from the bottom byte of a register. It can optionally update
// the condition flags based on the result.
bool
EmulateInstructionARM::EmulateASRReg (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    // ARM pseudo code...
    if ConditionPassed() then
        EncodingSpecificOperations();
        shift_n = UInt(R[m]<7:0>);
        (result, carry) = Shift_C(R[m], SRType_ASR, shift_n, APSR.C);
        R[d] = result;
        if setflags then
            APSR.N = result<31>;
            APSR.Z = IsZeroBit(result);
            APSR.C = carry;
            // APSR.V unchanged
#endif

    return EmulateShiftReg (opcode, encoding, SRType_ASR);
}

// Logical Shift Left (immediate) shifts a register value left by an immediate number of bits,
// shifting in zeros, and writes the result to the destination register.  It can optionally
// update the condition flags based on the result.
bool
EmulateInstructionARM::EmulateLSLImm (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    // ARM pseudo code...
    if ConditionPassed() then
        EncodingSpecificOperations();
        (result, carry) = Shift_C(R[m], SRType_LSL, shift_n, APSR.C);
        if d == 15 then         // Can only occur for ARM encoding
            ALUWritePC(result); // setflags is always FALSE here
        else
            R[d] = result;
            if setflags then
                APSR.N = result<31>;
                APSR.Z = IsZeroBit(result);
                APSR.C = carry;
                // APSR.V unchanged
#endif

    return EmulateShiftImm (opcode, encoding, SRType_LSL);
}

// Logical Shift Left (register) shifts a register value left by a variable number of bits,
// shifting in zeros, and writes the result to the destination register.  The variable number
// of bits is read from the bottom byte of a register. It can optionally update the condition
// flags based on the result.
bool
EmulateInstructionARM::EmulateLSLReg (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    // ARM pseudo code...
    if ConditionPassed() then
        EncodingSpecificOperations();
        shift_n = UInt(R[m]<7:0>);
        (result, carry) = Shift_C(R[m], SRType_LSL, shift_n, APSR.C);
        R[d] = result;
        if setflags then
            APSR.N = result<31>;
            APSR.Z = IsZeroBit(result);
            APSR.C = carry;
            // APSR.V unchanged
#endif

    return EmulateShiftReg (opcode, encoding, SRType_LSL);
}

// Logical Shift Right (immediate) shifts a register value right by an immediate number of bits,
// shifting in zeros, and writes the result to the destination register.  It can optionally
// update the condition flags based on the result.
bool
EmulateInstructionARM::EmulateLSRImm (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    // ARM pseudo code...
    if ConditionPassed() then
        EncodingSpecificOperations();
        (result, carry) = Shift_C(R[m], SRType_LSR, shift_n, APSR.C);
        if d == 15 then         // Can only occur for ARM encoding
            ALUWritePC(result); // setflags is always FALSE here
        else
            R[d] = result;
            if setflags then
                APSR.N = result<31>;
                APSR.Z = IsZeroBit(result);
                APSR.C = carry;
                // APSR.V unchanged
#endif

    return EmulateShiftImm (opcode, encoding, SRType_LSR);
}

// Logical Shift Right (register) shifts a register value right by a variable number of bits,
// shifting in zeros, and writes the result to the destination register.  The variable number
// of bits is read from the bottom byte of a register. It can optionally update the condition
// flags based on the result.
bool
EmulateInstructionARM::EmulateLSRReg (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    // ARM pseudo code...
    if ConditionPassed() then
        EncodingSpecificOperations();
        shift_n = UInt(R[m]<7:0>);
        (result, carry) = Shift_C(R[m], SRType_LSR, shift_n, APSR.C);
        R[d] = result;
        if setflags then
            APSR.N = result<31>;
            APSR.Z = IsZeroBit(result);
            APSR.C = carry;
            // APSR.V unchanged
#endif

    return EmulateShiftReg (opcode, encoding, SRType_LSR);
}

// Rotate Right (immediate) provides the value of the contents of a register rotated by a constant value.
// The bits that are rotated off the right end are inserted into the vacated bit positions on the left.
// It can optionally update the condition flags based on the result.
bool
EmulateInstructionARM::EmulateRORImm (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    // ARM pseudo code...
    if ConditionPassed() then
        EncodingSpecificOperations();
        (result, carry) = Shift_C(R[m], SRType_ROR, shift_n, APSR.C);
        if d == 15 then         // Can only occur for ARM encoding
            ALUWritePC(result); // setflags is always FALSE here
        else
            R[d] = result;
            if setflags then
                APSR.N = result<31>;
                APSR.Z = IsZeroBit(result);
                APSR.C = carry;
                // APSR.V unchanged
#endif

    return EmulateShiftImm (opcode, encoding, SRType_ROR);
}

// Rotate Right (register) provides the value of the contents of a register rotated by a variable number of bits.
// The bits that are rotated off the right end are inserted into the vacated bit positions on the left.
// The variable number of bits is read from the bottom byte of a register. It can optionally update the condition
// flags based on the result.
bool
EmulateInstructionARM::EmulateRORReg (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    // ARM pseudo code...
    if ConditionPassed() then
        EncodingSpecificOperations();
        shift_n = UInt(R[m]<7:0>);
        (result, carry) = Shift_C(R[m], SRType_ROR, shift_n, APSR.C);
        R[d] = result;
        if setflags then
            APSR.N = result<31>;
            APSR.Z = IsZeroBit(result);
            APSR.C = carry;
            // APSR.V unchanged
#endif

    return EmulateShiftReg (opcode, encoding, SRType_ROR);
}

// Rotate Right with Extend provides the value of the contents of a register shifted right by one place,
// with the carry flag shifted into bit [31].
//
// RRX can optionally update the condition flags based on the result.
// In that case, bit [0] is shifted into the carry flag.
bool
EmulateInstructionARM::EmulateRRX (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    // ARM pseudo code...
    if ConditionPassed() then
        EncodingSpecificOperations();
        (result, carry) = Shift_C(R[m], SRType_RRX, 1, APSR.C);
        if d == 15 then         // Can only occur for ARM encoding
            ALUWritePC(result); // setflags is always FALSE here
        else
            R[d] = result;
            if setflags then
                APSR.N = result<31>;
                APSR.Z = IsZeroBit(result);
                APSR.C = carry;
                // APSR.V unchanged
#endif

    return EmulateShiftImm (opcode, encoding, SRType_RRX);
}

bool
EmulateInstructionARM::EmulateShiftImm (const uint32_t opcode, const ARMEncoding encoding, ARM_ShifterType shift_type)
{
//    assert(shift_type == SRType_ASR
//           || shift_type == SRType_LSL
//           || shift_type == SRType_LSR
//           || shift_type == SRType_ROR
//           || shift_type == SRType_RRX);

    bool success = false;

    if (ConditionPassed(opcode))
    {
        uint32_t Rd;    // the destination register
        uint32_t Rm;    // the first operand register
        uint32_t imm5;  // encoding for the shift amount
        uint32_t carry; // the carry bit after the shift operation
        bool setflags;

        // Special case handling!
        // A8.6.139 ROR (immediate) -- Encoding T1
        ARMEncoding use_encoding = encoding;
        if (shift_type == SRType_ROR && use_encoding == eEncodingT1)
        {
            // Morph the T1 encoding from the ARM Architecture Manual into T2 encoding to
            // have the same decoding of bit fields as the other Thumb2 shift operations.
            use_encoding = eEncodingT2;
        }

        switch (use_encoding) {
        case eEncodingT1:
            // Due to the above special case handling!
            if (shift_type == SRType_ROR)
                return false;

            Rd = Bits32(opcode, 2, 0);
            Rm = Bits32(opcode, 5, 3);
            setflags = !InITBlock();
            imm5 = Bits32(opcode, 10, 6);
            break;
        case eEncodingT2:
            // A8.6.141 RRX
            // There's no imm form of RRX instructions.
            if (shift_type == SRType_RRX)
                return false;

            Rd = Bits32(opcode, 11, 8);
            Rm = Bits32(opcode, 3, 0);
            setflags = BitIsSet(opcode, 20);
            imm5 = Bits32(opcode, 14, 12) << 2 | Bits32(opcode, 7, 6);
            if (BadReg(Rd) || BadReg(Rm))
                return false;
            break;
        case eEncodingA1:
            Rd = Bits32(opcode, 15, 12);
            Rm = Bits32(opcode, 3, 0);
            setflags = BitIsSet(opcode, 20);
            imm5 = Bits32(opcode, 11, 7);
            break;
        default:
            return false;
        }

        // A8.6.139 ROR (immediate)
        if (shift_type == SRType_ROR && imm5 == 0)
            shift_type = SRType_RRX;

        // Get the first operand.
        uint32_t value = ReadCoreReg (Rm, &success);
        if (!success)
            return false;

        // Decode the shift amount if not RRX.
        uint32_t amt = (shift_type == SRType_RRX ? 1 : DecodeImmShift(shift_type, imm5));

        uint32_t result = Shift_C(value, shift_type, amt, APSR_C, carry, &success);
        if (!success)
            return false;

        // The context specifies that an immediate is to be moved into Rd.
        EmulateInstruction::Context context;
        context.type = EmulateInstruction::eContextImmediate;
        context.SetNoArgs ();

        if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
            return false;
    }
    return true;
}

bool
EmulateInstructionARM::EmulateShiftReg (const uint32_t opcode, const ARMEncoding encoding, ARM_ShifterType shift_type)
{
    // assert(shift_type == SRType_ASR
    //        || shift_type == SRType_LSL
    //        || shift_type == SRType_LSR
    //        || shift_type == SRType_ROR);

    bool success = false;

    if (ConditionPassed(opcode))
    {
        uint32_t Rd;    // the destination register
        uint32_t Rn;    // the first operand register
        uint32_t Rm;    // the register whose bottom byte contains the amount to shift by
        uint32_t carry; // the carry bit after the shift operation
        bool setflags;
        switch (encoding) {
        case eEncodingT1:
            Rd = Bits32(opcode, 2, 0);
            Rn = Rd;
            Rm = Bits32(opcode, 5, 3);
            setflags = !InITBlock();
            break;
        case eEncodingT2:
            Rd = Bits32(opcode, 11, 8);
            Rn = Bits32(opcode, 19, 16);
            Rm = Bits32(opcode, 3, 0);
            setflags = BitIsSet(opcode, 20);
            if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm))
                return false;
            break;
        case eEncodingA1:
            Rd = Bits32(opcode, 15, 12);
            Rn = Bits32(opcode, 3, 0);
            Rm = Bits32(opcode, 11, 8);
            setflags = BitIsSet(opcode, 20);
            if (Rd == 15 || Rn == 15 || Rm == 15)
                return false;
            break;
        default:
            return false;
        }

        // Get the first operand.
        uint32_t value = ReadCoreReg (Rn, &success);
        if (!success)
            return false;
        // Get the Rm register content.
        uint32_t val = ReadCoreReg (Rm, &success);
        if (!success)
            return false;

        // Get the shift amount.
        uint32_t amt = Bits32(val, 7, 0);

        uint32_t result = Shift_C(value, shift_type, amt, APSR_C, carry, &success);
        if (!success)
            return false;

        // The context specifies that an immediate is to be moved into Rd.
        EmulateInstruction::Context context;
        context.type = EmulateInstruction::eContextImmediate;
        context.SetNoArgs ();

        if (!WriteCoreRegOptionalFlags(context, result, Rd, setflags, carry))
            return false;
    }
    return true;
}

// LDM loads multiple registers from consecutive memory locations, using an
// address from a base register.  Optionally the address just above the highest of those locations
// can be written back to the base register.
bool
EmulateInstructionARM::EmulateLDM (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    // ARM pseudo code...
    if ConditionPassed()
        EncodingSpecificOperations(); NullCheckIfThumbEE (n);
        address = R[n];

        for i = 0 to 14
            if registers<i> == '1' then
                R[i] = MemA[address, 4]; address = address + 4;
        if registers<15> == '1' then
            LoadWritePC (MemA[address, 4]);

        if wback && registers<n> == '0' then R[n] = R[n] + 4 * BitCount (registers);
        if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN; // Only possible for encoding A1

#endif

    bool success = false;
    bool conditional = false;
    if (ConditionPassed(opcode, &conditional))
    {
        uint32_t n;
        uint32_t registers = 0;
        bool wback;
        const uint32_t addr_byte_size = GetAddressByteSize();
        switch (encoding)
        {
            case eEncodingT1:
                // n = UInt(Rn); registers = '00000000':register_list; wback = (registers<n> == '0');
                n = Bits32 (opcode, 10, 8);
                registers = Bits32 (opcode, 7, 0);
                registers = registers & 0x00ff;  // Make sure the top 8 bits are zeros.
                wback = BitIsClear (registers, n);
                // if BitCount(registers) < 1 then UNPREDICTABLE;
                if (BitCount(registers) < 1)
                    return false;
                break;
            case eEncodingT2:
                // if W == '1' && Rn == '1101' then SEE POP;
                // n = UInt(Rn); registers = P:M:'0':register_list; wback = (W == '1');
                n = Bits32 (opcode, 19, 16);
                registers = Bits32 (opcode, 15, 0);
                registers = registers & 0xdfff; // Make sure bit 13 is zero.
                wback = BitIsSet (opcode, 21);

                // if n == 15 || BitCount(registers) < 2 || (P == '1' && M == '1') then UNPREDICTABLE;
                if ((n == 15)
                    || (BitCount (registers) < 2)
                    || (BitIsSet (opcode, 14) && BitIsSet (opcode, 15)))
                    return false;

                // if registers<15> == '1' && InITBlock() && !LastInITBlock() then UNPREDICTABLE;
                if (BitIsSet (registers, 15) && InITBlock() && !LastInITBlock())
                    return false;

                // if wback && registers<n> == '1' then UNPREDICTABLE;
                if (wback
                    && BitIsSet (registers, n))
                    return false;
                break;

            case eEncodingA1:
                n = Bits32 (opcode, 19, 16);
                registers = Bits32 (opcode, 15, 0);
                wback = BitIsSet (opcode, 21);
                if ((n == 15)
                    || (BitCount (registers) < 1))
                    return false;
                break;
            default:
                return false;
        }

        int32_t offset = 0;
        const addr_t base_address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
        if (!success)
            return false;

        EmulateInstruction::Context context;
        context.type = EmulateInstruction::eContextRegisterPlusOffset;
        RegisterInfo dwarf_reg;
        GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, dwarf_reg);
        context.SetRegisterPlusOffset (dwarf_reg, offset);

        for (int i = 0; i < 14; ++i)
        {
            if (BitIsSet (registers, i))
            {
                context.type = EmulateInstruction::eContextRegisterPlusOffset;
                context.SetRegisterPlusOffset (dwarf_reg, offset);
                if (wback && (n == 13)) // Pop Instruction
                {
                    if (conditional)
                        context.type = EmulateInstruction::eContextRegisterLoad;
                    else
                        context.type = EmulateInstruction::eContextPopRegisterOffStack;
                }

                // R[i] = MemA [address, 4]; address = address + 4;
                uint32_t data = MemARead (context, base_address + offset, addr_byte_size, 0, &success);
                if (!success)
                    return false;

                if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + i, data))
                    return false;

                offset += addr_byte_size;
            }
        }

        if (BitIsSet (registers, 15))
        {
            //LoadWritePC (MemA [address, 4]);
            context.type = EmulateInstruction::eContextRegisterPlusOffset;
            context.SetRegisterPlusOffset (dwarf_reg, offset);
            uint32_t data = MemARead (context, base_address + offset, addr_byte_size, 0, &success);
            if (!success)
                return false;
            // In ARMv5T and above, this is an interworking branch.
            if (!LoadWritePC(context, data))
                return false;
        }

        if (wback && BitIsClear (registers, n))
        {
            // R[n] = R[n] + 4 * BitCount (registers)
            int32_t offset = addr_byte_size * BitCount (registers);
            context.type = EmulateInstruction::eContextAdjustBaseRegister;
            context.SetRegisterPlusOffset (dwarf_reg, offset);

            if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, base_address + offset))
                return false;
        }
        if (wback && BitIsSet (registers, n))
            // R[n] bits(32) UNKNOWN;
            return WriteBits32Unknown (n);
    }
    return true;
}

// LDMDA loads multiple registers from consecutive memory locations using an address from a base register.
// The consecutive memory locations end at this address and the address just below the lowest of those locations
// can optionally be written back to the base register.
bool
EmulateInstructionARM::EmulateLDMDA (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    // ARM pseudo code...
    if ConditionPassed() then
        EncodingSpecificOperations();
        address = R[n] - 4*BitCount(registers) + 4;

        for i = 0 to 14
            if registers<i> == '1' then
                  R[i] = MemA[address,4]; address = address + 4;

        if registers<15> == '1' then
            LoadWritePC(MemA[address,4]);

        if wback && registers<n> == '0' then R[n] = R[n] - 4*BitCount(registers);
        if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN;
#endif

    bool success = false;

    if (ConditionPassed(opcode))
    {
        uint32_t n;
        uint32_t registers = 0;
        bool wback;
        const uint32_t addr_byte_size = GetAddressByteSize();

        // EncodingSpecificOperations();
        switch (encoding)
        {
            case eEncodingA1:
                // n = UInt(Rn); registers = register_list; wback = (W == '1');
                n = Bits32 (opcode, 19, 16);
                registers = Bits32 (opcode, 15, 0);
                wback = BitIsSet (opcode, 21);

                // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
                if ((n == 15) || (BitCount (registers) < 1))
                    return false;

                break;

            default:
                return false;
        }
        // address = R[n] - 4*BitCount(registers) + 4;

        int32_t offset = 0;
        addr_t Rn = ReadCoreReg (n, &success);

        if (!success)
            return false;

        addr_t address = Rn - (addr_byte_size * BitCount (registers)) + addr_byte_size;

        EmulateInstruction::Context context;
        context.type = EmulateInstruction::eContextRegisterPlusOffset;
        RegisterInfo dwarf_reg;
        GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, dwarf_reg);
        context.SetRegisterPlusOffset (dwarf_reg, offset);

        // for i = 0 to 14
        for (int i = 0; i < 14; ++i)
        {
            // if registers<i> == '1' then
            if (BitIsSet (registers, i))
            {
                  // R[i] = MemA[address,4]; address = address + 4;
                  context.SetRegisterPlusOffset (dwarf_reg, Rn - (address + offset));
                  uint32_t data = MemARead (context, address + offset, addr_byte_size, 0, &success);
                  if (!success)
                      return false;
                  if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + i, data))
                      return false;
                  offset += addr_byte_size;
            }
        }

        // if registers<15> == '1' then
        //     LoadWritePC(MemA[address,4]);
        if (BitIsSet (registers, 15))
        {
            context.SetRegisterPlusOffset (dwarf_reg, offset);
            uint32_t data = MemARead (context, address + offset, addr_byte_size, 0, &success);
            if (!success)
                return false;
            // In ARMv5T and above, this is an interworking branch.
            if (!LoadWritePC(context, data))
                return false;
        }

        // if wback && registers<n> == '0' then R[n] = R[n] - 4*BitCount(registers);
        if (wback && BitIsClear (registers, n))
        {
            if (!success)
                return false;

            offset = (addr_byte_size * BitCount (registers)) * -1;
            context.type = EmulateInstruction::eContextAdjustBaseRegister;
            context.SetImmediateSigned (offset);
            addr_t addr = Rn + offset;
            if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, addr))
                return false;
        }

        // if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN;
        if (wback && BitIsSet (registers, n))
            return WriteBits32Unknown (n);
    }
    return true;
}

// LDMDB loads multiple registers from consecutive memory locations using an address from a base register.  The
// consecutive memory lcoations end just below this address, and the address of the lowest of those locations can
// be optionally written back to the base register.
bool
EmulateInstructionARM::EmulateLDMDB (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    // ARM pseudo code...
    if ConditionPassed() then
        EncodingSpecificOperations(); NullCheckIfThumbEE(n);
        address = R[n] - 4*BitCount(registers);

        for i = 0 to 14
            if registers<i> == '1' then
                  R[i] = MemA[address,4]; address = address + 4;
        if registers<15> == '1' then
                  LoadWritePC(MemA[address,4]);

        if wback && registers<n> == '0' then R[n] = R[n] - 4*BitCount(registers);
        if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN; // Only possible for encoding A1
#endif

    bool success = false;

    if (ConditionPassed(opcode))
    {
        uint32_t n;
        uint32_t registers = 0;
        bool wback;
        const uint32_t addr_byte_size = GetAddressByteSize();
        switch (encoding)
        {
            case eEncodingT1:
                // n = UInt(Rn); registers = P:M:'0':register_list; wback = (W == '1');
                n = Bits32 (opcode, 19, 16);
                registers = Bits32 (opcode, 15, 0);
                registers = registers & 0xdfff;  // Make sure bit 13 is a zero.
                wback = BitIsSet (opcode, 21);

                // if n == 15 || BitCount(registers) < 2 || (P == '1' && M == '1') then UNPREDICTABLE;
                if ((n == 15)
                    || (BitCount (registers) < 2)
                    || (BitIsSet (opcode, 14) && BitIsSet (opcode, 15)))
                    return false;

                // if registers<15> == '1' && InITBlock() && !LastInITBlock() then UNPREDICTABLE;
                if (BitIsSet (registers, 15) && InITBlock() && !LastInITBlock())
                    return false;

                // if wback && registers<n> == '1' then UNPREDICTABLE;
                if (wback && BitIsSet (registers, n))
                    return false;

                break;

            case eEncodingA1:
                // n = UInt(Rn); registers = register_list; wback = (W == '1');
                n = Bits32 (opcode, 19, 16);
                registers = Bits32 (opcode, 15, 0);
                wback = BitIsSet (opcode, 21);

                // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
                if ((n == 15) || (BitCount (registers) < 1))
                    return false;

                break;

            default:
                return false;
        }

        // address = R[n] - 4*BitCount(registers);

        int32_t offset = 0;
        addr_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);

        if (!success)
            return false;

        addr_t address = Rn - (addr_byte_size * BitCount (registers));
        EmulateInstruction::Context context;
        context.type = EmulateInstruction::eContextRegisterPlusOffset;
        RegisterInfo dwarf_reg;
        GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, dwarf_reg);
        context.SetRegisterPlusOffset (dwarf_reg, Rn - address);

        for (int i = 0; i < 14; ++i)
        {
            if (BitIsSet (registers, i))
            {
                // R[i] = MemA[address,4]; address = address + 4;
                context.SetRegisterPlusOffset (dwarf_reg, Rn - (address + offset));
                uint32_t data = MemARead (context, address + offset, addr_byte_size, 0, &success);
                if (!success)
                    return false;

                if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + i, data))
                    return false;

                offset += addr_byte_size;
            }
        }

        // if registers<15> == '1' then
        //     LoadWritePC(MemA[address,4]);
        if (BitIsSet (registers, 15))
        {
            context.SetRegisterPlusOffset (dwarf_reg, offset);
            uint32_t data = MemARead (context, address + offset, addr_byte_size, 0, &success);
            if (!success)
                return false;
            // In ARMv5T and above, this is an interworking branch.
            if (!LoadWritePC(context, data))
                return false;
        }

        // if wback && registers<n> == '0' then R[n] = R[n] - 4*BitCount(registers);
        if (wback && BitIsClear (registers, n))
        {
            if (!success)
                return false;

            offset = (addr_byte_size * BitCount (registers)) * -1;
            context.type = EmulateInstruction::eContextAdjustBaseRegister;
            context.SetImmediateSigned (offset);
            addr_t addr = Rn + offset;
            if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, addr))
                return false;
        }

        // if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN; // Only possible for encoding A1
        if (wback && BitIsSet (registers, n))
            return WriteBits32Unknown (n);
    }
    return true;
}

// LDMIB loads multiple registers from consecutive memory locations using an address from a base register.  The
// consecutive memory locations start just above this address, and thea ddress of the last of those locations can
// optinoally be written back to the base register.
bool
EmulateInstructionARM::EmulateLDMIB (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    if ConditionPassed() then
        EncodingSpecificOperations();
        address = R[n] + 4;

        for i = 0 to 14
            if registers<i> == '1' then
                  R[i] = MemA[address,4]; address = address + 4;
        if registers<15> == '1' then
            LoadWritePC(MemA[address,4]);

        if wback && registers<n> == '0' then R[n] = R[n] + 4*BitCount(registers);
        if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN;
#endif

    bool success = false;

    if (ConditionPassed(opcode))
    {
        uint32_t n;
        uint32_t registers = 0;
        bool wback;
        const uint32_t addr_byte_size = GetAddressByteSize();
        switch (encoding)
        {
            case eEncodingA1:
                // n = UInt(Rn); registers = register_list; wback = (W == '1');
                n = Bits32 (opcode, 19, 16);
                registers = Bits32 (opcode, 15, 0);
                wback = BitIsSet (opcode, 21);

                // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
                if ((n == 15) || (BitCount (registers) < 1))
                    return false;

                break;
            default:
                return false;
        }
        // address = R[n] + 4;

        int32_t offset = 0;
        addr_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);

        if (!success)
            return false;

        addr_t address = Rn + addr_byte_size;

        EmulateInstruction::Context context;
        context.type = EmulateInstruction::eContextRegisterPlusOffset;
        RegisterInfo dwarf_reg;
        GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, dwarf_reg);
        context.SetRegisterPlusOffset (dwarf_reg, offset);

        for (int i = 0; i < 14; ++i)
        {
            if (BitIsSet (registers, i))
            {
                // R[i] = MemA[address,4]; address = address + 4;

                context.SetRegisterPlusOffset (dwarf_reg, offset + addr_byte_size);
                uint32_t data = MemARead (context, address + offset, addr_byte_size, 0, &success);
                if (!success)
                    return false;

                if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + i, data))
                    return false;

                offset += addr_byte_size;
            }
        }

        // if registers<15> == '1' then
        //     LoadWritePC(MemA[address,4]);
        if (BitIsSet (registers, 15))
        {
            context.SetRegisterPlusOffset (dwarf_reg, offset);
            uint32_t data = MemARead (context, address + offset, addr_byte_size, 0, &success);
            if (!success)
                return false;
            // In ARMv5T and above, this is an interworking branch.
            if (!LoadWritePC(context, data))
                return false;
        }

        // if wback && registers<n> == '0' then R[n] = R[n] + 4*BitCount(registers);
        if (wback && BitIsClear (registers, n))
        {
            if (!success)
                return false;

            offset = addr_byte_size * BitCount (registers);
            context.type = EmulateInstruction::eContextAdjustBaseRegister;
            context.SetImmediateSigned (offset);
            addr_t addr = Rn + offset;
            if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, addr))
                return false;
        }

        // if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN; // Only possible for encoding A1
        if (wback && BitIsSet (registers, n))
            return WriteBits32Unknown (n);
    }
    return true;
}

// Load Register (immediate) calculates an address from a base register value and
// an immediate offset, loads a word from memory, and writes to a register.
// LDR (immediate, Thumb)
bool
EmulateInstructionARM::EmulateLDRRtRnImm (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    // ARM pseudo code...
    if (ConditionPassed())
    {
        EncodingSpecificOperations(); NullCheckIfThumbEE(15);
        offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
        address = if index then offset_addr else R[n];
        data = MemU[address,4];
        if wback then R[n] = offset_addr;
        if t == 15 then
            if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE;
        elsif UnalignedSupport() || address<1:0> = '00' then
            R[t] = data;
        else R[t] = bits(32) UNKNOWN; // Can only apply before ARMv7
    }
#endif

    bool success = false;

    if (ConditionPassed(opcode))
    {
        uint32_t Rt; // the destination register
        uint32_t Rn; // the base register
        uint32_t imm32; // the immediate offset used to form the address
        addr_t offset_addr; // the offset address
        addr_t address; // the calculated address
        uint32_t data; // the literal data value from memory load
        bool add, index, wback;
        switch (encoding) {
            case eEncodingT1:
                Rt = Bits32(opcode, 2, 0);
                Rn = Bits32(opcode, 5, 3);
                imm32 = Bits32(opcode, 10, 6) << 2; // imm32 = ZeroExtend(imm5:'00', 32);
                // index = TRUE; add = TRUE; wback = FALSE
                add = true;
                index = true;
                wback = false;

                break;

            case eEncodingT2:
                // t = UInt(Rt); n = 13; imm32 = ZeroExtend(imm8:'00', 32);
                Rt = Bits32 (opcode, 10, 8);
                Rn = 13;
                imm32 = Bits32 (opcode, 7, 0) << 2;

                // index = TRUE; add = TRUE; wback = FALSE;
                index = true;
                add = true;
                wback = false;

                break;

            case eEncodingT3:
                // if Rn == '1111' then SEE LDR (literal);
                // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
                Rt = Bits32 (opcode, 15, 12);
                Rn = Bits32 (opcode, 19, 16);
                imm32 = Bits32 (opcode, 11, 0);

                // index = TRUE; add = TRUE; wback = FALSE;
                index = true;
                add = true;
                wback = false;

                // if t == 15 && InITBlock() && !LastInITBlock() then UNPREDICTABLE;
                if ((Rt == 15) && InITBlock() && !LastInITBlock())
                    return false;

                break;

            case eEncodingT4:
                // if Rn == '1111' then SEE LDR (literal);
                // if P == '1' && U == '1' && W == '0' then SEE LDRT;
                // if Rn == '1101' && P == '0' && U == '1' && W == '1' && imm8 == '00000100' then SEE POP;
                // if P == '0' && W == '0' then UNDEFINED;
                if (BitIsClear (opcode, 10) && BitIsClear (opcode, 8))
                    return false;

                // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
                Rt = Bits32 (opcode, 15, 12);
                Rn = Bits32 (opcode, 19, 16);
                imm32 = Bits32 (opcode, 7, 0);

                // index = (P == '1'); add = (U == '1'); wback = (W == '1');
                index = BitIsSet (opcode, 10);
                add = BitIsSet (opcode, 9);
                wback = BitIsSet (opcode, 8);

                // if (wback && n == t) || (t == 15 && InITBlock() && !LastInITBlock()) then UNPREDICTABLE;
                if ((wback && (Rn == Rt)) || ((Rt == 15) && InITBlock() && !LastInITBlock()))
                    return false;

                break;

            default:
                return false;
        }
        uint32_t base = ReadCoreReg (Rn, &success);
        if (!success)
            return false;
        if (add)
            offset_addr = base + imm32;
        else
            offset_addr = base - imm32;

        address = (index ? offset_addr : base);

        RegisterInfo base_reg;
        GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + Rn, base_reg);
        if (wback)
        {
            EmulateInstruction::Context ctx;
            ctx.type = EmulateInstruction::eContextAdjustBaseRegister;
            ctx.SetRegisterPlusOffset (base_reg, (int32_t) (offset_addr - base));

            if (!WriteRegisterUnsigned (ctx, eRegisterKindDWARF, dwarf_r0 + Rn, offset_addr))
                return false;
        }

        // Prepare to write to the Rt register.
        EmulateInstruction::Context context;
        context.type = EmulateInstruction::eContextRegisterLoad;
        context.SetRegisterPlusOffset (base_reg, (int32_t) (offset_addr - base));

        // Read memory from the address.
        data = MemURead(context, address, 4, 0, &success);
        if (!success)
            return false;

        if (Rt == 15)
        {
            if (Bits32(address, 1, 0) == 0)
            {
                if (!LoadWritePC(context, data))
                    return false;
            }
            else
                return false;
        }
        else if (UnalignedSupport() || Bits32(address, 1, 0) == 0)
        {
            if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rt, data))
                return false;
        }
        else
            WriteBits32Unknown (Rt);
    }
    return true;
}

// STM (Store Multiple Increment After) stores multiple registers to consecutive memory locations using an address
// from a base register.  The consecutive memory locations start at this address, and teh address just above the last
// of those locations can optionally be written back to the base register.
bool
EmulateInstructionARM::EmulateSTM (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    if ConditionPassed() then
        EncodingSpecificOperations(); NullCheckIfThumbEE(n);
        address = R[n];

        for i = 0 to 14
            if registers<i> == '1' then
                if i == n && wback && i != LowestSetBit(registers) then
                    MemA[address,4] = bits(32) UNKNOWN; // Only possible for encodings T1 and A1
                else
                    MemA[address,4] = R[i];
                address = address + 4;

        if registers<15> == '1' then // Only possible for encoding A1
            MemA[address,4] = PCStoreValue();
        if wback then R[n] = R[n] + 4*BitCount(registers);
#endif

    bool success = false;

    if (ConditionPassed(opcode))
    {
        uint32_t n;
        uint32_t registers = 0;
        bool wback;
        const uint32_t addr_byte_size = GetAddressByteSize();

        // EncodingSpecificOperations(); NullCheckIfThumbEE(n);
        switch (encoding)
        {
            case eEncodingT1:
                // n = UInt(Rn); registers = '00000000':register_list; wback = TRUE;
                n = Bits32 (opcode, 10, 8);
                registers = Bits32 (opcode, 7, 0);
                registers = registers & 0x00ff;  // Make sure the top 8 bits are zeros.
                wback = true;

                // if BitCount(registers) < 1 then UNPREDICTABLE;
                if (BitCount (registers) < 1)
                    return false;

                break;

            case eEncodingT2:
                // n = UInt(Rn); registers = '0':M:'0':register_list; wback = (W == '1');
                n = Bits32 (opcode, 19, 16);
                registers = Bits32 (opcode, 15, 0);
                registers = registers & 0x5fff; // Make sure bits 15 & 13 are zeros.
                wback = BitIsSet (opcode, 21);

                // if n == 15 || BitCount(registers) < 2 then UNPREDICTABLE;
                if ((n == 15) || (BitCount (registers) < 2))
                    return false;

                // if wback && registers<n> == '1' then UNPREDICTABLE;
                if (wback && BitIsSet (registers, n))
                    return false;

                break;

            case eEncodingA1:
                // n = UInt(Rn); registers = register_list; wback = (W == '1');
                n = Bits32 (opcode, 19, 16);
                registers = Bits32 (opcode, 15, 0);
                wback = BitIsSet (opcode, 21);

                // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
                if ((n == 15) || (BitCount (registers) < 1))
                    return false;

                break;

            default:
                return false;
        }

        // address = R[n];
        int32_t offset = 0;
        const addr_t address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
        if (!success)
            return false;

        EmulateInstruction::Context context;
        context.type = EmulateInstruction::eContextRegisterStore;
        RegisterInfo base_reg;
        GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);

        // for i = 0 to 14
        uint32_t lowest_set_bit = 14;
        for (uint32_t i = 0; i < 14; ++i)
        {
            // if registers<i> == '1' then
            if (BitIsSet (registers, i))
            {
                  if (i < lowest_set_bit)
                      lowest_set_bit = i;
                  // if i == n && wback && i != LowestSetBit(registers) then
                  if ((i == n) && wback && (i != lowest_set_bit))
                      // MemA[address,4] = bits(32) UNKNOWN; // Only possible for encodings T1 and A1
                      WriteBits32UnknownToMemory (address + offset);
                  else
                  {
                     // MemA[address,4] = R[i];
                      uint32_t data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + i, 0, &success);
                      if (!success)
                          return false;

                      RegisterInfo data_reg;
                      GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + i, data_reg);
                      context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, offset);
                      if (!MemAWrite (context, address + offset, data, addr_byte_size))
                          return false;
                  }

                  // address = address + 4;
                  offset += addr_byte_size;
            }
        }

        // if registers<15> == '1' then // Only possible for encoding A1
        //     MemA[address,4] = PCStoreValue();
        if (BitIsSet (registers, 15))
        {
            RegisterInfo pc_reg;
            GetRegisterInfo (eRegisterKindDWARF, dwarf_pc, pc_reg);
            context.SetRegisterPlusOffset (pc_reg, 8);
            const uint32_t pc = ReadCoreReg (PC_REG, &success);
            if (!success)
                return false;

            if (!MemAWrite (context, address + offset, pc, addr_byte_size))
                return false;
        }

        // if wback then R[n] = R[n] + 4*BitCount(registers);
        if (wback)
        {
            offset = addr_byte_size * BitCount (registers);
            context.type = EmulateInstruction::eContextAdjustBaseRegister;
            context.SetImmediateSigned (offset);
            addr_t data = address + offset;
            if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, data))
                return false;
        }
    }
    return true;
}

// STMDA (Store Multiple Decrement After) stores multiple registers to consecutive memory locations using an address
// from a base register.  The consecutive memory locations end at this address, and the address just below the lowest
// of those locations can optionally be written back to the base register.
bool
EmulateInstructionARM::EmulateSTMDA (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    if ConditionPassed() then
        EncodingSpecificOperations();
        address = R[n] - 4*BitCount(registers) + 4;

        for i = 0 to 14
            if registers<i> == '1' then
                if i == n && wback && i != LowestSetBit(registers) then
                    MemA[address,4] = bits(32) UNKNOWN;
                else
                    MemA[address,4] = R[i];
                address = address + 4;

        if registers<15> == '1' then
            MemA[address,4] = PCStoreValue();

        if wback then R[n] = R[n] - 4*BitCount(registers);
#endif

    bool success = false;

    if (ConditionPassed(opcode))
    {
        uint32_t n;
        uint32_t registers = 0;
        bool wback;
        const uint32_t addr_byte_size = GetAddressByteSize();

        // EncodingSpecificOperations();
        switch (encoding)
        {
            case eEncodingA1:
                // n = UInt(Rn); registers = register_list; wback = (W == '1');
                n = Bits32 (opcode, 19, 16);
                registers = Bits32 (opcode, 15, 0);
                wback = BitIsSet (opcode, 21);

                // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
                if ((n == 15) || (BitCount (registers) < 1))
                    return false;
                break;
            default:
                return false;
        }

        // address = R[n] - 4*BitCount(registers) + 4;
        int32_t offset = 0;
        addr_t Rn = ReadCoreReg (n, &success);
        if (!success)
            return false;

        addr_t address = Rn - (addr_byte_size * BitCount (registers)) + 4;

        EmulateInstruction::Context context;
        context.type = EmulateInstruction::eContextRegisterStore;
        RegisterInfo base_reg;
        GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);

        // for i = 0 to 14
        uint32_t lowest_bit_set = 14;
        for (uint32_t i = 0; i < 14; ++i)
        {
            // if registers<i> == '1' then
            if (BitIsSet (registers, i))
            {
                if (i < lowest_bit_set)
                    lowest_bit_set = i;
                //if i == n && wback && i != LowestSetBit(registers) then
                if ((i == n) && wback && (i != lowest_bit_set))
                    // MemA[address,4] = bits(32) UNKNOWN;
                    WriteBits32UnknownToMemory (address + offset);
                else
                {
                    // MemA[address,4] = R[i];
                    uint32_t data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + i, 0, &success);
                    if (!success)
                        return false;

                    RegisterInfo data_reg;
                    GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + i, data_reg);
                    context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, Rn - (address + offset));
                    if (!MemAWrite (context, address + offset, data, addr_byte_size))
                        return false;
                }

                // address = address + 4;
                offset += addr_byte_size;
            }
        }

        // if registers<15> == '1' then
        //    MemA[address,4] = PCStoreValue();
        if (BitIsSet (registers, 15))
        {
            RegisterInfo pc_reg;
            GetRegisterInfo (eRegisterKindDWARF, dwarf_pc, pc_reg);
            context.SetRegisterPlusOffset (pc_reg, 8);
            const uint32_t pc = ReadCoreReg (PC_REG, &success);
            if (!success)
                return false;

            if (!MemAWrite (context, address + offset, pc, addr_byte_size))
                return false;
        }

        // if wback then R[n] = R[n] - 4*BitCount(registers);
        if (wback)
        {
            offset = (addr_byte_size * BitCount (registers)) * -1;
            context.type = EmulateInstruction::eContextAdjustBaseRegister;
            context.SetImmediateSigned (offset);
            addr_t data = Rn + offset;
            if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, data))
                return false;
        }
    }
    return true;
}

// STMDB (Store Multiple Decrement Before) stores multiple registers to consecutive memory locations using an address
// from a base register.  The consecutive memory locations end just below this address, and the address of the first of
// those locations can optionally be written back to the base register.
bool
EmulateInstructionARM::EmulateSTMDB (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    if ConditionPassed() then
        EncodingSpecificOperations(); NullCheckIfThumbEE(n);
        address = R[n] - 4*BitCount(registers);

        for i = 0 to 14
            if registers<i> == '1' then
                if i == n && wback && i != LowestSetBit(registers) then
                    MemA[address,4] = bits(32) UNKNOWN; // Only possible for encoding A1
                else
                    MemA[address,4] = R[i];
                address = address + 4;

        if registers<15> == '1' then // Only possible for encoding A1
            MemA[address,4] = PCStoreValue();

        if wback then R[n] = R[n] - 4*BitCount(registers);
#endif


    bool success = false;

    if (ConditionPassed(opcode))
    {
        uint32_t n;
        uint32_t registers = 0;
        bool wback;
        const uint32_t addr_byte_size = GetAddressByteSize();

        // EncodingSpecificOperations(); NullCheckIfThumbEE(n);
        switch (encoding)
        {
            case eEncodingT1:
                // if W == '1' && Rn == '1101' then SEE PUSH;
                if ((BitIsSet (opcode, 21)) && (Bits32 (opcode, 19, 16) == 13))
                {
                    // See PUSH
                }
                // n = UInt(Rn); registers = '0':M:'0':register_list; wback = (W == '1');
                n = Bits32 (opcode, 19, 16);
                registers = Bits32 (opcode, 15, 0);
                registers = registers & 0x5fff;  // Make sure bits 15 & 13 are zeros.
                wback = BitIsSet (opcode, 21);
                // if n == 15 || BitCount(registers) < 2 then UNPREDICTABLE;
                if ((n == 15) || BitCount (registers) < 2)
                    return false;
                // if wback && registers<n> == '1' then UNPREDICTABLE;
                if (wback && BitIsSet (registers, n))
                    return false;
                break;

            case eEncodingA1:
                // if W == '1' && Rn == '1101 && BitCount(register_list) >= 2 then SEE PUSH;
                if (BitIsSet (opcode, 21) && (Bits32 (opcode, 19, 16) == 13) && BitCount (Bits32 (opcode, 15, 0)) >= 2)
                {
                    // See Push
                }
                // n = UInt(Rn); registers = register_list; wback = (W == '1');
                n = Bits32 (opcode, 19, 16);
                registers = Bits32 (opcode, 15, 0);
                wback = BitIsSet (opcode, 21);
                // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
                if ((n == 15) || BitCount (registers) < 1)
                    return false;
                break;

            default:
                return false;
        }

        // address = R[n] - 4*BitCount(registers);

        int32_t offset = 0;
        addr_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
        if (!success)
        return false;

        addr_t address = Rn - (addr_byte_size * BitCount (registers));

        EmulateInstruction::Context context;
        context.type = EmulateInstruction::eContextRegisterStore;
        RegisterInfo base_reg;
        GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);

        // for i = 0 to 14
        uint32_t lowest_set_bit = 14;
        for (uint32_t i = 0; i < 14; ++i)
        {
            // if registers<i> == '1' then
            if (BitIsSet (registers, i))
            {
                if (i < lowest_set_bit)
                    lowest_set_bit = i;
                // if i == n && wback && i != LowestSetBit(registers) then
                if ((i == n) && wback && (i != lowest_set_bit))
                    // MemA[address,4] = bits(32) UNKNOWN; // Only possible for encoding A1
                    WriteBits32UnknownToMemory (address + offset);
                else
                {
                    // MemA[address,4] = R[i];
                    uint32_t data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + i, 0, &success);
                    if (!success)
                        return false;

                    RegisterInfo data_reg;
                    GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + i, data_reg);
                    context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, Rn - (address + offset));
                    if (!MemAWrite (context, address + offset, data, addr_byte_size))
                        return false;
                }

                // address = address + 4;
                offset += addr_byte_size;
            }
        }

        // if registers<15> == '1' then // Only possible for encoding A1
        //     MemA[address,4] = PCStoreValue();
        if (BitIsSet (registers, 15))
        {
            RegisterInfo pc_reg;
            GetRegisterInfo (eRegisterKindDWARF, dwarf_pc, pc_reg);
            context.SetRegisterPlusOffset (pc_reg, 8);
            const uint32_t pc = ReadCoreReg (PC_REG, &success);
            if (!success)
                return false;

            if (!MemAWrite (context, address + offset, pc, addr_byte_size))
                return false;
        }

        // if wback then R[n] = R[n] - 4*BitCount(registers);
        if (wback)
        {
            offset = (addr_byte_size * BitCount (registers)) * -1;
            context.type = EmulateInstruction::eContextAdjustBaseRegister;
            context.SetImmediateSigned (offset);
            addr_t data = Rn + offset;
            if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, data))
                return false;
        }
    }
    return true;
}

// STMIB (Store Multiple Increment Before) stores multiple registers to consecutive memory locations using an address
// from a base register.  The consecutive memory locations start just above this address, and the address of the last
// of those locations can optionally be written back to the base register.
bool
EmulateInstructionARM::EmulateSTMIB (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    if ConditionPassed() then
        EncodingSpecificOperations();
        address = R[n] + 4;

        for i = 0 to 14
            if registers<i> == '1' then
                if i == n && wback && i != LowestSetBit(registers) then
                    MemA[address,4] = bits(32) UNKNOWN;
                else
                    MemA[address,4] = R[i];
                address = address + 4;

        if registers<15> == '1' then
            MemA[address,4] = PCStoreValue();

        if wback then R[n] = R[n] + 4*BitCount(registers);
#endif

    bool success = false;

    if (ConditionPassed(opcode))
    {
        uint32_t n;
        uint32_t registers = 0;
        bool wback;
        const uint32_t addr_byte_size = GetAddressByteSize();

        // EncodingSpecificOperations();
        switch (encoding)
        {
            case eEncodingA1:
                // n = UInt(Rn); registers = register_list; wback = (W == '1');
                n = Bits32 (opcode, 19, 16);
                registers = Bits32 (opcode, 15, 0);
                wback = BitIsSet (opcode, 21);

                // if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
                if ((n == 15) && (BitCount (registers) < 1))
                    return false;
                break;
            default:
                return false;
        }
        // address = R[n] + 4;

        int32_t offset = 0;
        addr_t Rn = ReadCoreReg (n, &success);
        if (!success)
            return false;

        addr_t address = Rn + addr_byte_size;

        EmulateInstruction::Context context;
        context.type = EmulateInstruction::eContextRegisterStore;
        RegisterInfo base_reg;
        GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);

        uint32_t lowest_set_bit = 14;
        // for i = 0 to 14
        for (uint32_t i = 0; i < 14; ++i)
        {
            // if registers<i> == '1' then
            if (BitIsSet (registers, i))
            {
                if (i < lowest_set_bit)
                    lowest_set_bit = i;
                // if i == n && wback && i != LowestSetBit(registers) then
                if ((i == n) && wback && (i != lowest_set_bit))
                    // MemA[address,4] = bits(32) UNKNOWN;
                    WriteBits32UnknownToMemory (address + offset);
                // else
                else
                {
                    // MemA[address,4] = R[i];
                    uint32_t data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + i, 0, &success);
                    if (!success)
                        return false;

                    RegisterInfo data_reg;
                    GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + i, data_reg);
                    context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, offset + addr_byte_size);
                    if (!MemAWrite (context, address + offset, data, addr_byte_size))
                        return false;
                }

                // address = address + 4;
                offset += addr_byte_size;
            }
        }

        // if registers<15> == '1' then
            // MemA[address,4] = PCStoreValue();
        if (BitIsSet (registers, 15))
        {
            RegisterInfo pc_reg;
            GetRegisterInfo (eRegisterKindDWARF, dwarf_pc, pc_reg);
            context.SetRegisterPlusOffset (pc_reg, 8);
            const uint32_t pc = ReadCoreReg (PC_REG, &success);
            if (!success)
            return false;

            if (!MemAWrite (context, address + offset, pc, addr_byte_size))
                return false;
        }

        // if wback then R[n] = R[n] + 4*BitCount(registers);
        if (wback)
        {
            offset = addr_byte_size * BitCount (registers);
            context.type = EmulateInstruction::eContextAdjustBaseRegister;
            context.SetImmediateSigned (offset);
            addr_t data = Rn + offset;
            if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, data))
                return false;
        }
    }
    return true;
}

// STR (store immediate) calcualtes an address from a base register value and an immediate offset, and stores a word
// from a register to memory.  It can use offset, post-indexed, or pre-indexed addressing.
bool
EmulateInstructionARM::EmulateSTRThumb (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    if ConditionPassed() then
        EncodingSpecificOperations(); NullCheckIfThumbEE(n);
        offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
        address = if index then offset_addr else R[n];
        if UnalignedSupport() || address<1:0> == '00' then
            MemU[address,4] = R[t];
        else // Can only occur before ARMv7
            MemU[address,4] = bits(32) UNKNOWN;
        if wback then R[n] = offset_addr;
#endif

    bool success = false;

    if (ConditionPassed(opcode))
    {
        const uint32_t addr_byte_size = GetAddressByteSize();

        uint32_t t;
        uint32_t n;
        uint32_t imm32;
        bool index;
        bool add;
        bool wback;
        // EncodingSpecificOperations (); NullCheckIfThumbEE(n);
        switch (encoding)
        {
            case eEncodingT1:
                // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm5:'00', 32);
                t = Bits32 (opcode, 2, 0);
                n = Bits32 (opcode, 5, 3);
                imm32 = Bits32 (opcode, 10, 6) << 2;

                // index = TRUE; add = TRUE; wback = FALSE;
                index = true;
                add = false;
                wback = false;
                break;

            case eEncodingT2:
                // t = UInt(Rt); n = 13; imm32 = ZeroExtend(imm8:'00', 32);
                t = Bits32 (opcode, 10, 8);
                n = 13;
                imm32 = Bits32 (opcode, 7, 0) << 2;

                // index = TRUE; add = TRUE; wback = FALSE;
                index = true;
                add = true;
                wback = false;
                break;

            case eEncodingT3:
                // if Rn == '1111' then UNDEFINED;
                if (Bits32 (opcode, 19, 16) == 15)
                    return false;

                // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
                t = Bits32 (opcode, 15, 12);
                n = Bits32 (opcode, 19, 16);
                imm32 = Bits32 (opcode, 11, 0);

                // index = TRUE; add = TRUE; wback = FALSE;
                index = true;
                add = true;
                wback = false;

                // if t == 15 then UNPREDICTABLE;
                if (t == 15)
                    return false;
                break;

            case eEncodingT4:
                // if P == '1' && U == '1' && W == '0' then SEE STRT;
                // if Rn == '1101' && P == '1' && U == '0' && W == '1' && imm8 == '00000100' then SEE PUSH;
                // if Rn == '1111' || (P == '0' && W == '0') then UNDEFINED;
                if ((Bits32 (opcode, 19, 16) == 15)
                      || (BitIsClear (opcode, 10) && BitIsClear (opcode, 8)))
                    return false;

                // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
                t = Bits32 (opcode, 15, 12);
                n = Bits32 (opcode, 19, 16);
                imm32 = Bits32 (opcode, 7, 0);

                // index = (P == '1'); add = (U == '1'); wback = (W == '1');
                index = BitIsSet (opcode, 10);
                add = BitIsSet (opcode, 9);
                wback = BitIsSet (opcode, 8);

                // if t == 15 || (wback && n == t) then UNPREDICTABLE;
                if ((t == 15) || (wback && (n == t)))
                    return false;
                break;

            default:
                return false;
        }

        addr_t offset_addr;
        addr_t address;

        // offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
        uint32_t base_address = ReadCoreReg (n, &success);
        if (!success)
            return false;

        if (add)
            offset_addr = base_address + imm32;
        else
            offset_addr = base_address - imm32;

        // address = if index then offset_addr else R[n];
        if (index)
            address = offset_addr;
        else
            address = base_address;

        EmulateInstruction::Context context;
        context.type = eContextRegisterStore;
        RegisterInfo base_reg;
        GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);

        // if UnalignedSupport() || address<1:0> == '00' then
        if (UnalignedSupport () || (BitIsClear (address, 1) && BitIsClear (address, 0)))
        {
            // MemU[address,4] = R[t];
            uint32_t data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + t, 0, &success);
            if (!success)
                return false;

            RegisterInfo data_reg;
            GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + t, data_reg);
            int32_t offset = address - base_address;
            context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, offset);
            if (!MemUWrite (context, address, data, addr_byte_size))
                return false;
        }
        else
        {
            // MemU[address,4] = bits(32) UNKNOWN;
            WriteBits32UnknownToMemory (address);
        }

        // if wback then R[n] = offset_addr;
        if (wback)
        {
            context.type = eContextRegisterLoad;
            context.SetAddress (offset_addr);
            if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr))
                return false;
        }
    }
    return true;
}

// STR (Store Register) calculates an address from a base register value and an offset register value, stores a
// word from a register to memory.   The offset register value can optionally be shifted.
bool
EmulateInstructionARM::EmulateSTRRegister (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    if ConditionPassed() then
        EncodingSpecificOperations(); NullCheckIfThumbEE(n);
        offset = Shift(R[m], shift_t, shift_n, APSR.C);
        offset_addr = if add then (R[n] + offset) else (R[n] - offset);
        address = if index then offset_addr else R[n];
        if t == 15 then // Only possible for encoding A1
            data = PCStoreValue();
        else
            data = R[t];
        if UnalignedSupport() || address<1:0> == '00' || CurrentInstrSet() == InstrSet_ARM then
            MemU[address,4] = data;
        else // Can only occur before ARMv7
            MemU[address,4] = bits(32) UNKNOWN;
        if wback then R[n] = offset_addr;
#endif

    bool success = false;

    if (ConditionPassed(opcode))
    {
        const uint32_t addr_byte_size = GetAddressByteSize();

        uint32_t t;
        uint32_t n;
        uint32_t m;
        ARM_ShifterType shift_t;
        uint32_t shift_n;
        bool index;
        bool add;
        bool wback;

        // EncodingSpecificOperations (); NullCheckIfThumbEE(n);
        switch (encoding)
        {
            case eEncodingT1:
                // if CurrentInstrSet() == InstrSet_ThumbEE then SEE "Modified operation in ThumbEE";
                // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
                t = Bits32 (opcode, 2, 0);
                n = Bits32 (opcode, 5, 3);
                m = Bits32 (opcode, 8, 6);

                // index = TRUE; add = TRUE; wback = FALSE;
                index = true;
                add = true;
                wback = false;

                // (shift_t, shift_n) = (SRType_LSL, 0);
                shift_t = SRType_LSL;
                shift_n = 0;
                break;

            case eEncodingT2:
                // if Rn == '1111' then UNDEFINED;
                if (Bits32 (opcode, 19, 16) == 15)
                    return false;

                // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
                t = Bits32 (opcode, 15, 12);
                n = Bits32 (opcode, 19, 16);
                m = Bits32 (opcode, 3, 0);

                // index = TRUE; add = TRUE; wback = FALSE;
                index = true;
                add = true;
                wback = false;

                // (shift_t, shift_n) = (SRType_LSL, UInt(imm2));
                shift_t = SRType_LSL;
                shift_n = Bits32 (opcode, 5, 4);

                // if t == 15 || BadReg(m) then UNPREDICTABLE;
                if ((t == 15) || (BadReg (m)))
                    return false;
                break;

            case eEncodingA1:
            {
                // if P == '0' && W == '1' then SEE STRT;
                // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
                t = Bits32 (opcode, 15, 12);
                n = Bits32 (opcode, 19, 16);
                m = Bits32 (opcode, 3, 0);

                // index = (P == '1');	add = (U == '1');	wback = (P == '0') || (W == '1');
                index = BitIsSet (opcode, 24);
                add = BitIsSet (opcode, 23);
                wback = (BitIsClear (opcode, 24) || BitIsSet (opcode, 21));

                // (shift_t, shift_n) = DecodeImmShift(type, imm5);
                uint32_t typ = Bits32 (opcode, 6, 5);
                uint32_t imm5 = Bits32 (opcode, 11, 7);
                shift_n = DecodeImmShift(typ, imm5, shift_t);

                // if m == 15 then UNPREDICTABLE;
                if (m == 15)
                    return false;

                // if wback && (n == 15 || n == t) then UNPREDICTABLE;
                if (wback && ((n == 15) || (n == t)))
                    return false;

                break;
            }
            default:
                return false;
        }

        addr_t offset_addr;
        addr_t address;
        int32_t offset = 0;

        addr_t base_address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
        if (!success)
            return false;

        uint32_t Rm_data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
        if (!success)
            return false;

        // offset = Shift(R[m], shift_t, shift_n, APSR.C);
        offset = Shift (Rm_data, shift_t, shift_n, APSR_C, &success);
        if (!success)
            return false;

        // offset_addr = if add then (R[n] + offset) else (R[n] - offset);
        if (add)
            offset_addr = base_address + offset;
        else
            offset_addr = base_address - offset;

        // address = if index then offset_addr else R[n];
        if (index)
            address = offset_addr;
        else
            address = base_address;

        uint32_t data;
        // if t == 15 then // Only possible for encoding A1
        if (t == 15)
            // data = PCStoreValue();
            data = ReadCoreReg (PC_REG, &success);
        else
            // data = R[t];
            data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + t, 0, &success);

        if (!success)
            return false;

        EmulateInstruction::Context context;
        context.type = eContextRegisterStore;

        // if UnalignedSupport() || address<1:0> == '00' || CurrentInstrSet() == InstrSet_ARM then
        if (UnalignedSupport ()
            || (BitIsClear (address, 1) && BitIsClear (address, 0))
            || CurrentInstrSet() == eModeARM)
        {
            // MemU[address,4] = data;

            RegisterInfo base_reg;
            GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 +  n, base_reg);

            RegisterInfo data_reg;
            GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + t, data_reg);

            context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - base_address);
            if (!MemUWrite (context, address, data, addr_byte_size))
                return false;

        }
        else
            // MemU[address,4] = bits(32) UNKNOWN;
            WriteBits32UnknownToMemory (address);

        // if wback then R[n] = offset_addr;
        if (wback)
        {
            context.type = eContextRegisterLoad;
            context.SetAddress (offset_addr);
            if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr))
                return false;
        }

    }
    return true;
}

bool
EmulateInstructionARM::EmulateSTRBThumb (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    if ConditionPassed() then
        EncodingSpecificOperations(); NullCheckIfThumbEE(n);
        offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
        address = if index then offset_addr else R[n];
        MemU[address,1] = R[t]<7:0>;
        if wback then R[n] = offset_addr;
#endif


    bool success = false;

    if (ConditionPassed(opcode))
    {
        uint32_t t;
        uint32_t n;
        uint32_t imm32;
        bool index;
        bool add;
        bool wback;
        // EncodingSpecificOperations(); NullCheckIfThumbEE(n);
        switch (encoding)
        {
            case eEncodingT1:
                // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm5, 32);
                t = Bits32 (opcode, 2, 0);
                n = Bits32 (opcode, 5, 3);
                imm32 = Bits32 (opcode, 10, 6);

                // index = TRUE; add = TRUE; wback = FALSE;
                index = true;
                add = true;
                wback = false;
                break;

            case eEncodingT2:
                // if Rn == '1111' then UNDEFINED;
                if (Bits32 (opcode, 19, 16) == 15)
                    return false;

                // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm12, 32);
                t = Bits32 (opcode, 15, 12);
                n = Bits32 (opcode, 19, 16);
                imm32 = Bits32 (opcode, 11, 0);

                // index = TRUE; add = TRUE; wback = FALSE;
                index = true;
                add = true;
                wback = false;

                // if BadReg(t) then UNPREDICTABLE;
                if (BadReg (t))
                    return false;
                break;

            case eEncodingT3:
                // if P == '1' && U == '1' && W == '0' then SEE STRBT;
                // if Rn == '1111' || (P == '0' && W == '0') then UNDEFINED;
                if (Bits32 (opcode, 19, 16) == 15)
                    return false;

                // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
                t = Bits32 (opcode, 15, 12);
                n = Bits32 (opcode, 19, 16);
                imm32 = Bits32 (opcode, 7, 0);

                // index = (P == '1'); add = (U == '1'); wback = (W == '1');
                index = BitIsSet (opcode, 10);
                add = BitIsSet (opcode, 9);
                wback = BitIsSet (opcode, 8);

                // if BadReg(t) || (wback && n == t) then UNPREDICTABLE
                if ((BadReg (t)) || (wback && (n == t)))
                    return false;
                break;

            default:
                return false;
        }

        addr_t offset_addr;
        addr_t address;
        addr_t base_address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
        if (!success)
            return false;

        // offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
        if (add)
            offset_addr = base_address + imm32;
        else
            offset_addr = base_address - imm32;

        // address = if index then offset_addr else R[n];
        if (index)
            address = offset_addr;
        else
            address = base_address;

        // MemU[address,1] = R[t]<7:0>
        RegisterInfo base_reg;
        GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);

        RegisterInfo data_reg;
        GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + t, data_reg);

        EmulateInstruction::Context context;
        context.type = eContextRegisterStore;
        context.SetRegisterToRegisterPlusOffset (data_reg, base_reg, address - base_address);

        uint32_t data = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + t, 0, &success);
        if (!success)
            return false;

        data = Bits32 (data, 7, 0);

        if (!MemUWrite (context, address, data, 1))
            return false;

        // if wback then R[n] = offset_addr;
        if (wback)
        {
            context.type = eContextRegisterLoad;
            context.SetAddress (offset_addr);
            if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr))
                return false;
        }

    }

    return true;
}

// STRH (register) calculates an address from a base register value and an offset register value, and stores a
// halfword from a register to memory.  The offset register alue can be shifted left by 0, 1, 2, or 3 bits.
bool
EmulateInstructionARM::EmulateSTRHRegister (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    if ConditionPassed() then
        EncodingSpecificOperations(); NullCheckIfThumbEE(n);
        offset = Shift(R[m], shift_t, shift_n, APSR.C);
        offset_addr = if add then (R[n] + offset) else (R[n] - offset);
        address = if index then offset_addr else R[n];
        if UnalignedSupport() || address<0> == '0' then
            MemU[address,2] = R[t]<15:0>;
        else // Can only occur before ARMv7
            MemU[address,2] = bits(16) UNKNOWN;
        if wback then R[n] = offset_addr;
#endif

    bool success = false;

    if (ConditionPassed(opcode))
    {
        uint32_t t;
        uint32_t n;
        uint32_t m;
        bool index;
        bool add;
        bool wback;
        ARM_ShifterType shift_t;
        uint32_t shift_n;

        // EncodingSpecificOperations(); NullCheckIfThumbEE(n);
        switch (encoding)
        {
            case eEncodingT1:
                // if CurrentInstrSet() == InstrSet_ThumbEE then SEE "Modified operation in ThumbEE";
                // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
                t = Bits32 (opcode, 2, 0);
                n = Bits32 (opcode, 5, 3);
                m = Bits32 (opcode, 8, 6);

                // index = TRUE; add = TRUE; wback = FALSE;
                index = true;
                add = true;
                wback = false;

                // (shift_t, shift_n) = (SRType_LSL, 0);
                shift_t = SRType_LSL;
                shift_n = 0;

                break;

            case eEncodingT2:
                // if Rn == '1111' then UNDEFINED;
                // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
                t = Bits32 (opcode, 15, 12);
                n = Bits32 (opcode, 19, 16);
                m = Bits32 (opcode, 3, 0);
                if (n == 15)
                    return false;

                // index = TRUE; add = TRUE; wback = FALSE;
                index = true;
                add = true;
                wback = false;

                // (shift_t, shift_n) = (SRType_LSL, UInt(imm2));
                shift_t = SRType_LSL;
                shift_n = Bits32 (opcode, 5, 4);

                // if BadReg(t) || BadReg(m) then UNPREDICTABLE;
                if (BadReg (t) || BadReg (m))
                    return false;

                break;

            case eEncodingA1:
                // if P == '0' && W == '1' then SEE STRHT;
                // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
                t = Bits32 (opcode, 15, 12);
                n = Bits32 (opcode, 19, 16);
                m = Bits32 (opcode, 3, 0);

                // index = (P == '1');	add = (U == '1');	wback = (P == '0') || (W == '1');
                index = BitIsSet (opcode, 24);
                add = BitIsSet (opcode, 23);
                wback = (BitIsClear (opcode, 24) || BitIsSet (opcode, 21));

                // (shift_t, shift_n) = (SRType_LSL, 0);
                shift_t = SRType_LSL;
                shift_n = 0;

                // if t == 15 || m == 15 then UNPREDICTABLE;
                if ((t == 15) || (m == 15))
                    return false;

                // if wback && (n == 15 || n == t) then UNPREDICTABLE;
                if (wback && ((n == 15) || (n == t)))
                    return false;

                break;

            default:
                return false;
        }

        uint32_t Rm = ReadCoreReg (m, &success);
        if (!success)
            return false;

        uint32_t Rn = ReadCoreReg (n, &success);
        if (!success)
            return false;

        // offset = Shift(R[m], shift_t, shift_n, APSR.C);
        uint32_t offset = Shift (Rm, shift_t, shift_n, APSR_C, &success);
        if (!success)
            return false;

        // offset_addr = if add then (R[n] + offset) else (R[n] - offset);
        addr_t offset_addr;
        if (add)
            offset_addr = Rn + offset;
        else
            offset_addr = Rn - offset;

        // address = if index then offset_addr else R[n];
        addr_t address;
        if (index)
            address = offset_addr;
        else
            address = Rn;

        EmulateInstruction::Context context;
        context.type = eContextRegisterStore;
        RegisterInfo base_reg;
        GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
        RegisterInfo offset_reg;
        GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + m, offset_reg);

        // if UnalignedSupport() || address<0> == '0' then
        if (UnalignedSupport() || BitIsClear (address, 0))
        {
            // MemU[address,2] = R[t]<15:0>;
            uint32_t Rt = ReadCoreReg (t, &success);
            if (!success)
                return false;

            EmulateInstruction::Context context;
            context.type = eContextRegisterStore;
            RegisterInfo base_reg;
            GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + n, base_reg);
            RegisterInfo offset_reg;
            GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + m, offset_reg);
            RegisterInfo data_reg;
            GetRegisterInfo (eRegisterKindDWARF, dwarf_r0 + t, data_reg);
            context.SetRegisterToRegisterPlusIndirectOffset (base_reg, offset_reg, data_reg);

            if (!MemUWrite (context, address, Bits32 (Rt, 15, 0), 2))
                return false;
        }
        else // Can only occur before ARMv7
        {
            // MemU[address,2] = bits(16) UNKNOWN;
        }

        // if wback then R[n] = offset_addr;
        if (wback)
        {
            context.type = eContextAdjustBaseRegister;
            context.SetAddress (offset_addr);
            if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, offset_addr))
                return false;
        }
    }

    return true;
}

// Add with Carry (immediate) adds an immediate value and the carry flag value to a register value,
// and writes the result to the destination register.  It can optionally update the condition flags
// based on the result.
bool
EmulateInstructionARM::EmulateADCImm (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    // ARM pseudo code...
    if ConditionPassed() then
        EncodingSpecificOperations();
        (result, carry, overflow) = AddWithCarry(R[n], imm32, APSR.C);
        if d == 15 then         // Can only occur for ARM encoding
            ALUWritePC(result); // setflags is always FALSE here
        else
            R[d] = result;
            if setflags then
                APSR.N = result<31>;
                APSR.Z = IsZeroBit(result);
                APSR.C = carry;
                APSR.V = overflow;
#endif

    bool success = false;

    if (ConditionPassed(opcode))
    {
        uint32_t Rd, Rn;
        uint32_t imm32; // the immediate value to be added to the value obtained from Rn
        bool setflags;
        switch (encoding)
        {
        case eEncodingT1:
            Rd = Bits32(opcode, 11, 8);
            Rn = Bits32(opcode, 19, 16);
            setflags = BitIsSet(opcode, 20);
            imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
            if (BadReg(Rd) || BadReg(Rn))
                return false;
            break;
        case eEncodingA1:
            Rd = Bits32(opcode, 15, 12);
            Rn = Bits32(opcode, 19, 16);
            setflags = BitIsSet(opcode, 20);
            imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)

            if (Rd == 15 && setflags)
                return EmulateSUBSPcLrEtc (opcode, encoding);
            break;
        default:
            return false;
        }

        // Read the first operand.
        int32_t val1 = ReadCoreReg(Rn, &success);
        if (!success)
            return false;

        AddWithCarryResult res = AddWithCarry(val1, imm32, APSR_C);

        EmulateInstruction::Context context;
        context.type = EmulateInstruction::eContextImmediate;
        context.SetNoArgs ();

        if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res.overflow))
            return false;
    }
    return true;
}

// Add with Carry (register) adds a register value, the carry flag value, and an optionally-shifted
// register value, and writes the result to the destination register.  It can optionally update the
// condition flags based on the result.
bool
EmulateInstructionARM::EmulateADCReg (const uint32_t opcode, const ARMEncoding encoding)
{
#if 0
    // ARM pseudo code...
    if ConditionPassed() then
        EncodingSpecificOperations();
        shifted = Shift(R[m], shift_t, shift_n, APSR.C);
        (result, carry, overflow) = AddWithCarry(R[n], shifted, APSR.C);
        if d == 15 then         // Can only occur for ARM encoding
            ALUWritePC(result); // setflags is always FALSE here
        else
            R[d] = result;
            if setflags then
                APSR.N = result<31>;
                APSR.Z = IsZeroBit(result);
                APSR.C = carry;
                APSR.V = overflow;
#endif

    bool success = false;

    if (ConditionPassed(opcode))
    {
        uint32_t Rd, Rn, Rm;
        ARM_ShifterType shift_t;
        uint32_t shift_n; // the shift applied to the value read from Rm
        bool setflags;
        switch (encoding)
        {
        case eEncodingT1:
            Rd = Rn = Bits32(opcode, 2, 0);
            Rm = Bits32(opcode, 5, 3);
            setflags = !InITBlock();
            shift_t = SRType_LSL;
            shift_n = 0;
            break;
        case eEncodingT2:
            Rd = Bits32(opcode, 11, 8);
            Rn = Bits32(opcode, 19, 16);
            Rm = Bits32(opcode, 3, 0);
            setflags = BitIsSet(opcode, 20);
            shift_n = DecodeImmShiftThumb(opcode, shift_t);
            if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm))
                return false;
            break;
        case eEncodingA1:
            Rd = Bits32(opcode, 15, 12);
            Rn = Bits32(opcode, 19, 16);
            Rm = Bits32(opcode, 3, 0);
            setflags = BitIsSet(opcode, 20);
            shift_n = DecodeImmShiftARM(opcode, shift_t);

            if (Rd == 15 && setflags)
                return EmulateSUBSPcLrEtc (opcode, encoding);
            break;
        default:
            return false;
        }

        // Read the first operand.
        int32_t val1 = ReadCoreReg(Rn, &success);
        if (!success)
            return false;

        // Read the second operand.
        int32_t val2 = ReadCoreReg(Rm, &success);
        if (!success)
            return false;

        uint32_t shifted = Shift(val2, shift_t, shift_n, APSR_C, &success);
        if (!success)
            return false;
        AddWithCarryResult res = AddWithCarry(val1, shifted, APSR_C);

        EmulateInstruction::Context context;
        context.type = EmulateInstruction::eContextImmediate;
        context.SetNoArgs ();

        if (!WriteCoreRegOptionalFlags(context, res.result, Rd, setflags, res.carry_out, res