| /system/core/libpixelflinger/codeflinger/ |
| ARMAssemblerInterface.h | 123 int Rd, int Rn,
128 int Rd, int Rm, int Rs, int Rn) = 0;
130 int Rd, int Rm, int Rs) = 0;
153 virtual void LDR (int cc, int Rd,
155 virtual void LDRB(int cc, int Rd,
157 virtual void STR (int cc, int Rd,
159 virtual void STRB(int cc, int Rd,
162 virtual void LDRH (int cc, int Rd,
164 virtual void LDRSB(int cc, int Rd,
166 virtual void LDRSH(int cc, int Rd,
[all...] |
| ARMAssemblerInterface.cpp | 68 void ARMAssemblerInterface::ADDR_LDR(int cc, int Rd,
71 LDR(cc, Rd, Rn, offset);
73 void ARMAssemblerInterface::ADDR_STR(int cc, int Rd,
76 STR(cc, Rd, Rn, offset);
79 int Rd, int Rn, uint32_t Op2)
81 dataProcessing(opADD, cc, s, Rd, Rn, Op2);
84 int Rd, int Rn, uint32_t Op2)
86 dataProcessing(opSUB, cc, s, Rd, Rn, Op2);
|
| ARMAssemblerProxy.cpp | 161 int Rd, int Rn, uint32_t Op2)
163 mTarget->dataProcessing(opcode, cc, s, Rd, Rn, Op2);
166 void ARMAssemblerProxy::MLA(int cc, int s, int Rd, int Rm, int Rs, int Rn) {
167 mTarget->MLA(cc, s, Rd, Rm, Rs, Rn);
169 void ARMAssemblerProxy::MUL(int cc, int s, int Rd, int Rm, int Rs) {
170 mTarget->MUL(cc, s, Rd, Rm, Rs);
212 void ARMAssemblerProxy::LDR(int cc, int Rd, int Rn, uint32_t offset) {
213 mTarget->LDR(cc, Rd, Rn, offset);
215 void ARMAssemblerProxy::LDRB(int cc, int Rd, int Rn, uint32_t offset) {
216 mTarget->LDRB(cc, Rd, Rn, offset)
[all...] |
| Arm64Assembler.cpp | 341 int s, int Rd, int Rn, uint32_t Op2)
398 case opADD: *mPC++ = A64_ADD_W(Rd, Rn, Rm, shift, amount); break;
399 case opAND: *mPC++ = A64_AND_W(Rd, Rn, Rm, shift, amount); break;
400 case opORR: *mPC++ = A64_ORR_W(Rd, Rn, Rm, shift, amount); break;
401 case opMVN: *mPC++ = A64_ORN_W(Rd, Rn, Rm, shift, amount); break;
402 case opSUB: *mPC++ = A64_SUB_W(Rd, Rn, Rm, shift, amount, s);break;
409 int s, int Rd, int Rn, uint32_t Op2)
416 Wd = Rd;
456 *mPC++ = A64_CSEL_W(Rd, mTmpReg1, Rd, cc)
[all...] |
| Arm64Assembler.h | 99 int Rd, int Rn,
102 int Rd, int Rm, int Rs, int Rn);
104 int Rd, int Rm, int Rs);
123 virtual void ADDR_LDR(int cc, int Rd,
125 virtual void ADDR_ADD(int cc, int s, int Rd,
127 virtual void ADDR_SUB(int cc, int s, int Rd,
129 virtual void ADDR_STR (int cc, int Rd,
132 virtual void LDR (int cc, int Rd,
134 virtual void LDRB(int cc, int Rd,
136 virtual void STR (int cc, int Rd,
[all...] |
| ARMAssemblerProxy.h | 80 int Rd, int Rn,
83 int Rd, int Rm, int Rs, int Rn);
85 int Rd, int Rm, int Rs);
104 virtual void LDR (int cc, int Rd,
106 virtual void LDRB(int cc, int Rd,
108 virtual void STR (int cc, int Rd,
110 virtual void STRB(int cc, int Rd,
112 virtual void LDRH (int cc, int Rd,
114 virtual void LDRSB(int cc, int Rd,
116 virtual void LDRSH(int cc, int Rd,
[all...] |
| ARMAssembler.h | 91 int Rd, int Rn,
94 int Rd, int Rm, int Rs, int Rn);
96 int Rd, int Rm, int Rs);
115 virtual void LDR (int cc, int Rd,
117 virtual void LDRB(int cc, int Rd,
119 virtual void STR (int cc, int Rd,
121 virtual void STRB(int cc, int Rd,
123 virtual void LDRH (int cc, int Rd,
125 virtual void LDRSB(int cc, int Rd,
127 virtual void LDRSH(int cc, int Rd,
[all...] |
| MIPSAssembler.cpp | 355 void ArmToMipsAssembler::protectConditionalOperands(int Rd)
357 if (Rd == cond.r1) {
361 if (cond.type == CMP_COND && Rd == cond.r2) {
418 int s, int Rd, int Rn, uint32_t Op2)
424 protectConditionalOperands(Rd);
435 mMips->AND(Rd, Rn, src);
437 mMips->ANDI(Rd, Rn, src);
444 mMips->ADDU(Rd, Rn, src);
446 mMips->ADDIU(Rd, Rn, src);
453 mMips->SUBU(Rd, Rn, src)
[all...] |
| MIPSAssembler.h | 91 int Rd, int Rn,
94 int Rd, int Rm, int Rs, int Rn);
96 int Rd, int Rm, int Rs);
115 virtual void LDR (int cc, int Rd,
117 virtual void LDRB(int cc, int Rd,
119 virtual void STR (int cc, int Rd,
121 virtual void STRB(int cc, int Rd,
123 virtual void LDRH (int cc, int Rd,
125 virtual void LDRSB(int cc, int Rd,
127 virtual void LDRSH(int cc, int Rd,
[all...] |
| ARMAssembler.cpp | 217 int s, int Rd, int Rn, uint32_t Op2)
219 *mPC++ = (cc<<28) | (opcode<<21) | (s<<20) | (Rn<<16) | (Rd<<12) | Op2;
229 int Rd, int Rm, int Rs, int Rn) {
230 if (Rd == Rm) { int t = Rm; Rm=Rs; Rs=t; }
231 LOG_FATAL_IF(Rd==Rm, "MLA(r%u,r%u,r%u,r%u)", Rd,Rm,Rs,Rn);
233 (Rd<<16) | (Rn<<12) | (Rs<<8) | 0x90 | Rm;
236 int Rd, int Rm, int Rs) {
237 if (Rd == Rm) { int t = Rm; Rm=Rs; Rs=t; }
238 LOG_FATAL_IF(Rd==Rm, "MUL(r%u,r%u,r%u)", Rd,Rm,Rs)
[all...] |
| /art/disassembler/ |
| disassembler_arm.cc | 274 // Show only Rd and Rm.
287 // Rd is unused (and not shown), and we don't show the 's' suffix either.
511 ArmRegister Rd(instr, 8);
523 args << Rt << "," << Rd << ", [" << Rn;
538 args << Rd << ", " << Rt << ", [" << Rn << ", #" << (imm8 << 2) << "]";
539 if (Rd.r == 13 || Rd.r == 15 || Rt.r == 13 || Rt.r == 15 || Rn.r == 15 ||
540 Rd.r == Rn.r || Rd.r == Rt.r) {
550 Rd = ArmRegister(instr, 0)
[all...] |
| /system/core/libpixelflinger/tests/arch-arm64/assembler/ |
| arm64_assembler_test.cpp | 414 void dataOpTest(dataOpTest_t test, ARMAssemblerInterface *a64asm, uint32_t Rd = 0,
428 regs[Rd] = test.RdValue;
450 case INSTR_ADD: a64asm->ADD(test.cond, test.setFlags, Rd,Rn,op2); break;
451 case INSTR_SUB: a64asm->SUB(test.cond, test.setFlags, Rd,Rn,op2); break;
452 case INSTR_RSB: a64asm->RSB(test.cond, test.setFlags, Rd,Rn,op2); break;
453 case INSTR_AND: a64asm->AND(test.cond, test.setFlags, Rd,Rn,op2); break;
454 case INSTR_ORR: a64asm->ORR(test.cond, test.setFlags, Rd,Rn,op2); break;
455 case INSTR_BIC: a64asm->BIC(test.cond, test.setFlags, Rd,Rn,op2); break;
456 case INSTR_MUL: a64asm->MUL(test.cond, test.setFlags, Rd,Rm,Rs); break;
457 case INSTR_MLA: a64asm->MLA(test.cond, test.setFlags, Rd,Rm,Rs,Rn); break
[all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.cpp | 669 unsigned Rd = fieldFromInstruction(Insn, 0, 5);
674 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
677 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
[all...] |
| /external/vixl/src/a64/ |
| assembler-a64.cc | 533 void Assembler::adr(const Register& rd, int imm21) {
534 VIXL_ASSERT(rd.Is64Bits());
535 Emit(ADR | ImmPCRelAddress(imm21) | Rd(rd));
539 void Assembler::adr(const Register& rd, Label* label) {
540 adr(rd, UpdateAndGetByteOffsetTo(label));
544 void Assembler::add(const Register& rd,
547 AddSub(rd, rn, operand, LeaveFlags, ADD);
551 void Assembler::adds(const Register& rd,
554 AddSub(rd, rn, operand, SetFlags, ADD)
[all...] |
| disasm-a64.h | 70 return (instr->Rd() == kZeroRegCode);
|
| simulator-a64.cc | 509 instr->Rd(),
615 set_reg(reg_size, instr->Rd(), new_val, instr->RdMode());
660 set_reg(reg_size, instr->Rd(), new_val);
706 set_reg(reg_size, instr->Rd(), result, instr->RdMode());
1037 unsigned reg_code = instr->Rd();
1054 set_xreg(instr->Rd(), new_xn_val);
1076 set_reg(reg_size, instr->Rd(), new_val);
1081 unsigned dst = instr->Rd();
[all...] |
| /external/lldb/source/Plugins/Instruction/ARM/ |
| EmulateInstructionARM.cpp | 618 uint32_t Rd; // the destination register
622 Rd = 7;
626 Rd = Bits32(opcode, 15, 12);
641 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rd, addr))
677 uint32_t Rd; // the destination register
680 Rd = 7;
683 Rd = 12;
690 if (Rd == GetFramePointerRegisterNumber())
698 if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + Rd, sp))
740 uint32_t Rd; // the destination registe
[all...] |
| /external/chromium_org/v8/src/arm64/ |
| disasm-arm64.h | 51 return (instr->Rd() == kZeroRegCode);
|
| assembler-arm64.cc | 522 // Instruction to patch must be 'ldr rd, [pc, #offset]' with offset == 0.
538 // Instruction to patch must be 'ldr rd, [pc, #offset]' with offset == 0.
3128 Register rd = Register::XRegFromCode(rd_code); local
[all...] |
| instructions-arm64.h | 218 // Indicate whether Rd can be the stack pointer or the zero register. This
219 // does not check that the instruction actually has an Rd field.
221 // The following instructions use csp or wsp as Rd:
334 (Rd() == Rm()) &&
335 (Rd() == n);
|
| simulator-arm64.cc | 887 set_reg<T>(instr->Rd(), new_val);
961 set_reg<T>(instr->Rd(), result);
[all...] |
| instrument-arm64.cc | 246 (instr->Rd() == 31) && (instr->Rn() == 31)) {
266 if (instr->IsMovn() && (instr->Rd() == kZeroRegCode)) {
459 (instr->Rd() == 31) && (instr->Rn() == 31)) {
|
| /external/chromium_org/third_party/mesa/src/src/mesa/swrast/ |
| s_blend.c | 489 const GLfloat Rd = dest[i][RCOMP];
511 sR = Rd;
516 sR = 1.0F - Rd;
673 dR = Rd;
678 dR = 1.0F - Rd;
743 r = Rs * sR + Rd * dR;
749 r = Rs * sR - Rd * dR;
755 r = Rd * dR - Rs * sR;
761 r = MIN2( Rd, Rs );
766 r = MAX2( Rd, Rs )
[all...] |
| /external/mesa3d/src/mesa/swrast/ |
| s_blend.c | 489 const GLfloat Rd = dest[i][RCOMP];
511 sR = Rd;
516 sR = 1.0F - Rd;
673 dR = Rd;
678 dR = 1.0F - Rd;
743 r = Rs * sR + Rd * dR;
749 r = Rs * sR - Rd * dR;
755 r = Rd * dR - Rs * sR;
761 r = MIN2( Rd, Rs );
766 r = MAX2( Rd, Rs )
[all...] |
