| /system/core/libpixelflinger/codeflinger/ |
| ARMAssemblerInterface.h | 81 virtual uint32_t reg_imm(int Rm, int type, uint32_t shift) = 0;
82 virtual uint32_t reg_rrx(int Rm) = 0;
83 virtual uint32_t reg_reg(int Rm, int type, int Rs) = 0;
87 // (immediate and Rm can be negative, which indicates U=0)
90 virtual uint32_t reg_scale_pre(int Rm, int type=0, uint32_t shift=0, int W=0) = 0;
91 virtual uint32_t reg_scale_post(int Rm, int type=0, uint32_t shift=0) = 0;
94 // (immediate and Rm can be negative, which indicates U=0)
97 virtual uint32_t reg_pre(int Rm, int W=0) = 0;
98 virtual uint32_t reg_post(int Rm) = 0;
128 int Rd, int Rm, int Rs, int Rn) = 0
[all...] |
| ARMAssembler.cpp | 229 int Rd, int Rm, int Rs, int Rn) {
230 if (Rd == Rm) { int t = Rm; Rm=Rs; Rs=t; }
231 LOG_FATAL_IF(Rd==Rm, "MLA(r%u,r%u,r%u,r%u)", Rd,Rm,Rs,Rn);
233 (Rd<<16) | (Rn<<12) | (Rs<<8) | 0x90 | Rm;
236 int Rd, int Rm, int Rs) {
237 if (Rd == Rm) { int t = Rm; Rm=Rs; Rs=t; }
[all...] |
| ARMAssemblerProxy.cpp | 93 uint32_t ARMAssemblerProxy::reg_imm(int Rm, int type, uint32_t shift)
95 return mTarget->reg_imm(Rm, type, shift);
98 uint32_t ARMAssemblerProxy::reg_rrx(int Rm)
100 return mTarget->reg_rrx(Rm);
103 uint32_t ARMAssemblerProxy::reg_reg(int Rm, int type, int Rs)
105 return mTarget->reg_reg(Rm, type, Rs);
111 // (immediate and Rm can be negative, which indicates U=0)
122 uint32_t ARMAssemblerProxy::reg_scale_pre(int Rm, int type, uint32_t shift, int W)
124 return mTarget->reg_scale_pre(Rm, type, shift, W);
127 uint32_t ARMAssemblerProxy::reg_scale_post(int Rm, int type, uint32_t shift
[all...] |
| ARMAssembler.h | 70 virtual uint32_t reg_imm(int Rm, int type, uint32_t shift);
71 virtual uint32_t reg_rrx(int Rm);
72 virtual uint32_t reg_reg(int Rm, int type, int Rs);
76 // (immediate and Rm can be negative, which indicates U=0)
79 virtual uint32_t reg_scale_pre(int Rm, int type=0, uint32_t shift=0, int W=0);
80 virtual uint32_t reg_scale_post(int Rm, int type=0, uint32_t shift=0);
83 // (immediate and Rm can be negative, which indicates U=0)
86 virtual uint32_t reg_pre(int Rm, int W=0);
87 virtual uint32_t reg_post(int Rm);
94 int Rd, int Rm, int Rs, int Rn)
[all...] |
| ARMAssemblerProxy.h | 59 virtual uint32_t reg_imm(int Rm, int type, uint32_t shift);
60 virtual uint32_t reg_rrx(int Rm);
61 virtual uint32_t reg_reg(int Rm, int type, int Rs);
65 // (immediate and Rm can be negative, which indicates U=0)
68 virtual uint32_t reg_scale_pre(int Rm, int type=0, uint32_t shift=0, int W=0);
69 virtual uint32_t reg_scale_post(int Rm, int type=0, uint32_t shift=0);
72 // (immediate and Rm can be negative, which indicates U=0)
75 virtual uint32_t reg_pre(int Rm, int W=0);
76 virtual uint32_t reg_post(int Rm);
83 int Rd, int Rm, int Rs, int Rn)
[all...] |
| Arm64Assembler.h | 83 virtual uint32_t reg_imm(int Rm, int type, uint32_t shift);
84 virtual uint32_t reg_rrx(int Rm);
85 virtual uint32_t reg_reg(int Rm, int type, int Rs);
90 virtual uint32_t reg_scale_pre(int Rm, int type=0, uint32_t shift=0, int W=0);
91 virtual uint32_t reg_scale_post(int Rm, int type=0, uint32_t shift=0);
94 virtual uint32_t reg_pre(int Rm, int W=0);
95 virtual uint32_t reg_post(int Rm);
102 int Rd, int Rm, int Rs, int Rn);
104 int Rd, int Rm, int Rs);
106 int RdLo, int RdHi, int Rm, int Rs)
[all...] |
| Arm64Assembler.cpp | 376 uint32_t Rm;
382 Rm = mAddrMode.reg_imm_Rm;
388 Rm = Op2;
398 case opADD: *mPC++ = A64_ADD_W(Rd, Rn, Rm, shift, amount); break;
399 case opAND: *mPC++ = A64_AND_W(Rd, Rn, Rm, shift, amount); break;
400 case opORR: *mPC++ = A64_ORR_W(Rd, Rn, Rm, shift, amount); break;
401 case opMVN: *mPC++ = A64_ORN_W(Rd, Rn, Rm, shift, amount); break;
402 case opSUB: *mPC++ = A64_SUB_W(Rd, Rn, Rm, shift, amount, s);break;
472 int Rm = mAddrMode.reg_imm_Rm;
474 *mPC++ = A64_ADD_X_Wm_SXTW(Rd, Rn, Rm, amount)
[all...] |
| MIPSAssembler.h | 68 virtual uint32_t reg_imm(int Rm, int type, uint32_t shift);
69 virtual uint32_t reg_rrx(int Rm);
70 virtual uint32_t reg_reg(int Rm, int type, int Rs);
74 // (immediate and Rm can be negative, which indicates U=0)
77 virtual uint32_t reg_scale_pre(int Rm, int type=0, uint32_t shift=0, int W=0);
78 virtual uint32_t reg_scale_post(int Rm, int type=0, uint32_t shift=0);
81 // (immediate and Rm can be negative, which indicates U=0)
84 virtual uint32_t reg_pre(int Rm, int W=0);
85 virtual uint32_t reg_post(int Rm);
94 int Rd, int Rm, int Rs, int Rn)
[all...] |
| MIPSAssembler.cpp | 234 uint32_t ArmToMipsAssembler::reg_imm(int Rm, int type, uint32_t shift)
236 amode.reg = Rm;
242 uint32_t ArmToMipsAssembler::reg_rrx(int Rm)
248 uint32_t ArmToMipsAssembler::reg_reg(int Rm, int type, int Rs)
256 // LDR(B)/STR(B)/PLD (immediate and Rm can be negative, which indicate U=0)
277 uint32_t ArmToMipsAssembler::reg_scale_pre(int Rm, int type,
282 amode.reg = Rm;
289 uint32_t ArmToMipsAssembler::reg_scale_post(int Rm, int type, uint32_t shift)
295 // LDRH/LDRSB/LDRSH/STRH (immediate and Rm can be negative, which indicate U=0)
319 uint32_t ArmToMipsAssembler::reg_pre(int Rm, int W
[all...] |
| /cts/libs/vogar-expect/src/vogar/commands/ |
| Rm.java | 22 * A rm command.
24 public final class Rm {
27 new Command("rm", "-f", file.getPath()).execute();
31 new Command("rm", "-rf", directory.getPath()).execute();
|
| /art/disassembler/ |
| disassembler_arm.cc | 148 struct Rm {
149 explicit Rm(uint32_t instruction) : shift((instruction >> 4) & 0xff), rm(instruction & 0xf) {}
151 ArmRegister rm; member in struct:art::arm::Rm
153 std::ostream& operator<<(std::ostream& os, const Rm& r) {
154 os << r.rm;
274 // Show only Rd and Rm.
640 // |111|0101| op3|S| Rn |imm3| Rd |i2|ty| Rm |
649 ArmRegister Rm(instr, 0);
733 args << Rm;
1487 args << Rt << ", [" << Rn << ", " << rm; local
1704 args << rdn << ", " << rm; local
1717 args << DN_Rdn << ", " << rm; local
1728 args << DN_Rdn << ", " << rm; local
1738 args << N_Rn << ", " << rm; local
1746 args << rm; local
[all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | [all...] |
| /system/core/libpixelflinger/tests/arch-arm64/assembler/ |
| arm64_assembler_test.cpp | 415 uint32_t Rn = 1, uint32_t Rm = 2, uint32_t Rs = 3)
440 op2 = Rm;
441 regs[Rm] = test.RmValue;
445 op2 = a64asm->reg_imm(Rm, test.shiftMode, test.shiftAmount);
446 regs[Rm] = test.RmValue;
456 case INSTR_MUL: a64asm->MUL(test.cond, test.setFlags, Rd,Rm,Rs); break;
457 case INSTR_MLA: a64asm->MLA(test.cond, test.setFlags, Rd,Rm,Rs,Rn); break;
461 case INSTR_SMULBB:a64asm->SMULBB(test.cond, Rd,Rm,Rs); break;
462 case INSTR_SMULBT:a64asm->SMULBT(test.cond, Rd,Rm,Rs); break;
463 case INSTR_SMULTB:a64asm->SMULTB(test.cond, Rd,Rm,Rs); break
[all...] |
| /external/chromium_org/v8/src/arm64/ |
| disasm-arm64.h | 59 return (instr->Rm() == kZeroRegCode);
|
| simulator-arm64.cc | 875 T op2 = reg<T>(instr->Rm());
954 T op2 = reg<T>(instr->Rm());
2012 T rm = reg<T>(instr->Rm()); local
2027 unsignedT rm = static_cast<unsignedT>(reg<T>(instr->Rm())); local
[all...] |
| assembler-arm64.cc | [all...] |
| instructions-arm64.h | 334 (Rd() == Rm()) &&
|
| /external/vixl/src/a64/ |
| disasm-a64.h | 78 return (instr->Rm() == kZeroRegCode);
|
| simulator-a64.cc | 622 reg(reg_size, instr->Rm()),
638 reg(reg_size, instr->Rm()),
647 int64_t op2 = reg(reg_size, instr->Rm());
668 int64_t op2 = ShiftOperand(reg_size, reg(reg_size, instr->Rm()), shift_type,
712 ConditionalCompareHelper(instr, reg(reg_size, instr->Rm()));
767 int64_t offset = ExtendValue(kXRegSize, xreg(instr->Rm()), ext,
1062 new_val = xreg(instr->Rm());
1151 int32_t rm = wreg(instr->Rm()); local
1164 int64_t rm = xreg(instr->Rm()); local
1177 uint32_t rm = static_cast<uint32_t>(wreg(instr->Rm())); local
1188 uint64_t rm = static_cast<uint64_t>(xreg(instr->Rm())); local
[all...] |
| assembler-a64.cc | 702 const Register& rm) {
704 VIXL_ASSERT(rd.size() == rm.size());
705 Emit(SF(rd) | LSLV | Rm(rm) | Rn(rn) | Rd(rd));
711 const Register& rm) {
713 VIXL_ASSERT(rd.size() == rm.size());
714 Emit(SF(rd) | LSRV | Rm(rm) | Rn(rn) | Rd(rd));
720 const Register& rm) {
722 VIXL_ASSERT(rd.size() == rm.size())
[all...] |
| /external/lldb/source/Plugins/Instruction/ARM/ |
| EmulateInstructionARM.cpp | 739 uint32_t Rm; // the source register
745 Rm = Bits32(opcode, 6, 3);
752 Rm = Bits32(opcode, 5, 3);
759 Rm = Bits32(opcode, 3, 0);
762 if (setflags && (BadReg(Rd) || BadReg(Rm)))
765 if (!setflags && (Rd == 15 || Rm == 15 || (Rd == 13 && Rm == 13)))
770 Rm = Bits32(opcode, 3, 0);
780 uint32_t result = ReadCoreReg(Rm, &success);
784 // The context specifies that Rm is to be moved into Rd
[all...] |
| /external/chromium_org/v8/src/arm/ |
| disasm-arm.cc | 91 void FormatNeonMemory(int Rn, int align, int Rm);
194 int rm = instr->RmValue(); local
196 PrintRegister(rm);
199 // Special case for using rm only.
315 } else if (format[1] == 'm') { // 'rm: Rm register
416 void Decoder::FormatNeonMemory(int Rn, int align, int Rm) {
423 if (Rm == 15) {
425 } else if (Rm == 13) {
429 "], r%d", Rm);
[all...] |
| /external/chromium_org/tools/telemetry/ |
| cloud_storage | 143 class Rm(command_line.Command):
192 commands = (Ls, Mv, Rm, Upload)
|
| /external/qemu/distrib/sdl-1.2.15/src/video/ |
| SDL_pixels.c | 143 int Rm=0,Gm=0,Bm=0;
152 Rm|=1<<i;
155 fprintf(stderr,"Rw=%d Rm=0x%02X\n",Rw,Rm);
189 r=(r<<format->Rloss)|((r*Rm)>>Rw);
|
| /external/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.cpp | [all...] |
