| /external/chromium_org/third_party/libvpx/source/libvpx/vp9/ |
| vp9_common.mk | 99 VP9_COMMON_SRCS-$(HAVE_DSPR2) += common/mips/dspr2/vp9_common_dspr2.h
100 VP9_COMMON_SRCS-$(HAVE_DSPR2) += common/mips/dspr2/vp9_convolve2_avg_dspr2.c
101 VP9_COMMON_SRCS-$(HAVE_DSPR2) += common/mips/dspr2/vp9_convolve2_avg_horiz_dspr2.c
102 VP9_COMMON_SRCS-$(HAVE_DSPR2) += common/mips/dspr2/vp9_convolve2_dspr2.c
103 VP9_COMMON_SRCS-$(HAVE_DSPR2) += common/mips/dspr2/vp9_convolve2_horiz_dspr2.c
104 VP9_COMMON_SRCS-$(HAVE_DSPR2) += common/mips/dspr2/vp9_convolve2_vert_dspr2.c
105 VP9_COMMON_SRCS-$(HAVE_DSPR2) += common/mips/dspr2/vp9_convolve8_avg_dspr2.c
106 VP9_COMMON_SRCS-$(HAVE_DSPR2) += common/mips/dspr2/vp9_convolve8_avg_horiz_dspr2.c
107 VP9_COMMON_SRCS-$(HAVE_DSPR2) += common/mips/dspr2/vp9_convolve8_dspr2.c
108 VP9_COMMON_SRCS-$(HAVE_DSPR2) += common/mips/dspr2/vp9_convolve8_horiz_dspr2.
[all...] |
| /external/libvpx/libvpx/vp9/ |
| vp9_common.mk | 94 VP9_COMMON_SRCS-$(HAVE_DSPR2) += common/mips/dspr2/vp9_common_dspr2.h
95 VP9_COMMON_SRCS-$(HAVE_DSPR2) += common/mips/dspr2/vp9_convolve2_avg_dspr2.c
96 VP9_COMMON_SRCS-$(HAVE_DSPR2) += common/mips/dspr2/vp9_convolve2_avg_horiz_dspr2.c
97 VP9_COMMON_SRCS-$(HAVE_DSPR2) += common/mips/dspr2/vp9_convolve2_dspr2.c
98 VP9_COMMON_SRCS-$(HAVE_DSPR2) += common/mips/dspr2/vp9_convolve2_horiz_dspr2.c
99 VP9_COMMON_SRCS-$(HAVE_DSPR2) += common/mips/dspr2/vp9_convolve2_vert_dspr2.c
100 VP9_COMMON_SRCS-$(HAVE_DSPR2) += common/mips/dspr2/vp9_convolve8_avg_dspr2.c
101 VP9_COMMON_SRCS-$(HAVE_DSPR2) += common/mips/dspr2/vp9_convolve8_avg_horiz_dspr2.c
102 VP9_COMMON_SRCS-$(HAVE_DSPR2) += common/mips/dspr2/vp9_convolve8_dspr2.c
103 VP9_COMMON_SRCS-$(HAVE_DSPR2) += common/mips/dspr2/vp9_convolve8_horiz_dspr2.
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSubtarget.cpp | 1 //===-- MipsSubtarget.cpp - Mips Subtarget Information --------------------===//
10 // This file implements the Mips specific subclass of TargetSubtargetInfo.
15 #include "Mips.h"
28 #define DEBUG_TYPE "mips-subtarget"
37 "mips-mixed-16-32",
44 "mips-os16",
47 "floating point as Mips 16"),
52 cl::desc("MIPS: mips16 hard float enable."),
58 cl::desc("MIPS: mips16 constant islands enable."),
61 /// Select the Mips CPU for the given triple and cpu name
[all...] |
| MipsSEISelDAGToDAG.cpp | 16 #include "Mips.h"
37 #define DEBUG_TYPE "mips-isel"
52 MIB.addReg(Mips::DSPPos, Flag);
55 MIB.addReg(Mips::DSPSCount, Flag);
58 MIB.addReg(Mips::DSPCarry, Flag);
61 MIB.addReg(Mips::DSPOutFlag, Flag);
64 MIB.addReg(Mips::DSPCCond, Flag);
67 MIB.addReg(Mips::DSPEFI, Flag);
74 case 0: return Mips::MSAIR;
75 case 1: return Mips::MSACSR
[all...] |
| MipsRegisterInfo.td | 1 //===-- MipsRegisterInfo.td - Mips Register defs -----------*- tablegen -*-===//
11 // Declarations that describe the MIPS register file
13 let Namespace = "Mips" in {
32 let Namespace = "Mips";
38 let Namespace = "Mips";
41 // Mips CPU Registers
44 // Mips 64-bit CPU Registers
50 // Mips 32-bit FPU Registers
53 // Mips 64-bit (aliased) FPU Registers
66 // Mips 128-bit (aliased) MSA Register
[all...] |
| /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp9/ |
| vp9_common.mk | 94 VP9_COMMON_SRCS-$(HAVE_DSPR2) += common/mips/dspr2/vp9_common_dspr2.h
95 VP9_COMMON_SRCS-$(HAVE_DSPR2) += common/mips/dspr2/vp9_convolve2_avg_dspr2.c
96 VP9_COMMON_SRCS-$(HAVE_DSPR2) += common/mips/dspr2/vp9_convolve2_avg_horiz_dspr2.c
97 VP9_COMMON_SRCS-$(HAVE_DSPR2) += common/mips/dspr2/vp9_convolve2_dspr2.c
98 VP9_COMMON_SRCS-$(HAVE_DSPR2) += common/mips/dspr2/vp9_convolve2_horiz_dspr2.c
99 VP9_COMMON_SRCS-$(HAVE_DSPR2) += common/mips/dspr2/vp9_convolve2_vert_dspr2.c
100 VP9_COMMON_SRCS-$(HAVE_DSPR2) += common/mips/dspr2/vp9_convolve8_avg_dspr2.c
101 VP9_COMMON_SRCS-$(HAVE_DSPR2) += common/mips/dspr2/vp9_convolve8_avg_horiz_dspr2.c
102 VP9_COMMON_SRCS-$(HAVE_DSPR2) += common/mips/dspr2/vp9_convolve8_dspr2.c
103 VP9_COMMON_SRCS-$(HAVE_DSPR2) += common/mips/dspr2/vp9_convolve8_horiz_dspr2.
[all...] |
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsAsmBackend.cpp | 1 //===-- MipsAsmBackend.cpp - Mips Asm Backend ----------------------------===//
46 case Mips::fixup_Mips_LO16:
47 case Mips::fixup_Mips_GPREL16:
48 case Mips::fixup_Mips_GPOFF_HI:
49 case Mips::fixup_Mips_GPOFF_LO:
50 case Mips::fixup_Mips_GOT_PAGE:
51 case Mips::fixup_Mips_GOT_OFST:
52 case Mips::fixup_Mips_GOT_DISP:
53 case Mips::fixup_Mips_GOT_LO16:
54 case Mips::fixup_Mips_CALL_LO16
[all...] |
| /external/llvm/test/CodeGen/Mips/msa/ |
| bit.ll | 3 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
12 %1 = tail call <16 x i8> @llvm.mips.sat.s.b(<16 x i8> %0, i32 7)
17 declare <16 x i8> @llvm.mips.sat.s.b(<16 x i8>, i32) nounwind
31 %1 = tail call <8 x i16> @llvm.mips.sat.s.h(<8 x i16> %0, i32 7)
36 declare <8 x i16> @llvm.mips.sat.s.h(<8 x i16>, i32) nounwind
50 %1 = tail call <4 x i32> @llvm.mips.sat.s.w(<4 x i32> %0, i32 7)
55 declare <4 x i32> @llvm.mips.sat.s.w(<4 x i32>, i32) nounwind
69 %1 = tail call <2 x i64> @llvm.mips.sat.s.d(<2 x i64> %0, i32 7)
74 declare <2 x i64> @llvm.mips.sat.s.d(<2 x i64>, i32) nounwind
88 %1 = tail call <16 x i8> @llvm.mips.sat.u.b(<16 x i8> %0, i32 7
[all...] |
| 2rf_fq.ll | 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
13 %1 = tail call <4 x float> @llvm.mips.ffql.w(<8 x i16> %0)
18 declare <4 x float> @llvm.mips.ffql.w(<8 x i16>) nounwind
32 %1 = tail call <2 x double> @llvm.mips.ffql.d(<4 x i32> %0)
37 declare <2 x double> @llvm.mips.ffql.d(<4 x i32>) nounwind
51 %1 = tail call <4 x float> @llvm.mips.ffqr.w(<8 x i16> %0)
56 declare <4 x float> @llvm.mips.ffqr.w(<8 x i16>) nounwind
70 %1 = tail call <2 x double> @llvm.mips.ffqr.d(<4 x i32> %0)
75 declare <2 x double> @llvm.mips.ffqr.d(<4 x i32>) nounwind
|
| i10.ll | 3 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
11 %1 = tail call i32 @llvm.mips.bnz.b(<16 x i8> %0)
20 declare i32 @llvm.mips.bnz.b(<16 x i8>) nounwind
32 %1 = tail call i32 @llvm.mips.bnz.h(<8 x i16> %0)
41 declare i32 @llvm.mips.bnz.h(<8 x i16>) nounwind
53 %1 = tail call i32 @llvm.mips.bnz.w(<4 x i32> %0)
62 declare i32 @llvm.mips.bnz.w(<4 x i32>) nounwind
74 %1 = tail call i32 @llvm.mips.bnz.d(<2 x i64> %0)
83 declare i32 @llvm.mips.bnz.d(<2 x i64>) nounwind
|
| i5-a.ll | 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
13 %1 = tail call <16 x i8> @llvm.mips.addvi.b(<16 x i8> %0, i32 14)
18 declare <16 x i8> @llvm.mips.addvi.b(<16 x i8>, i32) nounwind
32 %1 = tail call <8 x i16> @llvm.mips.addvi.h(<8 x i16> %0, i32 14)
37 declare <8 x i16> @llvm.mips.addvi.h(<8 x i16>, i32) nounwind
51 %1 = tail call <4 x i32> @llvm.mips.addvi.w(<4 x i32> %0, i32 14)
56 declare <4 x i32> @llvm.mips.addvi.w(<4 x i32>, i32) nounwind
70 %1 = tail call <2 x i64> @llvm.mips.addvi.d(<2 x i64> %0, i32 14)
75 declare <2 x i64> @llvm.mips.addvi.d(<2 x i64>, i32) nounwind
|
| i5-s.ll | 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
13 %1 = tail call <16 x i8> @llvm.mips.subvi.b(<16 x i8> %0, i32 14)
18 declare <16 x i8> @llvm.mips.subvi.b(<16 x i8>, i32) nounwind
32 %1 = tail call <8 x i16> @llvm.mips.subvi.h(<8 x i16> %0, i32 14)
37 declare <8 x i16> @llvm.mips.subvi.h(<8 x i16>, i32) nounwind
51 %1 = tail call <4 x i32> @llvm.mips.subvi.w(<4 x i32> %0, i32 14)
56 declare <4 x i32> @llvm.mips.subvi.w(<4 x i32>, i32) nounwind
70 %1 = tail call <2 x i64> @llvm.mips.subvi.d(<2 x i64> %0, i32 14)
75 declare <2 x i64> @llvm.mips.subvi.d(<2 x i64>, i32) nounwind
|
| special.ll | 3 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | \
7 ; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+msa < %s | \
14 %0 = tail call i32 @llvm.mips.lsa(i32 %a, i32 %b, i32 2)
18 declare i32 @llvm.mips.lsa(i32, i32, i32) nounwind
37 %0 = tail call i64 @llvm.mips.dlsa(i64 %a, i64 %b, i32 2)
41 declare i64 @llvm.mips.dlsa(i64, i64, i32) nounwind
|
| i5_ld_st.ll | 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
13 %1 = tail call <16 x i8> @llvm.mips.ld.b(i8* %0, i32 16)
18 declare <16 x i8> @llvm.mips.ld.b(i8*, i32) nounwind
31 %1 = tail call <8 x i16> @llvm.mips.ld.h(i8* %0, i32 16)
36 declare <8 x i16> @llvm.mips.ld.h(i8*, i32) nounwind
49 %1 = tail call <4 x i32> @llvm.mips.ld.w(i8* %0, i32 16)
54 declare <4 x i32> @llvm.mips.ld.w(i8*, i32) nounwind
67 %1 = tail call <2 x i64> @llvm.mips.ld.d(i8* %0, i32 16)
72 declare <2 x i64> @llvm.mips.ld.d(i8*, i32) nounwind
86 tail call void @llvm.mips.st.b(<16 x i8> %0, i8* %1, i32 16
[all...] |
| i5-m.ll | 4 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
13 %1 = tail call <16 x i8> @llvm.mips.maxi.s.b(<16 x i8> %0, i32 14)
18 declare <16 x i8> @llvm.mips.maxi.s.b(<16 x i8>, i32) nounwind
32 %1 = tail call <8 x i16> @llvm.mips.maxi.s.h(<8 x i16> %0, i32 14)
37 declare <8 x i16> @llvm.mips.maxi.s.h(<8 x i16>, i32) nounwind
51 %1 = tail call <4 x i32> @llvm.mips.maxi.s.w(<4 x i32> %0, i32 14)
56 declare <4 x i32> @llvm.mips.maxi.s.w(<4 x i32>, i32) nounwind
70 %1 = tail call <2 x i64> @llvm.mips.maxi.s.d(<2 x i64> %0, i32 14)
75 declare <2 x i64> @llvm.mips.maxi.s.d(<2 x i64>, i32) nounwind
89 %1 = tail call <16 x i8> @llvm.mips.maxi.u.b(<16 x i8> %0, i32 14
[all...] |
| /external/jemalloc/android/scripts/ |
| conf_mips.sh | 4 echo "In order for this script to function, please choose an mips target"
13 "-isystem ${ANDROID_BUILD_TOP}/bionic/libc/arch-mips/include"
17 "-isystem ${ANDROID_BUILD_TOP}/bionic/libc/kernel/uapi/asm-mips"
19 "-isystem ${ANDROID_BUILD_TOP}/bionic/libm/include/mips"
20 "-include ${ANDROID_BUILD_TOP}/build/core/combo/include/arch/linux-mips/AndroidConfig.h"
57 --host=mips-android-linux \
|
| /external/llvm/test/MC/Mips/ |
| nooddspreg-cmdarg.s | 1 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 -mattr=+fp64,+nooddspreg | \
4 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 -mattr=+fp64,+nooddspreg -filetype=obj -o - | \
8 # RUN: not llvm-mc %s -arch=mips -mcpu=mips64 -mattr=-n64,+n32,+nooddspreg 2> %t0
11 # RUN: not llvm-mc %s -arch=mips -mcpu=mips64 -mattr=+nooddspreg 2> %t0
16 # Checking if the Mips.abiflags were correctly emitted.
19 # CHECK-OBJ: Name: .MIPS.abiflags (12)
|
| nooddspreg.s | 1 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 -mattr=+fp64 | \
4 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 -mattr=+fp64 -filetype=obj -o - | \
8 # RUN: not llvm-mc %s -arch=mips -mcpu=mips64 -mattr=-n64,n32 2> %t1
11 # RUN: not llvm-mc %s -arch=mips -mcpu=mips64 2> %t2
16 # Checking if the Mips.abiflags were correctly emitted.
19 # CHECK-OBJ: Name: .MIPS.abiflags (12)
|
| /external/pixman/pixman/ |
| pixman-mips.c | 37 /* Simple detection of MIPS features at runtime for Linux.
39 * to user-space applications. According to MIPS (early 2010), no similar
40 * facility is universally available on the MIPS architectures, so it's up
78 if (!_pixman_disabled ("mips-dspr2"))
85 /* Only currently available MIPS core that supports DSPr2 is 74K. */
86 have_feature ("MIPS 74K"))
|
| /ndk/tests/build/issue17144-byteswap/ |
| build.sh | 42 if [ -z "$APP_ABI" -o "$APP_ABI" = "all" -o "$APP_ABI" != "${APP_ABI%%mips*}" ]; then
43 # checking mips
46 $NDK/ndk-build -B APP_ABI=mips APP_CFLAGS="-save-temps -mips32r2" NDK_DEBUG=1
47 fail_panic "can't compile for mips"
49 fail_panic "mips doesn't use wsbh instruction for __swap16()"
51 fail_panic "mips doesn't use wsbh/rotr instruciton for __swap32()"
|
| /external/clang/test/Preprocessor/ |
| stdint.c | 216 // RUN: %clang_cc1 -E -ffreestanding -triple=mips-none-none %s | FileCheck -check-prefix MIPS %s
218 // MIPS:typedef signed long long int int64_t;
219 // MIPS:typedef unsigned long long int uint64_t;
220 // MIPS:typedef int64_t int_least64_t;
221 // MIPS:typedef uint64_t uint_least64_t;
222 // MIPS:typedef int64_t int_fast64_t;
223 // MIPS:typedef uint64_t uint_fast64_t;
225 // MIPS:typedef signed int int32_t;
226 // MIPS:typedef unsigned int uint32_t
[all...] |
| /external/chromium_org/third_party/libvpx/source/libvpx/vpx_scale/ |
| vpx_scale.mk | 12 #mips(dspr2)
13 SCALE_SRCS-$(HAVE_DSPR2) += mips/dspr2/yv12extend_dspr2.c
|
| /external/chromium_org/v8/src/ |
| simulator.h | 17 #include "src/mips/simulator-mips.h"
|
| /external/clang/test/Frontend/ |
| mips-long-double.c | 2 // RUN: %clang_cc1 -triple mips-unknown-freebsd -std=c11 -verify %s
3 // RUN: %clang_cc1 -triple mips-unknown-linux -std=c11 -verify %s
|
| /external/kernel-headers/original/uapi/asm-mips/asm/ |
| ioctl.h | 6 * Copyright (C) 1995, 96, 99, 2001 Ralf Baechle <ralf@linux-mips.org>
8 * Written by Ralf Baechle <ralf@linux-mips.org>
|
