1 //===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // Subclass of MipsTargetLowering specialized for mips32/64. 11 // 12 //===----------------------------------------------------------------------===// 13 #include "MipsSEISelLowering.h" 14 #include "MipsMachineFunction.h" 15 #include "MipsRegisterInfo.h" 16 #include "MipsTargetMachine.h" 17 #include "llvm/CodeGen/MachineInstrBuilder.h" 18 #include "llvm/CodeGen/MachineRegisterInfo.h" 19 #include "llvm/IR/Intrinsics.h" 20 #include "llvm/Support/CommandLine.h" 21 #include "llvm/Support/Debug.h" 22 #include "llvm/Support/raw_ostream.h" 23 #include "llvm/Target/TargetInstrInfo.h" 24 25 using namespace llvm; 26 27 #define DEBUG_TYPE "mips-isel" 28 29 static cl::opt<bool> 30 EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden, 31 cl::desc("MIPS: Enable tail calls."), cl::init(false)); 32 33 static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false), 34 cl::desc("Expand double precision loads and " 35 "stores to their single precision " 36 "counterparts")); 37 38 MipsSETargetLowering::MipsSETargetLowering(const MipsTargetMachine &TM, 39 const MipsSubtarget &STI) 40 : MipsTargetLowering(TM, STI) { 41 // Set up the register classes 42 addRegisterClass(MVT::i32, &Mips::GPR32RegClass); 43 44 if (Subtarget.isGP64bit()) 45 addRegisterClass(MVT::i64, &Mips::GPR64RegClass); 46 47 if (Subtarget.hasDSP() || Subtarget.hasMSA()) { 48 // Expand all truncating stores and extending loads. 49 for (MVT VT0 : MVT::vector_valuetypes()) { 50 for (MVT VT1 : MVT::vector_valuetypes()) { 51 setTruncStoreAction(VT0, VT1, Expand); 52 setLoadExtAction(ISD::SEXTLOAD, VT0, VT1, Expand); 53 setLoadExtAction(ISD::ZEXTLOAD, VT0, VT1, Expand); 54 setLoadExtAction(ISD::EXTLOAD, VT0, VT1, Expand); 55 } 56 } 57 } 58 59 if (Subtarget.hasDSP()) { 60 MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8}; 61 62 for (unsigned i = 0; i < array_lengthof(VecTys); ++i) { 63 addRegisterClass(VecTys[i], &Mips::DSPRRegClass); 64 65 // Expand all builtin opcodes. 66 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc) 67 setOperationAction(Opc, VecTys[i], Expand); 68 69 setOperationAction(ISD::ADD, VecTys[i], Legal); 70 setOperationAction(ISD::SUB, VecTys[i], Legal); 71 setOperationAction(ISD::LOAD, VecTys[i], Legal); 72 setOperationAction(ISD::STORE, VecTys[i], Legal); 73 setOperationAction(ISD::BITCAST, VecTys[i], Legal); 74 } 75 76 setTargetDAGCombine(ISD::SHL); 77 setTargetDAGCombine(ISD::SRA); 78 setTargetDAGCombine(ISD::SRL); 79 setTargetDAGCombine(ISD::SETCC); 80 setTargetDAGCombine(ISD::VSELECT); 81 } 82 83 if (Subtarget.hasDSPR2()) 84 setOperationAction(ISD::MUL, MVT::v2i16, Legal); 85 86 if (Subtarget.hasMSA()) { 87 addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass); 88 addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass); 89 addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass); 90 addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass); 91 addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass); 92 addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass); 93 addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass); 94 95 setTargetDAGCombine(ISD::AND); 96 setTargetDAGCombine(ISD::OR); 97 setTargetDAGCombine(ISD::SRA); 98 setTargetDAGCombine(ISD::VSELECT); 99 setTargetDAGCombine(ISD::XOR); 100 } 101 102 if (!Subtarget.abiUsesSoftFloat()) { 103 addRegisterClass(MVT::f32, &Mips::FGR32RegClass); 104 105 // When dealing with single precision only, use libcalls 106 if (!Subtarget.isSingleFloat()) { 107 if (Subtarget.isFP64bit()) 108 addRegisterClass(MVT::f64, &Mips::FGR64RegClass); 109 else 110 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass); 111 } 112 } 113 114 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom); 115 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom); 116 setOperationAction(ISD::MULHS, MVT::i32, Custom); 117 setOperationAction(ISD::MULHU, MVT::i32, Custom); 118 119 if (Subtarget.hasCnMips()) 120 setOperationAction(ISD::MUL, MVT::i64, Legal); 121 else if (Subtarget.isGP64bit()) 122 setOperationAction(ISD::MUL, MVT::i64, Custom); 123 124 if (Subtarget.isGP64bit()) { 125 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Custom); 126 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Custom); 127 setOperationAction(ISD::MULHS, MVT::i64, Custom); 128 setOperationAction(ISD::MULHU, MVT::i64, Custom); 129 setOperationAction(ISD::SDIVREM, MVT::i64, Custom); 130 setOperationAction(ISD::UDIVREM, MVT::i64, Custom); 131 } 132 133 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom); 134 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom); 135 136 setOperationAction(ISD::SDIVREM, MVT::i32, Custom); 137 setOperationAction(ISD::UDIVREM, MVT::i32, Custom); 138 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); 139 setOperationAction(ISD::LOAD, MVT::i32, Custom); 140 setOperationAction(ISD::STORE, MVT::i32, Custom); 141 142 setTargetDAGCombine(ISD::ADDE); 143 setTargetDAGCombine(ISD::SUBE); 144 setTargetDAGCombine(ISD::MUL); 145 146 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 147 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom); 148 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom); 149 150 if (NoDPLoadStore) { 151 setOperationAction(ISD::LOAD, MVT::f64, Custom); 152 setOperationAction(ISD::STORE, MVT::f64, Custom); 153 } 154 155 if (Subtarget.hasMips32r6()) { 156 // MIPS32r6 replaces the accumulator-based multiplies with a three register 157 // instruction 158 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 159 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 160 setOperationAction(ISD::MUL, MVT::i32, Legal); 161 setOperationAction(ISD::MULHS, MVT::i32, Legal); 162 setOperationAction(ISD::MULHU, MVT::i32, Legal); 163 164 // MIPS32r6 replaces the accumulator-based division/remainder with separate 165 // three register division and remainder instructions. 166 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 167 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 168 setOperationAction(ISD::SDIV, MVT::i32, Legal); 169 setOperationAction(ISD::UDIV, MVT::i32, Legal); 170 setOperationAction(ISD::SREM, MVT::i32, Legal); 171 setOperationAction(ISD::UREM, MVT::i32, Legal); 172 173 // MIPS32r6 replaces conditional moves with an equivalent that removes the 174 // need for three GPR read ports. 175 setOperationAction(ISD::SETCC, MVT::i32, Legal); 176 setOperationAction(ISD::SELECT, MVT::i32, Legal); 177 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); 178 179 setOperationAction(ISD::SETCC, MVT::f32, Legal); 180 setOperationAction(ISD::SELECT, MVT::f32, Legal); 181 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); 182 183 assert(Subtarget.isFP64bit() && "FR=1 is required for MIPS32r6"); 184 setOperationAction(ISD::SETCC, MVT::f64, Legal); 185 setOperationAction(ISD::SELECT, MVT::f64, Legal); 186 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); 187 188 setOperationAction(ISD::BRCOND, MVT::Other, Legal); 189 190 // Floating point > and >= are supported via < and <= 191 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand); 192 setCondCodeAction(ISD::SETOGT, MVT::f32, Expand); 193 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand); 194 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand); 195 196 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand); 197 setCondCodeAction(ISD::SETOGT, MVT::f64, Expand); 198 setCondCodeAction(ISD::SETUGE, MVT::f64, Expand); 199 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand); 200 } 201 202 if (Subtarget.hasMips64r6()) { 203 // MIPS64r6 replaces the accumulator-based multiplies with a three register 204 // instruction 205 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); 206 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); 207 setOperationAction(ISD::MUL, MVT::i64, Legal); 208 setOperationAction(ISD::MULHS, MVT::i64, Legal); 209 setOperationAction(ISD::MULHU, MVT::i64, Legal); 210 211 // MIPS32r6 replaces the accumulator-based division/remainder with separate 212 // three register division and remainder instructions. 213 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); 214 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); 215 setOperationAction(ISD::SDIV, MVT::i64, Legal); 216 setOperationAction(ISD::UDIV, MVT::i64, Legal); 217 setOperationAction(ISD::SREM, MVT::i64, Legal); 218 setOperationAction(ISD::UREM, MVT::i64, Legal); 219 220 // MIPS64r6 replaces conditional moves with an equivalent that removes the 221 // need for three GPR read ports. 222 setOperationAction(ISD::SETCC, MVT::i64, Legal); 223 setOperationAction(ISD::SELECT, MVT::i64, Legal); 224 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); 225 } 226 227 computeRegisterProperties(Subtarget.getRegisterInfo()); 228 } 229 230 const MipsTargetLowering * 231 llvm::createMipsSETargetLowering(const MipsTargetMachine &TM, 232 const MipsSubtarget &STI) { 233 return new MipsSETargetLowering(TM, STI); 234 } 235 236 const TargetRegisterClass * 237 MipsSETargetLowering::getRepRegClassFor(MVT VT) const { 238 if (VT == MVT::Untyped) 239 return Subtarget.hasDSP() ? &Mips::ACC64DSPRegClass : &Mips::ACC64RegClass; 240 241 return TargetLowering::getRepRegClassFor(VT); 242 } 243 244 // Enable MSA support for the given integer type and Register class. 245 void MipsSETargetLowering:: 246 addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) { 247 addRegisterClass(Ty, RC); 248 249 // Expand all builtin opcodes. 250 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc) 251 setOperationAction(Opc, Ty, Expand); 252 253 setOperationAction(ISD::BITCAST, Ty, Legal); 254 setOperationAction(ISD::LOAD, Ty, Legal); 255 setOperationAction(ISD::STORE, Ty, Legal); 256 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Custom); 257 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal); 258 setOperationAction(ISD::BUILD_VECTOR, Ty, Custom); 259 260 setOperationAction(ISD::ADD, Ty, Legal); 261 setOperationAction(ISD::AND, Ty, Legal); 262 setOperationAction(ISD::CTLZ, Ty, Legal); 263 setOperationAction(ISD::CTPOP, Ty, Legal); 264 setOperationAction(ISD::MUL, Ty, Legal); 265 setOperationAction(ISD::OR, Ty, Legal); 266 setOperationAction(ISD::SDIV, Ty, Legal); 267 setOperationAction(ISD::SREM, Ty, Legal); 268 setOperationAction(ISD::SHL, Ty, Legal); 269 setOperationAction(ISD::SRA, Ty, Legal); 270 setOperationAction(ISD::SRL, Ty, Legal); 271 setOperationAction(ISD::SUB, Ty, Legal); 272 setOperationAction(ISD::UDIV, Ty, Legal); 273 setOperationAction(ISD::UREM, Ty, Legal); 274 setOperationAction(ISD::VECTOR_SHUFFLE, Ty, Custom); 275 setOperationAction(ISD::VSELECT, Ty, Legal); 276 setOperationAction(ISD::XOR, Ty, Legal); 277 278 if (Ty == MVT::v4i32 || Ty == MVT::v2i64) { 279 setOperationAction(ISD::FP_TO_SINT, Ty, Legal); 280 setOperationAction(ISD::FP_TO_UINT, Ty, Legal); 281 setOperationAction(ISD::SINT_TO_FP, Ty, Legal); 282 setOperationAction(ISD::UINT_TO_FP, Ty, Legal); 283 } 284 285 setOperationAction(ISD::SETCC, Ty, Legal); 286 setCondCodeAction(ISD::SETNE, Ty, Expand); 287 setCondCodeAction(ISD::SETGE, Ty, Expand); 288 setCondCodeAction(ISD::SETGT, Ty, Expand); 289 setCondCodeAction(ISD::SETUGE, Ty, Expand); 290 setCondCodeAction(ISD::SETUGT, Ty, Expand); 291 } 292 293 // Enable MSA support for the given floating-point type and Register class. 294 void MipsSETargetLowering:: 295 addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) { 296 addRegisterClass(Ty, RC); 297 298 // Expand all builtin opcodes. 299 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc) 300 setOperationAction(Opc, Ty, Expand); 301 302 setOperationAction(ISD::LOAD, Ty, Legal); 303 setOperationAction(ISD::STORE, Ty, Legal); 304 setOperationAction(ISD::BITCAST, Ty, Legal); 305 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Legal); 306 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal); 307 setOperationAction(ISD::BUILD_VECTOR, Ty, Custom); 308 309 if (Ty != MVT::v8f16) { 310 setOperationAction(ISD::FABS, Ty, Legal); 311 setOperationAction(ISD::FADD, Ty, Legal); 312 setOperationAction(ISD::FDIV, Ty, Legal); 313 setOperationAction(ISD::FEXP2, Ty, Legal); 314 setOperationAction(ISD::FLOG2, Ty, Legal); 315 setOperationAction(ISD::FMA, Ty, Legal); 316 setOperationAction(ISD::FMUL, Ty, Legal); 317 setOperationAction(ISD::FRINT, Ty, Legal); 318 setOperationAction(ISD::FSQRT, Ty, Legal); 319 setOperationAction(ISD::FSUB, Ty, Legal); 320 setOperationAction(ISD::VSELECT, Ty, Legal); 321 322 setOperationAction(ISD::SETCC, Ty, Legal); 323 setCondCodeAction(ISD::SETOGE, Ty, Expand); 324 setCondCodeAction(ISD::SETOGT, Ty, Expand); 325 setCondCodeAction(ISD::SETUGE, Ty, Expand); 326 setCondCodeAction(ISD::SETUGT, Ty, Expand); 327 setCondCodeAction(ISD::SETGE, Ty, Expand); 328 setCondCodeAction(ISD::SETGT, Ty, Expand); 329 } 330 } 331 332 bool 333 MipsSETargetLowering::allowsMisalignedMemoryAccesses(EVT VT, 334 unsigned, 335 unsigned, 336 bool *Fast) const { 337 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy; 338 339 if (Subtarget.systemSupportsUnalignedAccess()) { 340 // MIPS32r6/MIPS64r6 is required to support unaligned access. It's 341 // implementation defined whether this is handled by hardware, software, or 342 // a hybrid of the two but it's expected that most implementations will 343 // handle the majority of cases in hardware. 344 if (Fast) 345 *Fast = true; 346 return true; 347 } 348 349 switch (SVT) { 350 case MVT::i64: 351 case MVT::i32: 352 if (Fast) 353 *Fast = true; 354 return true; 355 default: 356 return false; 357 } 358 } 359 360 SDValue MipsSETargetLowering::LowerOperation(SDValue Op, 361 SelectionDAG &DAG) const { 362 switch(Op.getOpcode()) { 363 case ISD::LOAD: return lowerLOAD(Op, DAG); 364 case ISD::STORE: return lowerSTORE(Op, DAG); 365 case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG); 366 case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG); 367 case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG); 368 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG); 369 case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG); 370 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG); 371 case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true, 372 DAG); 373 case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG); 374 case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG); 375 case ISD::INTRINSIC_VOID: return lowerINTRINSIC_VOID(Op, DAG); 376 case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG); 377 case ISD::BUILD_VECTOR: return lowerBUILD_VECTOR(Op, DAG); 378 case ISD::VECTOR_SHUFFLE: return lowerVECTOR_SHUFFLE(Op, DAG); 379 } 380 381 return MipsTargetLowering::LowerOperation(Op, DAG); 382 } 383 384 // selectMADD - 385 // Transforms a subgraph in CurDAG if the following pattern is found: 386 // (addc multLo, Lo0), (adde multHi, Hi0), 387 // where, 388 // multHi/Lo: product of multiplication 389 // Lo0: initial value of Lo register 390 // Hi0: initial value of Hi register 391 // Return true if pattern matching was successful. 392 static bool selectMADD(SDNode *ADDENode, SelectionDAG *CurDAG) { 393 // ADDENode's second operand must be a flag output of an ADDC node in order 394 // for the matching to be successful. 395 SDNode *ADDCNode = ADDENode->getOperand(2).getNode(); 396 397 if (ADDCNode->getOpcode() != ISD::ADDC) 398 return false; 399 400 SDValue MultHi = ADDENode->getOperand(0); 401 SDValue MultLo = ADDCNode->getOperand(0); 402 SDNode *MultNode = MultHi.getNode(); 403 unsigned MultOpc = MultHi.getOpcode(); 404 405 // MultHi and MultLo must be generated by the same node, 406 if (MultLo.getNode() != MultNode) 407 return false; 408 409 // and it must be a multiplication. 410 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 411 return false; 412 413 // MultLo amd MultHi must be the first and second output of MultNode 414 // respectively. 415 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 416 return false; 417 418 // Transform this to a MADD only if ADDENode and ADDCNode are the only users 419 // of the values of MultNode, in which case MultNode will be removed in later 420 // phases. 421 // If there exist users other than ADDENode or ADDCNode, this function returns 422 // here, which will result in MultNode being mapped to a single MULT 423 // instruction node rather than a pair of MULT and MADD instructions being 424 // produced. 425 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 426 return false; 427 428 SDLoc DL(ADDENode); 429 430 // Initialize accumulator. 431 SDValue ACCIn = CurDAG->getNode(MipsISD::MTLOHI, DL, MVT::Untyped, 432 ADDCNode->getOperand(1), 433 ADDENode->getOperand(1)); 434 435 // create MipsMAdd(u) node 436 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd; 437 438 SDValue MAdd = CurDAG->getNode(MultOpc, DL, MVT::Untyped, 439 MultNode->getOperand(0),// Factor 0 440 MultNode->getOperand(1),// Factor 1 441 ACCIn); 442 443 // replace uses of adde and addc here 444 if (!SDValue(ADDCNode, 0).use_empty()) { 445 SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MAdd); 446 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), LoOut); 447 } 448 if (!SDValue(ADDENode, 0).use_empty()) { 449 SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MAdd); 450 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), HiOut); 451 } 452 453 return true; 454 } 455 456 // selectMSUB - 457 // Transforms a subgraph in CurDAG if the following pattern is found: 458 // (addc Lo0, multLo), (sube Hi0, multHi), 459 // where, 460 // multHi/Lo: product of multiplication 461 // Lo0: initial value of Lo register 462 // Hi0: initial value of Hi register 463 // Return true if pattern matching was successful. 464 static bool selectMSUB(SDNode *SUBENode, SelectionDAG *CurDAG) { 465 // SUBENode's second operand must be a flag output of an SUBC node in order 466 // for the matching to be successful. 467 SDNode *SUBCNode = SUBENode->getOperand(2).getNode(); 468 469 if (SUBCNode->getOpcode() != ISD::SUBC) 470 return false; 471 472 SDValue MultHi = SUBENode->getOperand(1); 473 SDValue MultLo = SUBCNode->getOperand(1); 474 SDNode *MultNode = MultHi.getNode(); 475 unsigned MultOpc = MultHi.getOpcode(); 476 477 // MultHi and MultLo must be generated by the same node, 478 if (MultLo.getNode() != MultNode) 479 return false; 480 481 // and it must be a multiplication. 482 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 483 return false; 484 485 // MultLo amd MultHi must be the first and second output of MultNode 486 // respectively. 487 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 488 return false; 489 490 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users 491 // of the values of MultNode, in which case MultNode will be removed in later 492 // phases. 493 // If there exist users other than SUBENode or SUBCNode, this function returns 494 // here, which will result in MultNode being mapped to a single MULT 495 // instruction node rather than a pair of MULT and MSUB instructions being 496 // produced. 497 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 498 return false; 499 500 SDLoc DL(SUBENode); 501 502 // Initialize accumulator. 503 SDValue ACCIn = CurDAG->getNode(MipsISD::MTLOHI, DL, MVT::Untyped, 504 SUBCNode->getOperand(0), 505 SUBENode->getOperand(0)); 506 507 // create MipsSub(u) node 508 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub; 509 510 SDValue MSub = CurDAG->getNode(MultOpc, DL, MVT::Glue, 511 MultNode->getOperand(0),// Factor 0 512 MultNode->getOperand(1),// Factor 1 513 ACCIn); 514 515 // replace uses of sube and subc here 516 if (!SDValue(SUBCNode, 0).use_empty()) { 517 SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MSub); 518 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), LoOut); 519 } 520 if (!SDValue(SUBENode, 0).use_empty()) { 521 SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MSub); 522 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), HiOut); 523 } 524 525 return true; 526 } 527 528 static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG, 529 TargetLowering::DAGCombinerInfo &DCI, 530 const MipsSubtarget &Subtarget) { 531 if (DCI.isBeforeLegalize()) 532 return SDValue(); 533 534 if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() && 535 N->getValueType(0) == MVT::i32 && selectMADD(N, &DAG)) 536 return SDValue(N, 0); 537 538 return SDValue(); 539 } 540 541 // Fold zero extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT 542 // 543 // Performs the following transformations: 544 // - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to zero extension if its 545 // sign/zero-extension is completely overwritten by the new one performed by 546 // the ISD::AND. 547 // - Removes redundant zero extensions performed by an ISD::AND. 548 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, 549 TargetLowering::DAGCombinerInfo &DCI, 550 const MipsSubtarget &Subtarget) { 551 if (!Subtarget.hasMSA()) 552 return SDValue(); 553 554 SDValue Op0 = N->getOperand(0); 555 SDValue Op1 = N->getOperand(1); 556 unsigned Op0Opcode = Op0->getOpcode(); 557 558 // (and (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d) 559 // where $d + 1 == 2^n and n == 32 560 // or $d + 1 == 2^n and n <= 32 and ZExt 561 // -> (MipsVExtractZExt $a, $b, $c) 562 if (Op0Opcode == MipsISD::VEXTRACT_SEXT_ELT || 563 Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT) { 564 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(Op1); 565 566 if (!Mask) 567 return SDValue(); 568 569 int32_t Log2IfPositive = (Mask->getAPIntValue() + 1).exactLogBase2(); 570 571 if (Log2IfPositive <= 0) 572 return SDValue(); // Mask+1 is not a power of 2 573 574 SDValue Op0Op2 = Op0->getOperand(2); 575 EVT ExtendTy = cast<VTSDNode>(Op0Op2)->getVT(); 576 unsigned ExtendTySize = ExtendTy.getSizeInBits(); 577 unsigned Log2 = Log2IfPositive; 578 579 if ((Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT && Log2 >= ExtendTySize) || 580 Log2 == ExtendTySize) { 581 SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 }; 582 return DAG.getNode(MipsISD::VEXTRACT_ZEXT_ELT, SDLoc(Op0), 583 Op0->getVTList(), 584 makeArrayRef(Ops, Op0->getNumOperands())); 585 } 586 } 587 588 return SDValue(); 589 } 590 591 // Determine if the specified node is a constant vector splat. 592 // 593 // Returns true and sets Imm if: 594 // * N is a ISD::BUILD_VECTOR representing a constant splat 595 // 596 // This function is quite similar to MipsSEDAGToDAGISel::selectVSplat. The 597 // differences are that it assumes the MSA has already been checked and the 598 // arbitrary requirement for a maximum of 32-bit integers isn't applied (and 599 // must not be in order for binsri.d to be selectable). 600 static bool isVSplat(SDValue N, APInt &Imm, bool IsLittleEndian) { 601 BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(N.getNode()); 602 603 if (!Node) 604 return false; 605 606 APInt SplatValue, SplatUndef; 607 unsigned SplatBitSize; 608 bool HasAnyUndefs; 609 610 if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs, 611 8, !IsLittleEndian)) 612 return false; 613 614 Imm = SplatValue; 615 616 return true; 617 } 618 619 // Test whether the given node is an all-ones build_vector. 620 static bool isVectorAllOnes(SDValue N) { 621 // Look through bitcasts. Endianness doesn't matter because we are looking 622 // for an all-ones value. 623 if (N->getOpcode() == ISD::BITCAST) 624 N = N->getOperand(0); 625 626 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N); 627 628 if (!BVN) 629 return false; 630 631 APInt SplatValue, SplatUndef; 632 unsigned SplatBitSize; 633 bool HasAnyUndefs; 634 635 // Endianness doesn't matter in this context because we are looking for 636 // an all-ones value. 637 if (BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs)) 638 return SplatValue.isAllOnesValue(); 639 640 return false; 641 } 642 643 // Test whether N is the bitwise inverse of OfNode. 644 static bool isBitwiseInverse(SDValue N, SDValue OfNode) { 645 if (N->getOpcode() != ISD::XOR) 646 return false; 647 648 if (isVectorAllOnes(N->getOperand(0))) 649 return N->getOperand(1) == OfNode; 650 651 if (isVectorAllOnes(N->getOperand(1))) 652 return N->getOperand(0) == OfNode; 653 654 return false; 655 } 656 657 // Perform combines where ISD::OR is the root node. 658 // 659 // Performs the following transformations: 660 // - (or (and $a, $mask), (and $b, $inv_mask)) => (vselect $mask, $a, $b) 661 // where $inv_mask is the bitwise inverse of $mask and the 'or' has a 128-bit 662 // vector type. 663 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, 664 TargetLowering::DAGCombinerInfo &DCI, 665 const MipsSubtarget &Subtarget) { 666 if (!Subtarget.hasMSA()) 667 return SDValue(); 668 669 EVT Ty = N->getValueType(0); 670 671 if (!Ty.is128BitVector()) 672 return SDValue(); 673 674 SDValue Op0 = N->getOperand(0); 675 SDValue Op1 = N->getOperand(1); 676 677 if (Op0->getOpcode() == ISD::AND && Op1->getOpcode() == ISD::AND) { 678 SDValue Op0Op0 = Op0->getOperand(0); 679 SDValue Op0Op1 = Op0->getOperand(1); 680 SDValue Op1Op0 = Op1->getOperand(0); 681 SDValue Op1Op1 = Op1->getOperand(1); 682 bool IsLittleEndian = !Subtarget.isLittle(); 683 684 SDValue IfSet, IfClr, Cond; 685 bool IsConstantMask = false; 686 APInt Mask, InvMask; 687 688 // If Op0Op0 is an appropriate mask, try to find it's inverse in either 689 // Op1Op0, or Op1Op1. Keep track of the Cond, IfSet, and IfClr nodes, while 690 // looking. 691 // IfClr will be set if we find a valid match. 692 if (isVSplat(Op0Op0, Mask, IsLittleEndian)) { 693 Cond = Op0Op0; 694 IfSet = Op0Op1; 695 696 if (isVSplat(Op1Op0, InvMask, IsLittleEndian) && 697 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask) 698 IfClr = Op1Op1; 699 else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) && 700 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask) 701 IfClr = Op1Op0; 702 703 IsConstantMask = true; 704 } 705 706 // If IfClr is not yet set, and Op0Op1 is an appropriate mask, try the same 707 // thing again using this mask. 708 // IfClr will be set if we find a valid match. 709 if (!IfClr.getNode() && isVSplat(Op0Op1, Mask, IsLittleEndian)) { 710 Cond = Op0Op1; 711 IfSet = Op0Op0; 712 713 if (isVSplat(Op1Op0, InvMask, IsLittleEndian) && 714 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask) 715 IfClr = Op1Op1; 716 else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) && 717 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask) 718 IfClr = Op1Op0; 719 720 IsConstantMask = true; 721 } 722 723 // If IfClr is not yet set, try looking for a non-constant match. 724 // IfClr will be set if we find a valid match amongst the eight 725 // possibilities. 726 if (!IfClr.getNode()) { 727 if (isBitwiseInverse(Op0Op0, Op1Op0)) { 728 Cond = Op1Op0; 729 IfSet = Op1Op1; 730 IfClr = Op0Op1; 731 } else if (isBitwiseInverse(Op0Op1, Op1Op0)) { 732 Cond = Op1Op0; 733 IfSet = Op1Op1; 734 IfClr = Op0Op0; 735 } else if (isBitwiseInverse(Op0Op0, Op1Op1)) { 736 Cond = Op1Op1; 737 IfSet = Op1Op0; 738 IfClr = Op0Op1; 739 } else if (isBitwiseInverse(Op0Op1, Op1Op1)) { 740 Cond = Op1Op1; 741 IfSet = Op1Op0; 742 IfClr = Op0Op0; 743 } else if (isBitwiseInverse(Op1Op0, Op0Op0)) { 744 Cond = Op0Op0; 745 IfSet = Op0Op1; 746 IfClr = Op1Op1; 747 } else if (isBitwiseInverse(Op1Op1, Op0Op0)) { 748 Cond = Op0Op0; 749 IfSet = Op0Op1; 750 IfClr = Op1Op0; 751 } else if (isBitwiseInverse(Op1Op0, Op0Op1)) { 752 Cond = Op0Op1; 753 IfSet = Op0Op0; 754 IfClr = Op1Op1; 755 } else if (isBitwiseInverse(Op1Op1, Op0Op1)) { 756 Cond = Op0Op1; 757 IfSet = Op0Op0; 758 IfClr = Op1Op0; 759 } 760 } 761 762 // At this point, IfClr will be set if we have a valid match. 763 if (!IfClr.getNode()) 764 return SDValue(); 765 766 assert(Cond.getNode() && IfSet.getNode()); 767 768 // Fold degenerate cases. 769 if (IsConstantMask) { 770 if (Mask.isAllOnesValue()) 771 return IfSet; 772 else if (Mask == 0) 773 return IfClr; 774 } 775 776 // Transform the DAG into an equivalent VSELECT. 777 return DAG.getNode(ISD::VSELECT, SDLoc(N), Ty, Cond, IfSet, IfClr); 778 } 779 780 return SDValue(); 781 } 782 783 static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG, 784 TargetLowering::DAGCombinerInfo &DCI, 785 const MipsSubtarget &Subtarget) { 786 if (DCI.isBeforeLegalize()) 787 return SDValue(); 788 789 if (Subtarget.hasMips32() && N->getValueType(0) == MVT::i32 && 790 selectMSUB(N, &DAG)) 791 return SDValue(N, 0); 792 793 return SDValue(); 794 } 795 796 static SDValue genConstMult(SDValue X, uint64_t C, SDLoc DL, EVT VT, 797 EVT ShiftTy, SelectionDAG &DAG) { 798 // Clear the upper (64 - VT.sizeInBits) bits. 799 C &= ((uint64_t)-1) >> (64 - VT.getSizeInBits()); 800 801 // Return 0. 802 if (C == 0) 803 return DAG.getConstant(0, VT); 804 805 // Return x. 806 if (C == 1) 807 return X; 808 809 // If c is power of 2, return (shl x, log2(c)). 810 if (isPowerOf2_64(C)) 811 return DAG.getNode(ISD::SHL, DL, VT, X, 812 DAG.getConstant(Log2_64(C), ShiftTy)); 813 814 unsigned Log2Ceil = Log2_64_Ceil(C); 815 uint64_t Floor = 1LL << Log2_64(C); 816 uint64_t Ceil = Log2Ceil == 64 ? 0LL : 1LL << Log2Ceil; 817 818 // If |c - floor_c| <= |c - ceil_c|, 819 // where floor_c = pow(2, floor(log2(c))) and ceil_c = pow(2, ceil(log2(c))), 820 // return (add constMult(x, floor_c), constMult(x, c - floor_c)). 821 if (C - Floor <= Ceil - C) { 822 SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG); 823 SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG); 824 return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1); 825 } 826 827 // If |c - floor_c| > |c - ceil_c|, 828 // return (sub constMult(x, ceil_c), constMult(x, ceil_c - c)). 829 SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG); 830 SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG); 831 return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1); 832 } 833 834 static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG, 835 const TargetLowering::DAGCombinerInfo &DCI, 836 const MipsSETargetLowering *TL) { 837 EVT VT = N->getValueType(0); 838 839 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) 840 if (!VT.isVector()) 841 return genConstMult(N->getOperand(0), C->getZExtValue(), SDLoc(N), 842 VT, TL->getScalarShiftAmountTy(VT), DAG); 843 844 return SDValue(N, 0); 845 } 846 847 static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty, 848 SelectionDAG &DAG, 849 const MipsSubtarget &Subtarget) { 850 // See if this is a vector splat immediate node. 851 APInt SplatValue, SplatUndef; 852 unsigned SplatBitSize; 853 bool HasAnyUndefs; 854 unsigned EltSize = Ty.getVectorElementType().getSizeInBits(); 855 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1)); 856 857 if (!Subtarget.hasDSP()) 858 return SDValue(); 859 860 if (!BV || 861 !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs, 862 EltSize, !Subtarget.isLittle()) || 863 (SplatBitSize != EltSize) || 864 (SplatValue.getZExtValue() >= EltSize)) 865 return SDValue(); 866 867 return DAG.getNode(Opc, SDLoc(N), Ty, N->getOperand(0), 868 DAG.getConstant(SplatValue.getZExtValue(), MVT::i32)); 869 } 870 871 static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG, 872 TargetLowering::DAGCombinerInfo &DCI, 873 const MipsSubtarget &Subtarget) { 874 EVT Ty = N->getValueType(0); 875 876 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8)) 877 return SDValue(); 878 879 return performDSPShiftCombine(MipsISD::SHLL_DSP, N, Ty, DAG, Subtarget); 880 } 881 882 // Fold sign-extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT for MSA and fold 883 // constant splats into MipsISD::SHRA_DSP for DSPr2. 884 // 885 // Performs the following transformations: 886 // - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to sign extension if its 887 // sign/zero-extension is completely overwritten by the new one performed by 888 // the ISD::SRA and ISD::SHL nodes. 889 // - Removes redundant sign extensions performed by an ISD::SRA and ISD::SHL 890 // sequence. 891 // 892 // See performDSPShiftCombine for more information about the transformation 893 // used for DSPr2. 894 static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG, 895 TargetLowering::DAGCombinerInfo &DCI, 896 const MipsSubtarget &Subtarget) { 897 EVT Ty = N->getValueType(0); 898 899 if (Subtarget.hasMSA()) { 900 SDValue Op0 = N->getOperand(0); 901 SDValue Op1 = N->getOperand(1); 902 903 // (sra (shl (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d), imm:$d) 904 // where $d + sizeof($c) == 32 905 // or $d + sizeof($c) <= 32 and SExt 906 // -> (MipsVExtractSExt $a, $b, $c) 907 if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) { 908 SDValue Op0Op0 = Op0->getOperand(0); 909 ConstantSDNode *ShAmount = dyn_cast<ConstantSDNode>(Op1); 910 911 if (!ShAmount) 912 return SDValue(); 913 914 if (Op0Op0->getOpcode() != MipsISD::VEXTRACT_SEXT_ELT && 915 Op0Op0->getOpcode() != MipsISD::VEXTRACT_ZEXT_ELT) 916 return SDValue(); 917 918 EVT ExtendTy = cast<VTSDNode>(Op0Op0->getOperand(2))->getVT(); 919 unsigned TotalBits = ShAmount->getZExtValue() + ExtendTy.getSizeInBits(); 920 921 if (TotalBits == 32 || 922 (Op0Op0->getOpcode() == MipsISD::VEXTRACT_SEXT_ELT && 923 TotalBits <= 32)) { 924 SDValue Ops[] = { Op0Op0->getOperand(0), Op0Op0->getOperand(1), 925 Op0Op0->getOperand(2) }; 926 return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, SDLoc(Op0Op0), 927 Op0Op0->getVTList(), 928 makeArrayRef(Ops, Op0Op0->getNumOperands())); 929 } 930 } 931 } 932 933 if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget.hasDSPR2())) 934 return SDValue(); 935 936 return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget); 937 } 938 939 940 static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG, 941 TargetLowering::DAGCombinerInfo &DCI, 942 const MipsSubtarget &Subtarget) { 943 EVT Ty = N->getValueType(0); 944 945 if (((Ty != MVT::v2i16) || !Subtarget.hasDSPR2()) && (Ty != MVT::v4i8)) 946 return SDValue(); 947 948 return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget); 949 } 950 951 static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) { 952 bool IsV216 = (Ty == MVT::v2i16); 953 954 switch (CC) { 955 case ISD::SETEQ: 956 case ISD::SETNE: return true; 957 case ISD::SETLT: 958 case ISD::SETLE: 959 case ISD::SETGT: 960 case ISD::SETGE: return IsV216; 961 case ISD::SETULT: 962 case ISD::SETULE: 963 case ISD::SETUGT: 964 case ISD::SETUGE: return !IsV216; 965 default: return false; 966 } 967 } 968 969 static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG) { 970 EVT Ty = N->getValueType(0); 971 972 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8)) 973 return SDValue(); 974 975 if (!isLegalDSPCondCode(Ty, cast<CondCodeSDNode>(N->getOperand(2))->get())) 976 return SDValue(); 977 978 return DAG.getNode(MipsISD::SETCC_DSP, SDLoc(N), Ty, N->getOperand(0), 979 N->getOperand(1), N->getOperand(2)); 980 } 981 982 static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG) { 983 EVT Ty = N->getValueType(0); 984 985 if (Ty.is128BitVector() && Ty.isInteger()) { 986 // Try the following combines: 987 // (vselect (setcc $a, $b, SETLT), $b, $a)) -> (vsmax $a, $b) 988 // (vselect (setcc $a, $b, SETLE), $b, $a)) -> (vsmax $a, $b) 989 // (vselect (setcc $a, $b, SETLT), $a, $b)) -> (vsmin $a, $b) 990 // (vselect (setcc $a, $b, SETLE), $a, $b)) -> (vsmin $a, $b) 991 // (vselect (setcc $a, $b, SETULT), $b, $a)) -> (vumax $a, $b) 992 // (vselect (setcc $a, $b, SETULE), $b, $a)) -> (vumax $a, $b) 993 // (vselect (setcc $a, $b, SETULT), $a, $b)) -> (vumin $a, $b) 994 // (vselect (setcc $a, $b, SETULE), $a, $b)) -> (vumin $a, $b) 995 // SETGT/SETGE/SETUGT/SETUGE variants of these will show up initially but 996 // will be expanded to equivalent SETLT/SETLE/SETULT/SETULE versions by the 997 // legalizer. 998 SDValue Op0 = N->getOperand(0); 999 1000 if (Op0->getOpcode() != ISD::SETCC) 1001 return SDValue(); 1002 1003 ISD::CondCode CondCode = cast<CondCodeSDNode>(Op0->getOperand(2))->get(); 1004 bool Signed; 1005 1006 if (CondCode == ISD::SETLT || CondCode == ISD::SETLE) 1007 Signed = true; 1008 else if (CondCode == ISD::SETULT || CondCode == ISD::SETULE) 1009 Signed = false; 1010 else 1011 return SDValue(); 1012 1013 SDValue Op1 = N->getOperand(1); 1014 SDValue Op2 = N->getOperand(2); 1015 SDValue Op0Op0 = Op0->getOperand(0); 1016 SDValue Op0Op1 = Op0->getOperand(1); 1017 1018 if (Op1 == Op0Op0 && Op2 == Op0Op1) 1019 return DAG.getNode(Signed ? MipsISD::VSMIN : MipsISD::VUMIN, SDLoc(N), 1020 Ty, Op1, Op2); 1021 else if (Op1 == Op0Op1 && Op2 == Op0Op0) 1022 return DAG.getNode(Signed ? MipsISD::VSMAX : MipsISD::VUMAX, SDLoc(N), 1023 Ty, Op1, Op2); 1024 } else if ((Ty == MVT::v2i16) || (Ty == MVT::v4i8)) { 1025 SDValue SetCC = N->getOperand(0); 1026 1027 if (SetCC.getOpcode() != MipsISD::SETCC_DSP) 1028 return SDValue(); 1029 1030 return DAG.getNode(MipsISD::SELECT_CC_DSP, SDLoc(N), Ty, 1031 SetCC.getOperand(0), SetCC.getOperand(1), 1032 N->getOperand(1), N->getOperand(2), SetCC.getOperand(2)); 1033 } 1034 1035 return SDValue(); 1036 } 1037 1038 static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG, 1039 const MipsSubtarget &Subtarget) { 1040 EVT Ty = N->getValueType(0); 1041 1042 if (Subtarget.hasMSA() && Ty.is128BitVector() && Ty.isInteger()) { 1043 // Try the following combines: 1044 // (xor (or $a, $b), (build_vector allones)) 1045 // (xor (or $a, $b), (bitcast (build_vector allones))) 1046 SDValue Op0 = N->getOperand(0); 1047 SDValue Op1 = N->getOperand(1); 1048 SDValue NotOp; 1049 1050 if (ISD::isBuildVectorAllOnes(Op0.getNode())) 1051 NotOp = Op1; 1052 else if (ISD::isBuildVectorAllOnes(Op1.getNode())) 1053 NotOp = Op0; 1054 else 1055 return SDValue(); 1056 1057 if (NotOp->getOpcode() == ISD::OR) 1058 return DAG.getNode(MipsISD::VNOR, SDLoc(N), Ty, NotOp->getOperand(0), 1059 NotOp->getOperand(1)); 1060 } 1061 1062 return SDValue(); 1063 } 1064 1065 SDValue 1066 MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 1067 SelectionDAG &DAG = DCI.DAG; 1068 SDValue Val; 1069 1070 switch (N->getOpcode()) { 1071 case ISD::ADDE: 1072 return performADDECombine(N, DAG, DCI, Subtarget); 1073 case ISD::AND: 1074 Val = performANDCombine(N, DAG, DCI, Subtarget); 1075 break; 1076 case ISD::OR: 1077 Val = performORCombine(N, DAG, DCI, Subtarget); 1078 break; 1079 case ISD::SUBE: 1080 return performSUBECombine(N, DAG, DCI, Subtarget); 1081 case ISD::MUL: 1082 return performMULCombine(N, DAG, DCI, this); 1083 case ISD::SHL: 1084 return performSHLCombine(N, DAG, DCI, Subtarget); 1085 case ISD::SRA: 1086 return performSRACombine(N, DAG, DCI, Subtarget); 1087 case ISD::SRL: 1088 return performSRLCombine(N, DAG, DCI, Subtarget); 1089 case ISD::VSELECT: 1090 return performVSELECTCombine(N, DAG); 1091 case ISD::XOR: 1092 Val = performXORCombine(N, DAG, Subtarget); 1093 break; 1094 case ISD::SETCC: 1095 Val = performSETCCCombine(N, DAG); 1096 break; 1097 } 1098 1099 if (Val.getNode()) { 1100 DEBUG(dbgs() << "\nMipsSE DAG Combine:\n"; 1101 N->printrWithDepth(dbgs(), &DAG); 1102 dbgs() << "\n=> \n"; 1103 Val.getNode()->printrWithDepth(dbgs(), &DAG); 1104 dbgs() << "\n"); 1105 return Val; 1106 } 1107 1108 return MipsTargetLowering::PerformDAGCombine(N, DCI); 1109 } 1110 1111 MachineBasicBlock * 1112 MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 1113 MachineBasicBlock *BB) const { 1114 switch (MI->getOpcode()) { 1115 default: 1116 return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB); 1117 case Mips::BPOSGE32_PSEUDO: 1118 return emitBPOSGE32(MI, BB); 1119 case Mips::SNZ_B_PSEUDO: 1120 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_B); 1121 case Mips::SNZ_H_PSEUDO: 1122 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_H); 1123 case Mips::SNZ_W_PSEUDO: 1124 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_W); 1125 case Mips::SNZ_D_PSEUDO: 1126 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_D); 1127 case Mips::SNZ_V_PSEUDO: 1128 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_V); 1129 case Mips::SZ_B_PSEUDO: 1130 return emitMSACBranchPseudo(MI, BB, Mips::BZ_B); 1131 case Mips::SZ_H_PSEUDO: 1132 return emitMSACBranchPseudo(MI, BB, Mips::BZ_H); 1133 case Mips::SZ_W_PSEUDO: 1134 return emitMSACBranchPseudo(MI, BB, Mips::BZ_W); 1135 case Mips::SZ_D_PSEUDO: 1136 return emitMSACBranchPseudo(MI, BB, Mips::BZ_D); 1137 case Mips::SZ_V_PSEUDO: 1138 return emitMSACBranchPseudo(MI, BB, Mips::BZ_V); 1139 case Mips::COPY_FW_PSEUDO: 1140 return emitCOPY_FW(MI, BB); 1141 case Mips::COPY_FD_PSEUDO: 1142 return emitCOPY_FD(MI, BB); 1143 case Mips::INSERT_FW_PSEUDO: 1144 return emitINSERT_FW(MI, BB); 1145 case Mips::INSERT_FD_PSEUDO: 1146 return emitINSERT_FD(MI, BB); 1147 case Mips::INSERT_B_VIDX_PSEUDO: 1148 return emitINSERT_DF_VIDX(MI, BB, 1, false); 1149 case Mips::INSERT_H_VIDX_PSEUDO: 1150 return emitINSERT_DF_VIDX(MI, BB, 2, false); 1151 case Mips::INSERT_W_VIDX_PSEUDO: 1152 return emitINSERT_DF_VIDX(MI, BB, 4, false); 1153 case Mips::INSERT_D_VIDX_PSEUDO: 1154 return emitINSERT_DF_VIDX(MI, BB, 8, false); 1155 case Mips::INSERT_FW_VIDX_PSEUDO: 1156 return emitINSERT_DF_VIDX(MI, BB, 4, true); 1157 case Mips::INSERT_FD_VIDX_PSEUDO: 1158 return emitINSERT_DF_VIDX(MI, BB, 8, true); 1159 case Mips::FILL_FW_PSEUDO: 1160 return emitFILL_FW(MI, BB); 1161 case Mips::FILL_FD_PSEUDO: 1162 return emitFILL_FD(MI, BB); 1163 case Mips::FEXP2_W_1_PSEUDO: 1164 return emitFEXP2_W_1(MI, BB); 1165 case Mips::FEXP2_D_1_PSEUDO: 1166 return emitFEXP2_D_1(MI, BB); 1167 } 1168 } 1169 1170 bool MipsSETargetLowering::isEligibleForTailCallOptimization( 1171 const CCState &CCInfo, unsigned NextStackOffset, 1172 const MipsFunctionInfo &FI) const { 1173 if (!EnableMipsTailCalls) 1174 return false; 1175 1176 // Return false if either the callee or caller has a byval argument. 1177 if (CCInfo.getInRegsParamsCount() > 0 || FI.hasByvalArg()) 1178 return false; 1179 1180 // Return true if the callee's argument area is no larger than the 1181 // caller's. 1182 return NextStackOffset <= FI.getIncomingArgSize(); 1183 } 1184 1185 void MipsSETargetLowering:: 1186 getOpndList(SmallVectorImpl<SDValue> &Ops, 1187 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 1188 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 1189 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, 1190 SDValue Chain) const { 1191 Ops.push_back(Callee); 1192 MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, 1193 InternalLinkage, IsCallReloc, CLI, Callee, 1194 Chain); 1195 } 1196 1197 SDValue MipsSETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const { 1198 LoadSDNode &Nd = *cast<LoadSDNode>(Op); 1199 1200 if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore) 1201 return MipsTargetLowering::lowerLOAD(Op, DAG); 1202 1203 // Replace a double precision load with two i32 loads and a buildpair64. 1204 SDLoc DL(Op); 1205 SDValue Ptr = Nd.getBasePtr(), Chain = Nd.getChain(); 1206 EVT PtrVT = Ptr.getValueType(); 1207 1208 // i32 load from lower address. 1209 SDValue Lo = DAG.getLoad(MVT::i32, DL, Chain, Ptr, 1210 MachinePointerInfo(), Nd.isVolatile(), 1211 Nd.isNonTemporal(), Nd.isInvariant(), 1212 Nd.getAlignment()); 1213 1214 // i32 load from higher address. 1215 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT)); 1216 SDValue Hi = DAG.getLoad(MVT::i32, DL, Lo.getValue(1), Ptr, 1217 MachinePointerInfo(), Nd.isVolatile(), 1218 Nd.isNonTemporal(), Nd.isInvariant(), 1219 std::min(Nd.getAlignment(), 4U)); 1220 1221 if (!Subtarget.isLittle()) 1222 std::swap(Lo, Hi); 1223 1224 SDValue BP = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi); 1225 SDValue Ops[2] = {BP, Hi.getValue(1)}; 1226 return DAG.getMergeValues(Ops, DL); 1227 } 1228 1229 SDValue MipsSETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const { 1230 StoreSDNode &Nd = *cast<StoreSDNode>(Op); 1231 1232 if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore) 1233 return MipsTargetLowering::lowerSTORE(Op, DAG); 1234 1235 // Replace a double precision store with two extractelement64s and i32 stores. 1236 SDLoc DL(Op); 1237 SDValue Val = Nd.getValue(), Ptr = Nd.getBasePtr(), Chain = Nd.getChain(); 1238 EVT PtrVT = Ptr.getValueType(); 1239 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 1240 Val, DAG.getConstant(0, MVT::i32)); 1241 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 1242 Val, DAG.getConstant(1, MVT::i32)); 1243 1244 if (!Subtarget.isLittle()) 1245 std::swap(Lo, Hi); 1246 1247 // i32 store to lower address. 1248 Chain = DAG.getStore(Chain, DL, Lo, Ptr, MachinePointerInfo(), 1249 Nd.isVolatile(), Nd.isNonTemporal(), Nd.getAlignment(), 1250 Nd.getAAInfo()); 1251 1252 // i32 store to higher address. 1253 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT)); 1254 return DAG.getStore(Chain, DL, Hi, Ptr, MachinePointerInfo(), 1255 Nd.isVolatile(), Nd.isNonTemporal(), 1256 std::min(Nd.getAlignment(), 4U), Nd.getAAInfo()); 1257 } 1258 1259 SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc, 1260 bool HasLo, bool HasHi, 1261 SelectionDAG &DAG) const { 1262 // MIPS32r6/MIPS64r6 removed accumulator based multiplies. 1263 assert(!Subtarget.hasMips32r6()); 1264 1265 EVT Ty = Op.getOperand(0).getValueType(); 1266 SDLoc DL(Op); 1267 SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped, 1268 Op.getOperand(0), Op.getOperand(1)); 1269 SDValue Lo, Hi; 1270 1271 if (HasLo) 1272 Lo = DAG.getNode(MipsISD::MFLO, DL, Ty, Mult); 1273 if (HasHi) 1274 Hi = DAG.getNode(MipsISD::MFHI, DL, Ty, Mult); 1275 1276 if (!HasLo || !HasHi) 1277 return HasLo ? Lo : Hi; 1278 1279 SDValue Vals[] = { Lo, Hi }; 1280 return DAG.getMergeValues(Vals, DL); 1281 } 1282 1283 1284 static SDValue initAccumulator(SDValue In, SDLoc DL, SelectionDAG &DAG) { 1285 SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In, 1286 DAG.getConstant(0, MVT::i32)); 1287 SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In, 1288 DAG.getConstant(1, MVT::i32)); 1289 return DAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, InLo, InHi); 1290 } 1291 1292 static SDValue extractLOHI(SDValue Op, SDLoc DL, SelectionDAG &DAG) { 1293 SDValue Lo = DAG.getNode(MipsISD::MFLO, DL, MVT::i32, Op); 1294 SDValue Hi = DAG.getNode(MipsISD::MFHI, DL, MVT::i32, Op); 1295 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi); 1296 } 1297 1298 // This function expands mips intrinsic nodes which have 64-bit input operands 1299 // or output values. 1300 // 1301 // out64 = intrinsic-node in64 1302 // => 1303 // lo = copy (extract-element (in64, 0)) 1304 // hi = copy (extract-element (in64, 1)) 1305 // mips-specific-node 1306 // v0 = copy lo 1307 // v1 = copy hi 1308 // out64 = merge-values (v0, v1) 1309 // 1310 static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) { 1311 SDLoc DL(Op); 1312 bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other; 1313 SmallVector<SDValue, 3> Ops; 1314 unsigned OpNo = 0; 1315 1316 // See if Op has a chain input. 1317 if (HasChainIn) 1318 Ops.push_back(Op->getOperand(OpNo++)); 1319 1320 // The next operand is the intrinsic opcode. 1321 assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant); 1322 1323 // See if the next operand has type i64. 1324 SDValue Opnd = Op->getOperand(++OpNo), In64; 1325 1326 if (Opnd.getValueType() == MVT::i64) 1327 In64 = initAccumulator(Opnd, DL, DAG); 1328 else 1329 Ops.push_back(Opnd); 1330 1331 // Push the remaining operands. 1332 for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo) 1333 Ops.push_back(Op->getOperand(OpNo)); 1334 1335 // Add In64 to the end of the list. 1336 if (In64.getNode()) 1337 Ops.push_back(In64); 1338 1339 // Scan output. 1340 SmallVector<EVT, 2> ResTys; 1341 1342 for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end(); 1343 I != E; ++I) 1344 ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I); 1345 1346 // Create node. 1347 SDValue Val = DAG.getNode(Opc, DL, ResTys, Ops); 1348 SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val; 1349 1350 if (!HasChainIn) 1351 return Out; 1352 1353 assert(Val->getValueType(1) == MVT::Other); 1354 SDValue Vals[] = { Out, SDValue(Val.getNode(), 1) }; 1355 return DAG.getMergeValues(Vals, DL); 1356 } 1357 1358 // Lower an MSA copy intrinsic into the specified SelectionDAG node 1359 static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) { 1360 SDLoc DL(Op); 1361 SDValue Vec = Op->getOperand(1); 1362 SDValue Idx = Op->getOperand(2); 1363 EVT ResTy = Op->getValueType(0); 1364 EVT EltTy = Vec->getValueType(0).getVectorElementType(); 1365 1366 SDValue Result = DAG.getNode(Opc, DL, ResTy, Vec, Idx, 1367 DAG.getValueType(EltTy)); 1368 1369 return Result; 1370 } 1371 1372 static SDValue lowerMSASplatZExt(SDValue Op, unsigned OpNr, SelectionDAG &DAG) { 1373 EVT ResVecTy = Op->getValueType(0); 1374 EVT ViaVecTy = ResVecTy; 1375 SDLoc DL(Op); 1376 1377 // When ResVecTy == MVT::v2i64, LaneA is the upper 32 bits of the lane and 1378 // LaneB is the lower 32-bits. Otherwise LaneA and LaneB are alternating 1379 // lanes. 1380 SDValue LaneA; 1381 SDValue LaneB = Op->getOperand(2); 1382 1383 if (ResVecTy == MVT::v2i64) { 1384 LaneA = DAG.getConstant(0, MVT::i32); 1385 ViaVecTy = MVT::v4i32; 1386 } else 1387 LaneA = LaneB; 1388 1389 SDValue Ops[16] = { LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, 1390 LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB }; 1391 1392 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy, 1393 makeArrayRef(Ops, ViaVecTy.getVectorNumElements())); 1394 1395 if (ViaVecTy != ResVecTy) 1396 Result = DAG.getNode(ISD::BITCAST, DL, ResVecTy, Result); 1397 1398 return Result; 1399 } 1400 1401 static SDValue lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG) { 1402 return DAG.getConstant(Op->getConstantOperandVal(ImmOp), Op->getValueType(0)); 1403 } 1404 1405 static SDValue getBuildVectorSplat(EVT VecTy, SDValue SplatValue, 1406 bool BigEndian, SelectionDAG &DAG) { 1407 EVT ViaVecTy = VecTy; 1408 SDValue SplatValueA = SplatValue; 1409 SDValue SplatValueB = SplatValue; 1410 SDLoc DL(SplatValue); 1411 1412 if (VecTy == MVT::v2i64) { 1413 // v2i64 BUILD_VECTOR must be performed via v4i32 so split into i32's. 1414 ViaVecTy = MVT::v4i32; 1415 1416 SplatValueA = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValue); 1417 SplatValueB = DAG.getNode(ISD::SRL, DL, MVT::i64, SplatValue, 1418 DAG.getConstant(32, MVT::i32)); 1419 SplatValueB = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValueB); 1420 } 1421 1422 // We currently hold the parts in little endian order. Swap them if 1423 // necessary. 1424 if (BigEndian) 1425 std::swap(SplatValueA, SplatValueB); 1426 1427 SDValue Ops[16] = { SplatValueA, SplatValueB, SplatValueA, SplatValueB, 1428 SplatValueA, SplatValueB, SplatValueA, SplatValueB, 1429 SplatValueA, SplatValueB, SplatValueA, SplatValueB, 1430 SplatValueA, SplatValueB, SplatValueA, SplatValueB }; 1431 1432 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy, 1433 makeArrayRef(Ops, ViaVecTy.getVectorNumElements())); 1434 1435 if (VecTy != ViaVecTy) 1436 Result = DAG.getNode(ISD::BITCAST, DL, VecTy, Result); 1437 1438 return Result; 1439 } 1440 1441 static SDValue lowerMSABinaryBitImmIntr(SDValue Op, SelectionDAG &DAG, 1442 unsigned Opc, SDValue Imm, 1443 bool BigEndian) { 1444 EVT VecTy = Op->getValueType(0); 1445 SDValue Exp2Imm; 1446 SDLoc DL(Op); 1447 1448 // The DAG Combiner can't constant fold bitcasted vectors yet so we must do it 1449 // here for now. 1450 if (VecTy == MVT::v2i64) { 1451 if (ConstantSDNode *CImm = dyn_cast<ConstantSDNode>(Imm)) { 1452 APInt BitImm = APInt(64, 1) << CImm->getAPIntValue(); 1453 1454 SDValue BitImmHiOp = DAG.getConstant(BitImm.lshr(32).trunc(32), MVT::i32); 1455 SDValue BitImmLoOp = DAG.getConstant(BitImm.trunc(32), MVT::i32); 1456 1457 if (BigEndian) 1458 std::swap(BitImmLoOp, BitImmHiOp); 1459 1460 Exp2Imm = 1461 DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, 1462 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4i32, BitImmLoOp, 1463 BitImmHiOp, BitImmLoOp, BitImmHiOp)); 1464 } 1465 } 1466 1467 if (!Exp2Imm.getNode()) { 1468 // We couldnt constant fold, do a vector shift instead 1469 1470 // Extend i32 to i64 if necessary. Sign or zero extend doesn't matter since 1471 // only values 0-63 are valid. 1472 if (VecTy == MVT::v2i64) 1473 Imm = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Imm); 1474 1475 Exp2Imm = getBuildVectorSplat(VecTy, Imm, BigEndian, DAG); 1476 1477 Exp2Imm = 1478 DAG.getNode(ISD::SHL, DL, VecTy, DAG.getConstant(1, VecTy), Exp2Imm); 1479 } 1480 1481 return DAG.getNode(Opc, DL, VecTy, Op->getOperand(1), Exp2Imm); 1482 } 1483 1484 static SDValue lowerMSABitClear(SDValue Op, SelectionDAG &DAG) { 1485 EVT ResTy = Op->getValueType(0); 1486 SDLoc DL(Op); 1487 SDValue One = DAG.getConstant(1, ResTy); 1488 SDValue Bit = DAG.getNode(ISD::SHL, DL, ResTy, One, Op->getOperand(2)); 1489 1490 return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1), 1491 DAG.getNOT(DL, Bit, ResTy)); 1492 } 1493 1494 static SDValue lowerMSABitClearImm(SDValue Op, SelectionDAG &DAG) { 1495 SDLoc DL(Op); 1496 EVT ResTy = Op->getValueType(0); 1497 APInt BitImm = APInt(ResTy.getVectorElementType().getSizeInBits(), 1) 1498 << cast<ConstantSDNode>(Op->getOperand(2))->getAPIntValue(); 1499 SDValue BitMask = DAG.getConstant(~BitImm, ResTy); 1500 1501 return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1), BitMask); 1502 } 1503 1504 SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op, 1505 SelectionDAG &DAG) const { 1506 SDLoc DL(Op); 1507 1508 switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) { 1509 default: 1510 return SDValue(); 1511 case Intrinsic::mips_shilo: 1512 return lowerDSPIntr(Op, DAG, MipsISD::SHILO); 1513 case Intrinsic::mips_dpau_h_qbl: 1514 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL); 1515 case Intrinsic::mips_dpau_h_qbr: 1516 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR); 1517 case Intrinsic::mips_dpsu_h_qbl: 1518 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL); 1519 case Intrinsic::mips_dpsu_h_qbr: 1520 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR); 1521 case Intrinsic::mips_dpa_w_ph: 1522 return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH); 1523 case Intrinsic::mips_dps_w_ph: 1524 return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH); 1525 case Intrinsic::mips_dpax_w_ph: 1526 return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH); 1527 case Intrinsic::mips_dpsx_w_ph: 1528 return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH); 1529 case Intrinsic::mips_mulsa_w_ph: 1530 return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH); 1531 case Intrinsic::mips_mult: 1532 return lowerDSPIntr(Op, DAG, MipsISD::Mult); 1533 case Intrinsic::mips_multu: 1534 return lowerDSPIntr(Op, DAG, MipsISD::Multu); 1535 case Intrinsic::mips_madd: 1536 return lowerDSPIntr(Op, DAG, MipsISD::MAdd); 1537 case Intrinsic::mips_maddu: 1538 return lowerDSPIntr(Op, DAG, MipsISD::MAddu); 1539 case Intrinsic::mips_msub: 1540 return lowerDSPIntr(Op, DAG, MipsISD::MSub); 1541 case Intrinsic::mips_msubu: 1542 return lowerDSPIntr(Op, DAG, MipsISD::MSubu); 1543 case Intrinsic::mips_addv_b: 1544 case Intrinsic::mips_addv_h: 1545 case Intrinsic::mips_addv_w: 1546 case Intrinsic::mips_addv_d: 1547 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1), 1548 Op->getOperand(2)); 1549 case Intrinsic::mips_addvi_b: 1550 case Intrinsic::mips_addvi_h: 1551 case Intrinsic::mips_addvi_w: 1552 case Intrinsic::mips_addvi_d: 1553 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1), 1554 lowerMSASplatImm(Op, 2, DAG)); 1555 case Intrinsic::mips_and_v: 1556 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1), 1557 Op->getOperand(2)); 1558 case Intrinsic::mips_andi_b: 1559 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1), 1560 lowerMSASplatImm(Op, 2, DAG)); 1561 case Intrinsic::mips_bclr_b: 1562 case Intrinsic::mips_bclr_h: 1563 case Intrinsic::mips_bclr_w: 1564 case Intrinsic::mips_bclr_d: 1565 return lowerMSABitClear(Op, DAG); 1566 case Intrinsic::mips_bclri_b: 1567 case Intrinsic::mips_bclri_h: 1568 case Intrinsic::mips_bclri_w: 1569 case Intrinsic::mips_bclri_d: 1570 return lowerMSABitClearImm(Op, DAG); 1571 case Intrinsic::mips_binsli_b: 1572 case Intrinsic::mips_binsli_h: 1573 case Intrinsic::mips_binsli_w: 1574 case Intrinsic::mips_binsli_d: { 1575 // binsli_x(IfClear, IfSet, nbits) -> (vselect LBitsMask, IfSet, IfClear) 1576 EVT VecTy = Op->getValueType(0); 1577 EVT EltTy = VecTy.getVectorElementType(); 1578 APInt Mask = APInt::getHighBitsSet(EltTy.getSizeInBits(), 1579 Op->getConstantOperandVal(3)); 1580 return DAG.getNode(ISD::VSELECT, DL, VecTy, 1581 DAG.getConstant(Mask, VecTy, true), Op->getOperand(2), 1582 Op->getOperand(1)); 1583 } 1584 case Intrinsic::mips_binsri_b: 1585 case Intrinsic::mips_binsri_h: 1586 case Intrinsic::mips_binsri_w: 1587 case Intrinsic::mips_binsri_d: { 1588 // binsri_x(IfClear, IfSet, nbits) -> (vselect RBitsMask, IfSet, IfClear) 1589 EVT VecTy = Op->getValueType(0); 1590 EVT EltTy = VecTy.getVectorElementType(); 1591 APInt Mask = APInt::getLowBitsSet(EltTy.getSizeInBits(), 1592 Op->getConstantOperandVal(3)); 1593 return DAG.getNode(ISD::VSELECT, DL, VecTy, 1594 DAG.getConstant(Mask, VecTy, true), Op->getOperand(2), 1595 Op->getOperand(1)); 1596 } 1597 case Intrinsic::mips_bmnz_v: 1598 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3), 1599 Op->getOperand(2), Op->getOperand(1)); 1600 case Intrinsic::mips_bmnzi_b: 1601 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), 1602 lowerMSASplatImm(Op, 3, DAG), Op->getOperand(2), 1603 Op->getOperand(1)); 1604 case Intrinsic::mips_bmz_v: 1605 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3), 1606 Op->getOperand(1), Op->getOperand(2)); 1607 case Intrinsic::mips_bmzi_b: 1608 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), 1609 lowerMSASplatImm(Op, 3, DAG), Op->getOperand(1), 1610 Op->getOperand(2)); 1611 case Intrinsic::mips_bneg_b: 1612 case Intrinsic::mips_bneg_h: 1613 case Intrinsic::mips_bneg_w: 1614 case Intrinsic::mips_bneg_d: { 1615 EVT VecTy = Op->getValueType(0); 1616 SDValue One = DAG.getConstant(1, VecTy); 1617 1618 return DAG.getNode(ISD::XOR, DL, VecTy, Op->getOperand(1), 1619 DAG.getNode(ISD::SHL, DL, VecTy, One, 1620 Op->getOperand(2))); 1621 } 1622 case Intrinsic::mips_bnegi_b: 1623 case Intrinsic::mips_bnegi_h: 1624 case Intrinsic::mips_bnegi_w: 1625 case Intrinsic::mips_bnegi_d: 1626 return lowerMSABinaryBitImmIntr(Op, DAG, ISD::XOR, Op->getOperand(2), 1627 !Subtarget.isLittle()); 1628 case Intrinsic::mips_bnz_b: 1629 case Intrinsic::mips_bnz_h: 1630 case Intrinsic::mips_bnz_w: 1631 case Intrinsic::mips_bnz_d: 1632 return DAG.getNode(MipsISD::VALL_NONZERO, DL, Op->getValueType(0), 1633 Op->getOperand(1)); 1634 case Intrinsic::mips_bnz_v: 1635 return DAG.getNode(MipsISD::VANY_NONZERO, DL, Op->getValueType(0), 1636 Op->getOperand(1)); 1637 case Intrinsic::mips_bsel_v: 1638 // bsel_v(Mask, IfClear, IfSet) -> (vselect Mask, IfSet, IfClear) 1639 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), 1640 Op->getOperand(1), Op->getOperand(3), 1641 Op->getOperand(2)); 1642 case Intrinsic::mips_bseli_b: 1643 // bseli_v(Mask, IfClear, IfSet) -> (vselect Mask, IfSet, IfClear) 1644 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), 1645 Op->getOperand(1), lowerMSASplatImm(Op, 3, DAG), 1646 Op->getOperand(2)); 1647 case Intrinsic::mips_bset_b: 1648 case Intrinsic::mips_bset_h: 1649 case Intrinsic::mips_bset_w: 1650 case Intrinsic::mips_bset_d: { 1651 EVT VecTy = Op->getValueType(0); 1652 SDValue One = DAG.getConstant(1, VecTy); 1653 1654 return DAG.getNode(ISD::OR, DL, VecTy, Op->getOperand(1), 1655 DAG.getNode(ISD::SHL, DL, VecTy, One, 1656 Op->getOperand(2))); 1657 } 1658 case Intrinsic::mips_bseti_b: 1659 case Intrinsic::mips_bseti_h: 1660 case Intrinsic::mips_bseti_w: 1661 case Intrinsic::mips_bseti_d: 1662 return lowerMSABinaryBitImmIntr(Op, DAG, ISD::OR, Op->getOperand(2), 1663 !Subtarget.isLittle()); 1664 case Intrinsic::mips_bz_b: 1665 case Intrinsic::mips_bz_h: 1666 case Intrinsic::mips_bz_w: 1667 case Intrinsic::mips_bz_d: 1668 return DAG.getNode(MipsISD::VALL_ZERO, DL, Op->getValueType(0), 1669 Op->getOperand(1)); 1670 case Intrinsic::mips_bz_v: 1671 return DAG.getNode(MipsISD::VANY_ZERO, DL, Op->getValueType(0), 1672 Op->getOperand(1)); 1673 case Intrinsic::mips_ceq_b: 1674 case Intrinsic::mips_ceq_h: 1675 case Intrinsic::mips_ceq_w: 1676 case Intrinsic::mips_ceq_d: 1677 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1678 Op->getOperand(2), ISD::SETEQ); 1679 case Intrinsic::mips_ceqi_b: 1680 case Intrinsic::mips_ceqi_h: 1681 case Intrinsic::mips_ceqi_w: 1682 case Intrinsic::mips_ceqi_d: 1683 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1684 lowerMSASplatImm(Op, 2, DAG), ISD::SETEQ); 1685 case Intrinsic::mips_cle_s_b: 1686 case Intrinsic::mips_cle_s_h: 1687 case Intrinsic::mips_cle_s_w: 1688 case Intrinsic::mips_cle_s_d: 1689 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1690 Op->getOperand(2), ISD::SETLE); 1691 case Intrinsic::mips_clei_s_b: 1692 case Intrinsic::mips_clei_s_h: 1693 case Intrinsic::mips_clei_s_w: 1694 case Intrinsic::mips_clei_s_d: 1695 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1696 lowerMSASplatImm(Op, 2, DAG), ISD::SETLE); 1697 case Intrinsic::mips_cle_u_b: 1698 case Intrinsic::mips_cle_u_h: 1699 case Intrinsic::mips_cle_u_w: 1700 case Intrinsic::mips_cle_u_d: 1701 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1702 Op->getOperand(2), ISD::SETULE); 1703 case Intrinsic::mips_clei_u_b: 1704 case Intrinsic::mips_clei_u_h: 1705 case Intrinsic::mips_clei_u_w: 1706 case Intrinsic::mips_clei_u_d: 1707 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1708 lowerMSASplatImm(Op, 2, DAG), ISD::SETULE); 1709 case Intrinsic::mips_clt_s_b: 1710 case Intrinsic::mips_clt_s_h: 1711 case Intrinsic::mips_clt_s_w: 1712 case Intrinsic::mips_clt_s_d: 1713 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1714 Op->getOperand(2), ISD::SETLT); 1715 case Intrinsic::mips_clti_s_b: 1716 case Intrinsic::mips_clti_s_h: 1717 case Intrinsic::mips_clti_s_w: 1718 case Intrinsic::mips_clti_s_d: 1719 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1720 lowerMSASplatImm(Op, 2, DAG), ISD::SETLT); 1721 case Intrinsic::mips_clt_u_b: 1722 case Intrinsic::mips_clt_u_h: 1723 case Intrinsic::mips_clt_u_w: 1724 case Intrinsic::mips_clt_u_d: 1725 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1726 Op->getOperand(2), ISD::SETULT); 1727 case Intrinsic::mips_clti_u_b: 1728 case Intrinsic::mips_clti_u_h: 1729 case Intrinsic::mips_clti_u_w: 1730 case Intrinsic::mips_clti_u_d: 1731 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1732 lowerMSASplatImm(Op, 2, DAG), ISD::SETULT); 1733 case Intrinsic::mips_copy_s_b: 1734 case Intrinsic::mips_copy_s_h: 1735 case Intrinsic::mips_copy_s_w: 1736 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT); 1737 case Intrinsic::mips_copy_s_d: 1738 if (Subtarget.hasMips64()) 1739 // Lower directly into VEXTRACT_SEXT_ELT since i64 is legal on Mips64. 1740 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT); 1741 else { 1742 // Lower into the generic EXTRACT_VECTOR_ELT node and let the type 1743 // legalizer and EXTRACT_VECTOR_ELT lowering sort it out. 1744 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), 1745 Op->getValueType(0), Op->getOperand(1), 1746 Op->getOperand(2)); 1747 } 1748 case Intrinsic::mips_copy_u_b: 1749 case Intrinsic::mips_copy_u_h: 1750 case Intrinsic::mips_copy_u_w: 1751 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT); 1752 case Intrinsic::mips_copy_u_d: 1753 if (Subtarget.hasMips64()) 1754 // Lower directly into VEXTRACT_ZEXT_ELT since i64 is legal on Mips64. 1755 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT); 1756 else { 1757 // Lower into the generic EXTRACT_VECTOR_ELT node and let the type 1758 // legalizer and EXTRACT_VECTOR_ELT lowering sort it out. 1759 // Note: When i64 is illegal, this results in copy_s.w instructions 1760 // instead of copy_u.w instructions. This makes no difference to the 1761 // behaviour since i64 is only illegal when the register file is 32-bit. 1762 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), 1763 Op->getValueType(0), Op->getOperand(1), 1764 Op->getOperand(2)); 1765 } 1766 case Intrinsic::mips_div_s_b: 1767 case Intrinsic::mips_div_s_h: 1768 case Intrinsic::mips_div_s_w: 1769 case Intrinsic::mips_div_s_d: 1770 return DAG.getNode(ISD::SDIV, DL, Op->getValueType(0), Op->getOperand(1), 1771 Op->getOperand(2)); 1772 case Intrinsic::mips_div_u_b: 1773 case Intrinsic::mips_div_u_h: 1774 case Intrinsic::mips_div_u_w: 1775 case Intrinsic::mips_div_u_d: 1776 return DAG.getNode(ISD::UDIV, DL, Op->getValueType(0), Op->getOperand(1), 1777 Op->getOperand(2)); 1778 case Intrinsic::mips_fadd_w: 1779 case Intrinsic::mips_fadd_d: 1780 return DAG.getNode(ISD::FADD, DL, Op->getValueType(0), Op->getOperand(1), 1781 Op->getOperand(2)); 1782 // Don't lower mips_fcaf_[wd] since LLVM folds SETFALSE condcodes away 1783 case Intrinsic::mips_fceq_w: 1784 case Intrinsic::mips_fceq_d: 1785 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1786 Op->getOperand(2), ISD::SETOEQ); 1787 case Intrinsic::mips_fcle_w: 1788 case Intrinsic::mips_fcle_d: 1789 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1790 Op->getOperand(2), ISD::SETOLE); 1791 case Intrinsic::mips_fclt_w: 1792 case Intrinsic::mips_fclt_d: 1793 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1794 Op->getOperand(2), ISD::SETOLT); 1795 case Intrinsic::mips_fcne_w: 1796 case Intrinsic::mips_fcne_d: 1797 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1798 Op->getOperand(2), ISD::SETONE); 1799 case Intrinsic::mips_fcor_w: 1800 case Intrinsic::mips_fcor_d: 1801 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1802 Op->getOperand(2), ISD::SETO); 1803 case Intrinsic::mips_fcueq_w: 1804 case Intrinsic::mips_fcueq_d: 1805 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1806 Op->getOperand(2), ISD::SETUEQ); 1807 case Intrinsic::mips_fcule_w: 1808 case Intrinsic::mips_fcule_d: 1809 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1810 Op->getOperand(2), ISD::SETULE); 1811 case Intrinsic::mips_fcult_w: 1812 case Intrinsic::mips_fcult_d: 1813 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1814 Op->getOperand(2), ISD::SETULT); 1815 case Intrinsic::mips_fcun_w: 1816 case Intrinsic::mips_fcun_d: 1817 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1818 Op->getOperand(2), ISD::SETUO); 1819 case Intrinsic::mips_fcune_w: 1820 case Intrinsic::mips_fcune_d: 1821 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1822 Op->getOperand(2), ISD::SETUNE); 1823 case Intrinsic::mips_fdiv_w: 1824 case Intrinsic::mips_fdiv_d: 1825 return DAG.getNode(ISD::FDIV, DL, Op->getValueType(0), Op->getOperand(1), 1826 Op->getOperand(2)); 1827 case Intrinsic::mips_ffint_u_w: 1828 case Intrinsic::mips_ffint_u_d: 1829 return DAG.getNode(ISD::UINT_TO_FP, DL, Op->getValueType(0), 1830 Op->getOperand(1)); 1831 case Intrinsic::mips_ffint_s_w: 1832 case Intrinsic::mips_ffint_s_d: 1833 return DAG.getNode(ISD::SINT_TO_FP, DL, Op->getValueType(0), 1834 Op->getOperand(1)); 1835 case Intrinsic::mips_fill_b: 1836 case Intrinsic::mips_fill_h: 1837 case Intrinsic::mips_fill_w: 1838 case Intrinsic::mips_fill_d: { 1839 EVT ResTy = Op->getValueType(0); 1840 SmallVector<SDValue, 16> Ops(ResTy.getVectorNumElements(), 1841 Op->getOperand(1)); 1842 1843 // If ResTy is v2i64 then the type legalizer will break this node down into 1844 // an equivalent v4i32. 1845 return DAG.getNode(ISD::BUILD_VECTOR, DL, ResTy, Ops); 1846 } 1847 case Intrinsic::mips_fexp2_w: 1848 case Intrinsic::mips_fexp2_d: { 1849 EVT ResTy = Op->getValueType(0); 1850 return DAG.getNode( 1851 ISD::FMUL, SDLoc(Op), ResTy, Op->getOperand(1), 1852 DAG.getNode(ISD::FEXP2, SDLoc(Op), ResTy, Op->getOperand(2))); 1853 } 1854 case Intrinsic::mips_flog2_w: 1855 case Intrinsic::mips_flog2_d: 1856 return DAG.getNode(ISD::FLOG2, DL, Op->getValueType(0), Op->getOperand(1)); 1857 case Intrinsic::mips_fmadd_w: 1858 case Intrinsic::mips_fmadd_d: 1859 return DAG.getNode(ISD::FMA, SDLoc(Op), Op->getValueType(0), 1860 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3)); 1861 case Intrinsic::mips_fmul_w: 1862 case Intrinsic::mips_fmul_d: 1863 return DAG.getNode(ISD::FMUL, DL, Op->getValueType(0), Op->getOperand(1), 1864 Op->getOperand(2)); 1865 case Intrinsic::mips_fmsub_w: 1866 case Intrinsic::mips_fmsub_d: { 1867 EVT ResTy = Op->getValueType(0); 1868 return DAG.getNode(ISD::FSUB, SDLoc(Op), ResTy, Op->getOperand(1), 1869 DAG.getNode(ISD::FMUL, SDLoc(Op), ResTy, 1870 Op->getOperand(2), Op->getOperand(3))); 1871 } 1872 case Intrinsic::mips_frint_w: 1873 case Intrinsic::mips_frint_d: 1874 return DAG.getNode(ISD::FRINT, DL, Op->getValueType(0), Op->getOperand(1)); 1875 case Intrinsic::mips_fsqrt_w: 1876 case Intrinsic::mips_fsqrt_d: 1877 return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1)); 1878 case Intrinsic::mips_fsub_w: 1879 case Intrinsic::mips_fsub_d: 1880 return DAG.getNode(ISD::FSUB, DL, Op->getValueType(0), Op->getOperand(1), 1881 Op->getOperand(2)); 1882 case Intrinsic::mips_ftrunc_u_w: 1883 case Intrinsic::mips_ftrunc_u_d: 1884 return DAG.getNode(ISD::FP_TO_UINT, DL, Op->getValueType(0), 1885 Op->getOperand(1)); 1886 case Intrinsic::mips_ftrunc_s_w: 1887 case Intrinsic::mips_ftrunc_s_d: 1888 return DAG.getNode(ISD::FP_TO_SINT, DL, Op->getValueType(0), 1889 Op->getOperand(1)); 1890 case Intrinsic::mips_ilvev_b: 1891 case Intrinsic::mips_ilvev_h: 1892 case Intrinsic::mips_ilvev_w: 1893 case Intrinsic::mips_ilvev_d: 1894 return DAG.getNode(MipsISD::ILVEV, DL, Op->getValueType(0), 1895 Op->getOperand(1), Op->getOperand(2)); 1896 case Intrinsic::mips_ilvl_b: 1897 case Intrinsic::mips_ilvl_h: 1898 case Intrinsic::mips_ilvl_w: 1899 case Intrinsic::mips_ilvl_d: 1900 return DAG.getNode(MipsISD::ILVL, DL, Op->getValueType(0), 1901 Op->getOperand(1), Op->getOperand(2)); 1902 case Intrinsic::mips_ilvod_b: 1903 case Intrinsic::mips_ilvod_h: 1904 case Intrinsic::mips_ilvod_w: 1905 case Intrinsic::mips_ilvod_d: 1906 return DAG.getNode(MipsISD::ILVOD, DL, Op->getValueType(0), 1907 Op->getOperand(1), Op->getOperand(2)); 1908 case Intrinsic::mips_ilvr_b: 1909 case Intrinsic::mips_ilvr_h: 1910 case Intrinsic::mips_ilvr_w: 1911 case Intrinsic::mips_ilvr_d: 1912 return DAG.getNode(MipsISD::ILVR, DL, Op->getValueType(0), 1913 Op->getOperand(1), Op->getOperand(2)); 1914 case Intrinsic::mips_insert_b: 1915 case Intrinsic::mips_insert_h: 1916 case Intrinsic::mips_insert_w: 1917 case Intrinsic::mips_insert_d: 1918 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0), 1919 Op->getOperand(1), Op->getOperand(3), Op->getOperand(2)); 1920 case Intrinsic::mips_insve_b: 1921 case Intrinsic::mips_insve_h: 1922 case Intrinsic::mips_insve_w: 1923 case Intrinsic::mips_insve_d: 1924 return DAG.getNode(MipsISD::INSVE, DL, Op->getValueType(0), 1925 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3), 1926 DAG.getConstant(0, MVT::i32)); 1927 case Intrinsic::mips_ldi_b: 1928 case Intrinsic::mips_ldi_h: 1929 case Intrinsic::mips_ldi_w: 1930 case Intrinsic::mips_ldi_d: 1931 return lowerMSASplatImm(Op, 1, DAG); 1932 case Intrinsic::mips_lsa: 1933 case Intrinsic::mips_dlsa: { 1934 EVT ResTy = Op->getValueType(0); 1935 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1), 1936 DAG.getNode(ISD::SHL, SDLoc(Op), ResTy, 1937 Op->getOperand(2), Op->getOperand(3))); 1938 } 1939 case Intrinsic::mips_maddv_b: 1940 case Intrinsic::mips_maddv_h: 1941 case Intrinsic::mips_maddv_w: 1942 case Intrinsic::mips_maddv_d: { 1943 EVT ResTy = Op->getValueType(0); 1944 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1), 1945 DAG.getNode(ISD::MUL, SDLoc(Op), ResTy, 1946 Op->getOperand(2), Op->getOperand(3))); 1947 } 1948 case Intrinsic::mips_max_s_b: 1949 case Intrinsic::mips_max_s_h: 1950 case Intrinsic::mips_max_s_w: 1951 case Intrinsic::mips_max_s_d: 1952 return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0), 1953 Op->getOperand(1), Op->getOperand(2)); 1954 case Intrinsic::mips_max_u_b: 1955 case Intrinsic::mips_max_u_h: 1956 case Intrinsic::mips_max_u_w: 1957 case Intrinsic::mips_max_u_d: 1958 return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0), 1959 Op->getOperand(1), Op->getOperand(2)); 1960 case Intrinsic::mips_maxi_s_b: 1961 case Intrinsic::mips_maxi_s_h: 1962 case Intrinsic::mips_maxi_s_w: 1963 case Intrinsic::mips_maxi_s_d: 1964 return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0), 1965 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1966 case Intrinsic::mips_maxi_u_b: 1967 case Intrinsic::mips_maxi_u_h: 1968 case Intrinsic::mips_maxi_u_w: 1969 case Intrinsic::mips_maxi_u_d: 1970 return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0), 1971 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1972 case Intrinsic::mips_min_s_b: 1973 case Intrinsic::mips_min_s_h: 1974 case Intrinsic::mips_min_s_w: 1975 case Intrinsic::mips_min_s_d: 1976 return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0), 1977 Op->getOperand(1), Op->getOperand(2)); 1978 case Intrinsic::mips_min_u_b: 1979 case Intrinsic::mips_min_u_h: 1980 case Intrinsic::mips_min_u_w: 1981 case Intrinsic::mips_min_u_d: 1982 return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0), 1983 Op->getOperand(1), Op->getOperand(2)); 1984 case Intrinsic::mips_mini_s_b: 1985 case Intrinsic::mips_mini_s_h: 1986 case Intrinsic::mips_mini_s_w: 1987 case Intrinsic::mips_mini_s_d: 1988 return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0), 1989 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1990 case Intrinsic::mips_mini_u_b: 1991 case Intrinsic::mips_mini_u_h: 1992 case Intrinsic::mips_mini_u_w: 1993 case Intrinsic::mips_mini_u_d: 1994 return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0), 1995 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1996 case Intrinsic::mips_mod_s_b: 1997 case Intrinsic::mips_mod_s_h: 1998 case Intrinsic::mips_mod_s_w: 1999 case Intrinsic::mips_mod_s_d: 2000 return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1), 2001 Op->getOperand(2)); 2002 case Intrinsic::mips_mod_u_b: 2003 case Intrinsic::mips_mod_u_h: 2004 case Intrinsic::mips_mod_u_w: 2005 case Intrinsic::mips_mod_u_d: 2006 return DAG.getNode(ISD::UREM, DL, Op->getValueType(0), Op->getOperand(1), 2007 Op->getOperand(2)); 2008 case Intrinsic::mips_mulv_b: 2009 case Intrinsic::mips_mulv_h: 2010 case Intrinsic::mips_mulv_w: 2011 case Intrinsic::mips_mulv_d: 2012 return DAG.getNode(ISD::MUL, DL, Op->getValueType(0), Op->getOperand(1), 2013 Op->getOperand(2)); 2014 case Intrinsic::mips_msubv_b: 2015 case Intrinsic::mips_msubv_h: 2016 case Intrinsic::mips_msubv_w: 2017 case Intrinsic::mips_msubv_d: { 2018 EVT ResTy = Op->getValueType(0); 2019 return DAG.getNode(ISD::SUB, SDLoc(Op), ResTy, Op->getOperand(1), 2020 DAG.getNode(ISD::MUL, SDLoc(Op), ResTy, 2021 Op->getOperand(2), Op->getOperand(3))); 2022 } 2023 case Intrinsic::mips_nlzc_b: 2024 case Intrinsic::mips_nlzc_h: 2025 case Intrinsic::mips_nlzc_w: 2026 case Intrinsic::mips_nlzc_d: 2027 return DAG.getNode(ISD::CTLZ, DL, Op->getValueType(0), Op->getOperand(1)); 2028 case Intrinsic::mips_nor_v: { 2029 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0), 2030 Op->getOperand(1), Op->getOperand(2)); 2031 return DAG.getNOT(DL, Res, Res->getValueType(0)); 2032 } 2033 case Intrinsic::mips_nori_b: { 2034 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0), 2035 Op->getOperand(1), 2036 lowerMSASplatImm(Op, 2, DAG)); 2037 return DAG.getNOT(DL, Res, Res->getValueType(0)); 2038 } 2039 case Intrinsic::mips_or_v: 2040 return DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1), 2041 Op->getOperand(2)); 2042 case Intrinsic::mips_ori_b: 2043 return DAG.getNode(ISD::OR, DL, Op->getValueType(0), 2044 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 2045 case Intrinsic::mips_pckev_b: 2046 case Intrinsic::mips_pckev_h: 2047 case Intrinsic::mips_pckev_w: 2048 case Intrinsic::mips_pckev_d: 2049 return DAG.getNode(MipsISD::PCKEV, DL, Op->getValueType(0), 2050 Op->getOperand(1), Op->getOperand(2)); 2051 case Intrinsic::mips_pckod_b: 2052 case Intrinsic::mips_pckod_h: 2053 case Intrinsic::mips_pckod_w: 2054 case Intrinsic::mips_pckod_d: 2055 return DAG.getNode(MipsISD::PCKOD, DL, Op->getValueType(0), 2056 Op->getOperand(1), Op->getOperand(2)); 2057 case Intrinsic::mips_pcnt_b: 2058 case Intrinsic::mips_pcnt_h: 2059 case Intrinsic::mips_pcnt_w: 2060 case Intrinsic::mips_pcnt_d: 2061 return DAG.getNode(ISD::CTPOP, DL, Op->getValueType(0), Op->getOperand(1)); 2062 case Intrinsic::mips_shf_b: 2063 case Intrinsic::mips_shf_h: 2064 case Intrinsic::mips_shf_w: 2065 return DAG.getNode(MipsISD::SHF, DL, Op->getValueType(0), 2066 Op->getOperand(2), Op->getOperand(1)); 2067 case Intrinsic::mips_sll_b: 2068 case Intrinsic::mips_sll_h: 2069 case Intrinsic::mips_sll_w: 2070 case Intrinsic::mips_sll_d: 2071 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), Op->getOperand(1), 2072 Op->getOperand(2)); 2073 case Intrinsic::mips_slli_b: 2074 case Intrinsic::mips_slli_h: 2075 case Intrinsic::mips_slli_w: 2076 case Intrinsic::mips_slli_d: 2077 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), 2078 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 2079 case Intrinsic::mips_splat_b: 2080 case Intrinsic::mips_splat_h: 2081 case Intrinsic::mips_splat_w: 2082 case Intrinsic::mips_splat_d: 2083 // We can't lower via VECTOR_SHUFFLE because it requires constant shuffle 2084 // masks, nor can we lower via BUILD_VECTOR & EXTRACT_VECTOR_ELT because 2085 // EXTRACT_VECTOR_ELT can't extract i64's on MIPS32. 2086 // Instead we lower to MipsISD::VSHF and match from there. 2087 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0), 2088 lowerMSASplatZExt(Op, 2, DAG), Op->getOperand(1), 2089 Op->getOperand(1)); 2090 case Intrinsic::mips_splati_b: 2091 case Intrinsic::mips_splati_h: 2092 case Intrinsic::mips_splati_w: 2093 case Intrinsic::mips_splati_d: 2094 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0), 2095 lowerMSASplatImm(Op, 2, DAG), Op->getOperand(1), 2096 Op->getOperand(1)); 2097 case Intrinsic::mips_sra_b: 2098 case Intrinsic::mips_sra_h: 2099 case Intrinsic::mips_sra_w: 2100 case Intrinsic::mips_sra_d: 2101 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), Op->getOperand(1), 2102 Op->getOperand(2)); 2103 case Intrinsic::mips_srai_b: 2104 case Intrinsic::mips_srai_h: 2105 case Intrinsic::mips_srai_w: 2106 case Intrinsic::mips_srai_d: 2107 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), 2108 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 2109 case Intrinsic::mips_srl_b: 2110 case Intrinsic::mips_srl_h: 2111 case Intrinsic::mips_srl_w: 2112 case Intrinsic::mips_srl_d: 2113 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), Op->getOperand(1), 2114 Op->getOperand(2)); 2115 case Intrinsic::mips_srli_b: 2116 case Intrinsic::mips_srli_h: 2117 case Intrinsic::mips_srli_w: 2118 case Intrinsic::mips_srli_d: 2119 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), 2120 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 2121 case Intrinsic::mips_subv_b: 2122 case Intrinsic::mips_subv_h: 2123 case Intrinsic::mips_subv_w: 2124 case Intrinsic::mips_subv_d: 2125 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), Op->getOperand(1), 2126 Op->getOperand(2)); 2127 case Intrinsic::mips_subvi_b: 2128 case Intrinsic::mips_subvi_h: 2129 case Intrinsic::mips_subvi_w: 2130 case Intrinsic::mips_subvi_d: 2131 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), 2132 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 2133 case Intrinsic::mips_vshf_b: 2134 case Intrinsic::mips_vshf_h: 2135 case Intrinsic::mips_vshf_w: 2136 case Intrinsic::mips_vshf_d: 2137 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0), 2138 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3)); 2139 case Intrinsic::mips_xor_v: 2140 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), Op->getOperand(1), 2141 Op->getOperand(2)); 2142 case Intrinsic::mips_xori_b: 2143 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), 2144 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 2145 } 2146 } 2147 2148 static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) { 2149 SDLoc DL(Op); 2150 SDValue ChainIn = Op->getOperand(0); 2151 SDValue Address = Op->getOperand(2); 2152 SDValue Offset = Op->getOperand(3); 2153 EVT ResTy = Op->getValueType(0); 2154 EVT PtrTy = Address->getValueType(0); 2155 2156 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset); 2157 2158 return DAG.getLoad(ResTy, DL, ChainIn, Address, MachinePointerInfo(), false, 2159 false, false, 16); 2160 } 2161 2162 SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op, 2163 SelectionDAG &DAG) const { 2164 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue(); 2165 switch (Intr) { 2166 default: 2167 return SDValue(); 2168 case Intrinsic::mips_extp: 2169 return lowerDSPIntr(Op, DAG, MipsISD::EXTP); 2170 case Intrinsic::mips_extpdp: 2171 return lowerDSPIntr(Op, DAG, MipsISD::EXTPDP); 2172 case Intrinsic::mips_extr_w: 2173 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W); 2174 case Intrinsic::mips_extr_r_w: 2175 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W); 2176 case Intrinsic::mips_extr_rs_w: 2177 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W); 2178 case Intrinsic::mips_extr_s_h: 2179 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H); 2180 case Intrinsic::mips_mthlip: 2181 return lowerDSPIntr(Op, DAG, MipsISD::MTHLIP); 2182 case Intrinsic::mips_mulsaq_s_w_ph: 2183 return lowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH); 2184 case Intrinsic::mips_maq_s_w_phl: 2185 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL); 2186 case Intrinsic::mips_maq_s_w_phr: 2187 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR); 2188 case Intrinsic::mips_maq_sa_w_phl: 2189 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL); 2190 case Intrinsic::mips_maq_sa_w_phr: 2191 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR); 2192 case Intrinsic::mips_dpaq_s_w_ph: 2193 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH); 2194 case Intrinsic::mips_dpsq_s_w_ph: 2195 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH); 2196 case Intrinsic::mips_dpaq_sa_l_w: 2197 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W); 2198 case Intrinsic::mips_dpsq_sa_l_w: 2199 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W); 2200 case Intrinsic::mips_dpaqx_s_w_ph: 2201 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH); 2202 case Intrinsic::mips_dpaqx_sa_w_ph: 2203 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH); 2204 case Intrinsic::mips_dpsqx_s_w_ph: 2205 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH); 2206 case Intrinsic::mips_dpsqx_sa_w_ph: 2207 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH); 2208 case Intrinsic::mips_ld_b: 2209 case Intrinsic::mips_ld_h: 2210 case Intrinsic::mips_ld_w: 2211 case Intrinsic::mips_ld_d: 2212 return lowerMSALoadIntr(Op, DAG, Intr); 2213 } 2214 } 2215 2216 static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) { 2217 SDLoc DL(Op); 2218 SDValue ChainIn = Op->getOperand(0); 2219 SDValue Value = Op->getOperand(2); 2220 SDValue Address = Op->getOperand(3); 2221 SDValue Offset = Op->getOperand(4); 2222 EVT PtrTy = Address->getValueType(0); 2223 2224 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset); 2225 2226 return DAG.getStore(ChainIn, DL, Value, Address, MachinePointerInfo(), false, 2227 false, 16); 2228 } 2229 2230 SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op, 2231 SelectionDAG &DAG) const { 2232 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue(); 2233 switch (Intr) { 2234 default: 2235 return SDValue(); 2236 case Intrinsic::mips_st_b: 2237 case Intrinsic::mips_st_h: 2238 case Intrinsic::mips_st_w: 2239 case Intrinsic::mips_st_d: 2240 return lowerMSAStoreIntr(Op, DAG, Intr); 2241 } 2242 } 2243 2244 /// \brief Check if the given BuildVectorSDNode is a splat. 2245 /// This method currently relies on DAG nodes being reused when equivalent, 2246 /// so it's possible for this to return false even when isConstantSplat returns 2247 /// true. 2248 static bool isSplatVector(const BuildVectorSDNode *N) { 2249 unsigned int nOps = N->getNumOperands(); 2250 assert(nOps > 1 && "isSplatVector has 0 or 1 sized build vector"); 2251 2252 SDValue Operand0 = N->getOperand(0); 2253 2254 for (unsigned int i = 1; i < nOps; ++i) { 2255 if (N->getOperand(i) != Operand0) 2256 return false; 2257 } 2258 2259 return true; 2260 } 2261 2262 // Lower ISD::EXTRACT_VECTOR_ELT into MipsISD::VEXTRACT_SEXT_ELT. 2263 // 2264 // The non-value bits resulting from ISD::EXTRACT_VECTOR_ELT are undefined. We 2265 // choose to sign-extend but we could have equally chosen zero-extend. The 2266 // DAGCombiner will fold any sign/zero extension of the ISD::EXTRACT_VECTOR_ELT 2267 // result into this node later (possibly changing it to a zero-extend in the 2268 // process). 2269 SDValue MipsSETargetLowering:: 2270 lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const { 2271 SDLoc DL(Op); 2272 EVT ResTy = Op->getValueType(0); 2273 SDValue Op0 = Op->getOperand(0); 2274 EVT VecTy = Op0->getValueType(0); 2275 2276 if (!VecTy.is128BitVector()) 2277 return SDValue(); 2278 2279 if (ResTy.isInteger()) { 2280 SDValue Op1 = Op->getOperand(1); 2281 EVT EltTy = VecTy.getVectorElementType(); 2282 return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, DL, ResTy, Op0, Op1, 2283 DAG.getValueType(EltTy)); 2284 } 2285 2286 return Op; 2287 } 2288 2289 static bool isConstantOrUndef(const SDValue Op) { 2290 if (Op->getOpcode() == ISD::UNDEF) 2291 return true; 2292 if (isa<ConstantSDNode>(Op)) 2293 return true; 2294 if (isa<ConstantFPSDNode>(Op)) 2295 return true; 2296 return false; 2297 } 2298 2299 static bool isConstantOrUndefBUILD_VECTOR(const BuildVectorSDNode *Op) { 2300 for (unsigned i = 0; i < Op->getNumOperands(); ++i) 2301 if (isConstantOrUndef(Op->getOperand(i))) 2302 return true; 2303 return false; 2304 } 2305 2306 // Lowers ISD::BUILD_VECTOR into appropriate SelectionDAG nodes for the 2307 // backend. 2308 // 2309 // Lowers according to the following rules: 2310 // - Constant splats are legal as-is as long as the SplatBitSize is a power of 2311 // 2 less than or equal to 64 and the value fits into a signed 10-bit 2312 // immediate 2313 // - Constant splats are lowered to bitconverted BUILD_VECTORs if SplatBitSize 2314 // is a power of 2 less than or equal to 64 and the value does not fit into a 2315 // signed 10-bit immediate 2316 // - Non-constant splats are legal as-is. 2317 // - Non-constant non-splats are lowered to sequences of INSERT_VECTOR_ELT. 2318 // - All others are illegal and must be expanded. 2319 SDValue MipsSETargetLowering::lowerBUILD_VECTOR(SDValue Op, 2320 SelectionDAG &DAG) const { 2321 BuildVectorSDNode *Node = cast<BuildVectorSDNode>(Op); 2322 EVT ResTy = Op->getValueType(0); 2323 SDLoc DL(Op); 2324 APInt SplatValue, SplatUndef; 2325 unsigned SplatBitSize; 2326 bool HasAnyUndefs; 2327 2328 if (!Subtarget.hasMSA() || !ResTy.is128BitVector()) 2329 return SDValue(); 2330 2331 if (Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, 2332 HasAnyUndefs, 8, 2333 !Subtarget.isLittle()) && SplatBitSize <= 64) { 2334 // We can only cope with 8, 16, 32, or 64-bit elements 2335 if (SplatBitSize != 8 && SplatBitSize != 16 && SplatBitSize != 32 && 2336 SplatBitSize != 64) 2337 return SDValue(); 2338 2339 // If the value fits into a simm10 then we can use ldi.[bhwd] 2340 // However, if it isn't an integer type we will have to bitcast from an 2341 // integer type first. Also, if there are any undefs, we must lower them 2342 // to defined values first. 2343 if (ResTy.isInteger() && !HasAnyUndefs && SplatValue.isSignedIntN(10)) 2344 return Op; 2345 2346 EVT ViaVecTy; 2347 2348 switch (SplatBitSize) { 2349 default: 2350 return SDValue(); 2351 case 8: 2352 ViaVecTy = MVT::v16i8; 2353 break; 2354 case 16: 2355 ViaVecTy = MVT::v8i16; 2356 break; 2357 case 32: 2358 ViaVecTy = MVT::v4i32; 2359 break; 2360 case 64: 2361 // There's no fill.d to fall back on for 64-bit values 2362 return SDValue(); 2363 } 2364 2365 // SelectionDAG::getConstant will promote SplatValue appropriately. 2366 SDValue Result = DAG.getConstant(SplatValue, ViaVecTy); 2367 2368 // Bitcast to the type we originally wanted 2369 if (ViaVecTy != ResTy) 2370 Result = DAG.getNode(ISD::BITCAST, SDLoc(Node), ResTy, Result); 2371 2372 return Result; 2373 } else if (isSplatVector(Node)) 2374 return Op; 2375 else if (!isConstantOrUndefBUILD_VECTOR(Node)) { 2376 // Use INSERT_VECTOR_ELT operations rather than expand to stores. 2377 // The resulting code is the same length as the expansion, but it doesn't 2378 // use memory operations 2379 EVT ResTy = Node->getValueType(0); 2380 2381 assert(ResTy.isVector()); 2382 2383 unsigned NumElts = ResTy.getVectorNumElements(); 2384 SDValue Vector = DAG.getUNDEF(ResTy); 2385 for (unsigned i = 0; i < NumElts; ++i) { 2386 Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector, 2387 Node->getOperand(i), 2388 DAG.getConstant(i, MVT::i32)); 2389 } 2390 return Vector; 2391 } 2392 2393 return SDValue(); 2394 } 2395 2396 // Lower VECTOR_SHUFFLE into SHF (if possible). 2397 // 2398 // SHF splits the vector into blocks of four elements, then shuffles these 2399 // elements according to a <4 x i2> constant (encoded as an integer immediate). 2400 // 2401 // It is therefore possible to lower into SHF when the mask takes the form: 2402 // <a, b, c, d, a+4, b+4, c+4, d+4, a+8, b+8, c+8, d+8, ...> 2403 // When undef's appear they are treated as if they were whatever value is 2404 // necessary in order to fit the above form. 2405 // 2406 // For example: 2407 // %2 = shufflevector <8 x i16> %0, <8 x i16> undef, 2408 // <8 x i32> <i32 3, i32 2, i32 1, i32 0, 2409 // i32 7, i32 6, i32 5, i32 4> 2410 // is lowered to: 2411 // (SHF_H $w0, $w1, 27) 2412 // where the 27 comes from: 2413 // 3 + (2 << 2) + (1 << 4) + (0 << 6) 2414 static SDValue lowerVECTOR_SHUFFLE_SHF(SDValue Op, EVT ResTy, 2415 SmallVector<int, 16> Indices, 2416 SelectionDAG &DAG) { 2417 int SHFIndices[4] = { -1, -1, -1, -1 }; 2418 2419 if (Indices.size() < 4) 2420 return SDValue(); 2421 2422 for (unsigned i = 0; i < 4; ++i) { 2423 for (unsigned j = i; j < Indices.size(); j += 4) { 2424 int Idx = Indices[j]; 2425 2426 // Convert from vector index to 4-element subvector index 2427 // If an index refers to an element outside of the subvector then give up 2428 if (Idx != -1) { 2429 Idx -= 4 * (j / 4); 2430 if (Idx < 0 || Idx >= 4) 2431 return SDValue(); 2432 } 2433 2434 // If the mask has an undef, replace it with the current index. 2435 // Note that it might still be undef if the current index is also undef 2436 if (SHFIndices[i] == -1) 2437 SHFIndices[i] = Idx; 2438 2439 // Check that non-undef values are the same as in the mask. If they 2440 // aren't then give up 2441 if (!(Idx == -1 || Idx == SHFIndices[i])) 2442 return SDValue(); 2443 } 2444 } 2445 2446 // Calculate the immediate. Replace any remaining undefs with zero 2447 APInt Imm(32, 0); 2448 for (int i = 3; i >= 0; --i) { 2449 int Idx = SHFIndices[i]; 2450 2451 if (Idx == -1) 2452 Idx = 0; 2453 2454 Imm <<= 2; 2455 Imm |= Idx & 0x3; 2456 } 2457 2458 return DAG.getNode(MipsISD::SHF, SDLoc(Op), ResTy, 2459 DAG.getConstant(Imm, MVT::i32), Op->getOperand(0)); 2460 } 2461 2462 // Lower VECTOR_SHUFFLE into ILVEV (if possible). 2463 // 2464 // ILVEV interleaves the even elements from each vector. 2465 // 2466 // It is possible to lower into ILVEV when the mask takes the form: 2467 // <0, n, 2, n+2, 4, n+4, ...> 2468 // where n is the number of elements in the vector. 2469 // 2470 // When undef's appear in the mask they are treated as if they were whatever 2471 // value is necessary in order to fit the above form. 2472 static SDValue lowerVECTOR_SHUFFLE_ILVEV(SDValue Op, EVT ResTy, 2473 SmallVector<int, 16> Indices, 2474 SelectionDAG &DAG) { 2475 assert ((Indices.size() % 2) == 0); 2476 int WsIdx = 0; 2477 int WtIdx = ResTy.getVectorNumElements(); 2478 2479 for (unsigned i = 0; i < Indices.size(); i += 2) { 2480 if (Indices[i] != -1 && Indices[i] != WsIdx) 2481 return SDValue(); 2482 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx) 2483 return SDValue(); 2484 WsIdx += 2; 2485 WtIdx += 2; 2486 } 2487 2488 return DAG.getNode(MipsISD::ILVEV, SDLoc(Op), ResTy, Op->getOperand(0), 2489 Op->getOperand(1)); 2490 } 2491 2492 // Lower VECTOR_SHUFFLE into ILVOD (if possible). 2493 // 2494 // ILVOD interleaves the odd elements from each vector. 2495 // 2496 // It is possible to lower into ILVOD when the mask takes the form: 2497 // <1, n+1, 3, n+3, 5, n+5, ...> 2498 // where n is the number of elements in the vector. 2499 // 2500 // When undef's appear in the mask they are treated as if they were whatever 2501 // value is necessary in order to fit the above form. 2502 static SDValue lowerVECTOR_SHUFFLE_ILVOD(SDValue Op, EVT ResTy, 2503 SmallVector<int, 16> Indices, 2504 SelectionDAG &DAG) { 2505 assert ((Indices.size() % 2) == 0); 2506 int WsIdx = 1; 2507 int WtIdx = ResTy.getVectorNumElements() + 1; 2508 2509 for (unsigned i = 0; i < Indices.size(); i += 2) { 2510 if (Indices[i] != -1 && Indices[i] != WsIdx) 2511 return SDValue(); 2512 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx) 2513 return SDValue(); 2514 WsIdx += 2; 2515 WtIdx += 2; 2516 } 2517 2518 return DAG.getNode(MipsISD::ILVOD, SDLoc(Op), ResTy, Op->getOperand(0), 2519 Op->getOperand(1)); 2520 } 2521 2522 // Lower VECTOR_SHUFFLE into ILVL (if possible). 2523 // 2524 // ILVL interleaves consecutive elements from the left half of each vector. 2525 // 2526 // It is possible to lower into ILVL when the mask takes the form: 2527 // <0, n, 1, n+1, 2, n+2, ...> 2528 // where n is the number of elements in the vector. 2529 // 2530 // When undef's appear in the mask they are treated as if they were whatever 2531 // value is necessary in order to fit the above form. 2532 static SDValue lowerVECTOR_SHUFFLE_ILVL(SDValue Op, EVT ResTy, 2533 SmallVector<int, 16> Indices, 2534 SelectionDAG &DAG) { 2535 assert ((Indices.size() % 2) == 0); 2536 int WsIdx = 0; 2537 int WtIdx = ResTy.getVectorNumElements(); 2538 2539 for (unsigned i = 0; i < Indices.size(); i += 2) { 2540 if (Indices[i] != -1 && Indices[i] != WsIdx) 2541 return SDValue(); 2542 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx) 2543 return SDValue(); 2544 WsIdx ++; 2545 WtIdx ++; 2546 } 2547 2548 return DAG.getNode(MipsISD::ILVL, SDLoc(Op), ResTy, Op->getOperand(0), 2549 Op->getOperand(1)); 2550 } 2551 2552 // Lower VECTOR_SHUFFLE into ILVR (if possible). 2553 // 2554 // ILVR interleaves consecutive elements from the right half of each vector. 2555 // 2556 // It is possible to lower into ILVR when the mask takes the form: 2557 // <x, n+x, x+1, n+x+1, x+2, n+x+2, ...> 2558 // where n is the number of elements in the vector and x is half n. 2559 // 2560 // When undef's appear in the mask they are treated as if they were whatever 2561 // value is necessary in order to fit the above form. 2562 static SDValue lowerVECTOR_SHUFFLE_ILVR(SDValue Op, EVT ResTy, 2563 SmallVector<int, 16> Indices, 2564 SelectionDAG &DAG) { 2565 assert ((Indices.size() % 2) == 0); 2566 unsigned NumElts = ResTy.getVectorNumElements(); 2567 int WsIdx = NumElts / 2; 2568 int WtIdx = NumElts + NumElts / 2; 2569 2570 for (unsigned i = 0; i < Indices.size(); i += 2) { 2571 if (Indices[i] != -1 && Indices[i] != WsIdx) 2572 return SDValue(); 2573 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx) 2574 return SDValue(); 2575 WsIdx ++; 2576 WtIdx ++; 2577 } 2578 2579 return DAG.getNode(MipsISD::ILVR, SDLoc(Op), ResTy, Op->getOperand(0), 2580 Op->getOperand(1)); 2581 } 2582 2583 // Lower VECTOR_SHUFFLE into PCKEV (if possible). 2584 // 2585 // PCKEV copies the even elements of each vector into the result vector. 2586 // 2587 // It is possible to lower into PCKEV when the mask takes the form: 2588 // <0, 2, 4, ..., n, n+2, n+4, ...> 2589 // where n is the number of elements in the vector. 2590 // 2591 // When undef's appear in the mask they are treated as if they were whatever 2592 // value is necessary in order to fit the above form. 2593 static SDValue lowerVECTOR_SHUFFLE_PCKEV(SDValue Op, EVT ResTy, 2594 SmallVector<int, 16> Indices, 2595 SelectionDAG &DAG) { 2596 assert ((Indices.size() % 2) == 0); 2597 int Idx = 0; 2598 2599 for (unsigned i = 0; i < Indices.size(); ++i) { 2600 if (Indices[i] != -1 && Indices[i] != Idx) 2601 return SDValue(); 2602 Idx += 2; 2603 } 2604 2605 return DAG.getNode(MipsISD::PCKEV, SDLoc(Op), ResTy, Op->getOperand(0), 2606 Op->getOperand(1)); 2607 } 2608 2609 // Lower VECTOR_SHUFFLE into PCKOD (if possible). 2610 // 2611 // PCKOD copies the odd elements of each vector into the result vector. 2612 // 2613 // It is possible to lower into PCKOD when the mask takes the form: 2614 // <1, 3, 5, ..., n+1, n+3, n+5, ...> 2615 // where n is the number of elements in the vector. 2616 // 2617 // When undef's appear in the mask they are treated as if they were whatever 2618 // value is necessary in order to fit the above form. 2619 static SDValue lowerVECTOR_SHUFFLE_PCKOD(SDValue Op, EVT ResTy, 2620 SmallVector<int, 16> Indices, 2621 SelectionDAG &DAG) { 2622 assert ((Indices.size() % 2) == 0); 2623 int Idx = 1; 2624 2625 for (unsigned i = 0; i < Indices.size(); ++i) { 2626 if (Indices[i] != -1 && Indices[i] != Idx) 2627 return SDValue(); 2628 Idx += 2; 2629 } 2630 2631 return DAG.getNode(MipsISD::PCKOD, SDLoc(Op), ResTy, Op->getOperand(0), 2632 Op->getOperand(1)); 2633 } 2634 2635 // Lower VECTOR_SHUFFLE into VSHF. 2636 // 2637 // This mostly consists of converting the shuffle indices in Indices into a 2638 // BUILD_VECTOR and adding it as an operand to the resulting VSHF. There is 2639 // also code to eliminate unused operands of the VECTOR_SHUFFLE. For example, 2640 // if the type is v8i16 and all the indices are less than 8 then the second 2641 // operand is unused and can be replaced with anything. We choose to replace it 2642 // with the used operand since this reduces the number of instructions overall. 2643 static SDValue lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy, 2644 SmallVector<int, 16> Indices, 2645 SelectionDAG &DAG) { 2646 SmallVector<SDValue, 16> Ops; 2647 SDValue Op0; 2648 SDValue Op1; 2649 EVT MaskVecTy = ResTy.changeVectorElementTypeToInteger(); 2650 EVT MaskEltTy = MaskVecTy.getVectorElementType(); 2651 bool Using1stVec = false; 2652 bool Using2ndVec = false; 2653 SDLoc DL(Op); 2654 int ResTyNumElts = ResTy.getVectorNumElements(); 2655 2656 for (int i = 0; i < ResTyNumElts; ++i) { 2657 // Idx == -1 means UNDEF 2658 int Idx = Indices[i]; 2659 2660 if (0 <= Idx && Idx < ResTyNumElts) 2661 Using1stVec = true; 2662 if (ResTyNumElts <= Idx && Idx < ResTyNumElts * 2) 2663 Using2ndVec = true; 2664 } 2665 2666 for (SmallVector<int, 16>::iterator I = Indices.begin(); I != Indices.end(); 2667 ++I) 2668 Ops.push_back(DAG.getTargetConstant(*I, MaskEltTy)); 2669 2670 SDValue MaskVec = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVecTy, Ops); 2671 2672 if (Using1stVec && Using2ndVec) { 2673 Op0 = Op->getOperand(0); 2674 Op1 = Op->getOperand(1); 2675 } else if (Using1stVec) 2676 Op0 = Op1 = Op->getOperand(0); 2677 else if (Using2ndVec) 2678 Op0 = Op1 = Op->getOperand(1); 2679 else 2680 llvm_unreachable("shuffle vector mask references neither vector operand?"); 2681 2682 // VECTOR_SHUFFLE concatenates the vectors in an vectorwise fashion. 2683 // <0b00, 0b01> + <0b10, 0b11> -> <0b00, 0b01, 0b10, 0b11> 2684 // VSHF concatenates the vectors in a bitwise fashion: 2685 // <0b00, 0b01> + <0b10, 0b11> -> 2686 // 0b0100 + 0b1110 -> 0b01001110 2687 // <0b10, 0b11, 0b00, 0b01> 2688 // We must therefore swap the operands to get the correct result. 2689 return DAG.getNode(MipsISD::VSHF, DL, ResTy, MaskVec, Op1, Op0); 2690 } 2691 2692 // Lower VECTOR_SHUFFLE into one of a number of instructions depending on the 2693 // indices in the shuffle. 2694 SDValue MipsSETargetLowering::lowerVECTOR_SHUFFLE(SDValue Op, 2695 SelectionDAG &DAG) const { 2696 ShuffleVectorSDNode *Node = cast<ShuffleVectorSDNode>(Op); 2697 EVT ResTy = Op->getValueType(0); 2698 2699 if (!ResTy.is128BitVector()) 2700 return SDValue(); 2701 2702 int ResTyNumElts = ResTy.getVectorNumElements(); 2703 SmallVector<int, 16> Indices; 2704 2705 for (int i = 0; i < ResTyNumElts; ++i) 2706 Indices.push_back(Node->getMaskElt(i)); 2707 2708 SDValue Result = lowerVECTOR_SHUFFLE_SHF(Op, ResTy, Indices, DAG); 2709 if (Result.getNode()) 2710 return Result; 2711 Result = lowerVECTOR_SHUFFLE_ILVEV(Op, ResTy, Indices, DAG); 2712 if (Result.getNode()) 2713 return Result; 2714 Result = lowerVECTOR_SHUFFLE_ILVOD(Op, ResTy, Indices, DAG); 2715 if (Result.getNode()) 2716 return Result; 2717 Result = lowerVECTOR_SHUFFLE_ILVL(Op, ResTy, Indices, DAG); 2718 if (Result.getNode()) 2719 return Result; 2720 Result = lowerVECTOR_SHUFFLE_ILVR(Op, ResTy, Indices, DAG); 2721 if (Result.getNode()) 2722 return Result; 2723 Result = lowerVECTOR_SHUFFLE_PCKEV(Op, ResTy, Indices, DAG); 2724 if (Result.getNode()) 2725 return Result; 2726 Result = lowerVECTOR_SHUFFLE_PCKOD(Op, ResTy, Indices, DAG); 2727 if (Result.getNode()) 2728 return Result; 2729 return lowerVECTOR_SHUFFLE_VSHF(Op, ResTy, Indices, DAG); 2730 } 2731 2732 MachineBasicBlock * MipsSETargetLowering:: 2733 emitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{ 2734 // $bb: 2735 // bposge32_pseudo $vr0 2736 // => 2737 // $bb: 2738 // bposge32 $tbb 2739 // $fbb: 2740 // li $vr2, 0 2741 // b $sink 2742 // $tbb: 2743 // li $vr1, 1 2744 // $sink: 2745 // $vr0 = phi($vr2, $fbb, $vr1, $tbb) 2746 2747 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2748 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 2749 const TargetRegisterClass *RC = &Mips::GPR32RegClass; 2750 DebugLoc DL = MI->getDebugLoc(); 2751 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 2752 MachineFunction::iterator It = std::next(MachineFunction::iterator(BB)); 2753 MachineFunction *F = BB->getParent(); 2754 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB); 2755 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB); 2756 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB); 2757 F->insert(It, FBB); 2758 F->insert(It, TBB); 2759 F->insert(It, Sink); 2760 2761 // Transfer the remainder of BB and its successor edges to Sink. 2762 Sink->splice(Sink->begin(), BB, std::next(MachineBasicBlock::iterator(MI)), 2763 BB->end()); 2764 Sink->transferSuccessorsAndUpdatePHIs(BB); 2765 2766 // Add successors. 2767 BB->addSuccessor(FBB); 2768 BB->addSuccessor(TBB); 2769 FBB->addSuccessor(Sink); 2770 TBB->addSuccessor(Sink); 2771 2772 // Insert the real bposge32 instruction to $BB. 2773 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB); 2774 2775 // Fill $FBB. 2776 unsigned VR2 = RegInfo.createVirtualRegister(RC); 2777 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2) 2778 .addReg(Mips::ZERO).addImm(0); 2779 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink); 2780 2781 // Fill $TBB. 2782 unsigned VR1 = RegInfo.createVirtualRegister(RC); 2783 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1) 2784 .addReg(Mips::ZERO).addImm(1); 2785 2786 // Insert phi function to $Sink. 2787 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI), 2788 MI->getOperand(0).getReg()) 2789 .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB); 2790 2791 MI->eraseFromParent(); // The pseudo instruction is gone now. 2792 return Sink; 2793 } 2794 2795 MachineBasicBlock * MipsSETargetLowering:: 2796 emitMSACBranchPseudo(MachineInstr *MI, MachineBasicBlock *BB, 2797 unsigned BranchOp) const{ 2798 // $bb: 2799 // vany_nonzero $rd, $ws 2800 // => 2801 // $bb: 2802 // bnz.b $ws, $tbb 2803 // b $fbb 2804 // $fbb: 2805 // li $rd1, 0 2806 // b $sink 2807 // $tbb: 2808 // li $rd2, 1 2809 // $sink: 2810 // $rd = phi($rd1, $fbb, $rd2, $tbb) 2811 2812 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2813 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 2814 const TargetRegisterClass *RC = &Mips::GPR32RegClass; 2815 DebugLoc DL = MI->getDebugLoc(); 2816 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 2817 MachineFunction::iterator It = std::next(MachineFunction::iterator(BB)); 2818 MachineFunction *F = BB->getParent(); 2819 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB); 2820 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB); 2821 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB); 2822 F->insert(It, FBB); 2823 F->insert(It, TBB); 2824 F->insert(It, Sink); 2825 2826 // Transfer the remainder of BB and its successor edges to Sink. 2827 Sink->splice(Sink->begin(), BB, std::next(MachineBasicBlock::iterator(MI)), 2828 BB->end()); 2829 Sink->transferSuccessorsAndUpdatePHIs(BB); 2830 2831 // Add successors. 2832 BB->addSuccessor(FBB); 2833 BB->addSuccessor(TBB); 2834 FBB->addSuccessor(Sink); 2835 TBB->addSuccessor(Sink); 2836 2837 // Insert the real bnz.b instruction to $BB. 2838 BuildMI(BB, DL, TII->get(BranchOp)) 2839 .addReg(MI->getOperand(1).getReg()) 2840 .addMBB(TBB); 2841 2842 // Fill $FBB. 2843 unsigned RD1 = RegInfo.createVirtualRegister(RC); 2844 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1) 2845 .addReg(Mips::ZERO).addImm(0); 2846 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink); 2847 2848 // Fill $TBB. 2849 unsigned RD2 = RegInfo.createVirtualRegister(RC); 2850 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2) 2851 .addReg(Mips::ZERO).addImm(1); 2852 2853 // Insert phi function to $Sink. 2854 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI), 2855 MI->getOperand(0).getReg()) 2856 .addReg(RD1).addMBB(FBB).addReg(RD2).addMBB(TBB); 2857 2858 MI->eraseFromParent(); // The pseudo instruction is gone now. 2859 return Sink; 2860 } 2861 2862 // Emit the COPY_FW pseudo instruction. 2863 // 2864 // copy_fw_pseudo $fd, $ws, n 2865 // => 2866 // copy_u_w $rt, $ws, $n 2867 // mtc1 $rt, $fd 2868 // 2869 // When n is zero, the equivalent operation can be performed with (potentially) 2870 // zero instructions due to register overlaps. This optimization is never valid 2871 // for lane 1 because it would require FR=0 mode which isn't supported by MSA. 2872 MachineBasicBlock * MipsSETargetLowering:: 2873 emitCOPY_FW(MachineInstr *MI, MachineBasicBlock *BB) const{ 2874 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 2875 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2876 DebugLoc DL = MI->getDebugLoc(); 2877 unsigned Fd = MI->getOperand(0).getReg(); 2878 unsigned Ws = MI->getOperand(1).getReg(); 2879 unsigned Lane = MI->getOperand(2).getImm(); 2880 2881 if (Lane == 0) { 2882 unsigned Wt = Ws; 2883 if (!Subtarget.useOddSPReg()) { 2884 // We must copy to an even-numbered MSA register so that the 2885 // single-precision sub-register is also guaranteed to be even-numbered. 2886 Wt = RegInfo.createVirtualRegister(&Mips::MSA128WEvensRegClass); 2887 2888 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Wt).addReg(Ws); 2889 } 2890 2891 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo); 2892 } else { 2893 unsigned Wt = RegInfo.createVirtualRegister( 2894 Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass : 2895 &Mips::MSA128WEvensRegClass); 2896 2897 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(Lane); 2898 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo); 2899 } 2900 2901 MI->eraseFromParent(); // The pseudo instruction is gone now. 2902 return BB; 2903 } 2904 2905 // Emit the COPY_FD pseudo instruction. 2906 // 2907 // copy_fd_pseudo $fd, $ws, n 2908 // => 2909 // splati.d $wt, $ws, $n 2910 // copy $fd, $wt:sub_64 2911 // 2912 // When n is zero, the equivalent operation can be performed with (potentially) 2913 // zero instructions due to register overlaps. This optimization is always 2914 // valid because FR=1 mode which is the only supported mode in MSA. 2915 MachineBasicBlock * MipsSETargetLowering:: 2916 emitCOPY_FD(MachineInstr *MI, MachineBasicBlock *BB) const{ 2917 assert(Subtarget.isFP64bit()); 2918 2919 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 2920 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2921 unsigned Fd = MI->getOperand(0).getReg(); 2922 unsigned Ws = MI->getOperand(1).getReg(); 2923 unsigned Lane = MI->getOperand(2).getImm() * 2; 2924 DebugLoc DL = MI->getDebugLoc(); 2925 2926 if (Lane == 0) 2927 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_64); 2928 else { 2929 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass); 2930 2931 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wt).addReg(Ws).addImm(1); 2932 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_64); 2933 } 2934 2935 MI->eraseFromParent(); // The pseudo instruction is gone now. 2936 return BB; 2937 } 2938 2939 // Emit the INSERT_FW pseudo instruction. 2940 // 2941 // insert_fw_pseudo $wd, $wd_in, $n, $fs 2942 // => 2943 // subreg_to_reg $wt:sub_lo, $fs 2944 // insve_w $wd[$n], $wd_in, $wt[0] 2945 MachineBasicBlock * 2946 MipsSETargetLowering::emitINSERT_FW(MachineInstr *MI, 2947 MachineBasicBlock *BB) const { 2948 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 2949 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2950 DebugLoc DL = MI->getDebugLoc(); 2951 unsigned Wd = MI->getOperand(0).getReg(); 2952 unsigned Wd_in = MI->getOperand(1).getReg(); 2953 unsigned Lane = MI->getOperand(2).getImm(); 2954 unsigned Fs = MI->getOperand(3).getReg(); 2955 unsigned Wt = RegInfo.createVirtualRegister( 2956 Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass : 2957 &Mips::MSA128WEvensRegClass); 2958 2959 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt) 2960 .addImm(0) 2961 .addReg(Fs) 2962 .addImm(Mips::sub_lo); 2963 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_W), Wd) 2964 .addReg(Wd_in) 2965 .addImm(Lane) 2966 .addReg(Wt) 2967 .addImm(0); 2968 2969 MI->eraseFromParent(); // The pseudo instruction is gone now. 2970 return BB; 2971 } 2972 2973 // Emit the INSERT_FD pseudo instruction. 2974 // 2975 // insert_fd_pseudo $wd, $fs, n 2976 // => 2977 // subreg_to_reg $wt:sub_64, $fs 2978 // insve_d $wd[$n], $wd_in, $wt[0] 2979 MachineBasicBlock * 2980 MipsSETargetLowering::emitINSERT_FD(MachineInstr *MI, 2981 MachineBasicBlock *BB) const { 2982 assert(Subtarget.isFP64bit()); 2983 2984 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 2985 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2986 DebugLoc DL = MI->getDebugLoc(); 2987 unsigned Wd = MI->getOperand(0).getReg(); 2988 unsigned Wd_in = MI->getOperand(1).getReg(); 2989 unsigned Lane = MI->getOperand(2).getImm(); 2990 unsigned Fs = MI->getOperand(3).getReg(); 2991 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass); 2992 2993 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt) 2994 .addImm(0) 2995 .addReg(Fs) 2996 .addImm(Mips::sub_64); 2997 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_D), Wd) 2998 .addReg(Wd_in) 2999 .addImm(Lane) 3000 .addReg(Wt) 3001 .addImm(0); 3002 3003 MI->eraseFromParent(); // The pseudo instruction is gone now. 3004 return BB; 3005 } 3006 3007 // Emit the INSERT_([BHWD]|F[WD])_VIDX pseudo instruction. 3008 // 3009 // For integer: 3010 // (INSERT_([BHWD]|F[WD])_PSEUDO $wd, $wd_in, $n, $rs) 3011 // => 3012 // (SLL $lanetmp1, $lane, <log2size) 3013 // (SLD_B $wdtmp1, $wd_in, $wd_in, $lanetmp1) 3014 // (INSERT_[BHWD], $wdtmp2, $wdtmp1, 0, $rs) 3015 // (NEG $lanetmp2, $lanetmp1) 3016 // (SLD_B $wd, $wdtmp2, $wdtmp2, $lanetmp2) 3017 // 3018 // For floating point: 3019 // (INSERT_([BHWD]|F[WD])_PSEUDO $wd, $wd_in, $n, $fs) 3020 // => 3021 // (SUBREG_TO_REG $wt, $fs, <subreg>) 3022 // (SLL $lanetmp1, $lane, <log2size) 3023 // (SLD_B $wdtmp1, $wd_in, $wd_in, $lanetmp1) 3024 // (INSVE_[WD], $wdtmp2, 0, $wdtmp1, 0) 3025 // (NEG $lanetmp2, $lanetmp1) 3026 // (SLD_B $wd, $wdtmp2, $wdtmp2, $lanetmp2) 3027 MachineBasicBlock * 3028 MipsSETargetLowering::emitINSERT_DF_VIDX(MachineInstr *MI, 3029 MachineBasicBlock *BB, 3030 unsigned EltSizeInBytes, 3031 bool IsFP) const { 3032 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 3033 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 3034 DebugLoc DL = MI->getDebugLoc(); 3035 unsigned Wd = MI->getOperand(0).getReg(); 3036 unsigned SrcVecReg = MI->getOperand(1).getReg(); 3037 unsigned LaneReg = MI->getOperand(2).getReg(); 3038 unsigned SrcValReg = MI->getOperand(3).getReg(); 3039 3040 const TargetRegisterClass *VecRC = nullptr; 3041 const TargetRegisterClass *GPRRC = 3042 Subtarget.isGP64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; 3043 unsigned EltLog2Size; 3044 unsigned InsertOp = 0; 3045 unsigned InsveOp = 0; 3046 switch (EltSizeInBytes) { 3047 default: 3048 llvm_unreachable("Unexpected size"); 3049 case 1: 3050 EltLog2Size = 0; 3051 InsertOp = Mips::INSERT_B; 3052 InsveOp = Mips::INSVE_B; 3053 VecRC = &Mips::MSA128BRegClass; 3054 break; 3055 case 2: 3056 EltLog2Size = 1; 3057 InsertOp = Mips::INSERT_H; 3058 InsveOp = Mips::INSVE_H; 3059 VecRC = &Mips::MSA128HRegClass; 3060 break; 3061 case 4: 3062 EltLog2Size = 2; 3063 InsertOp = Mips::INSERT_W; 3064 InsveOp = Mips::INSVE_W; 3065 VecRC = &Mips::MSA128WRegClass; 3066 break; 3067 case 8: 3068 EltLog2Size = 3; 3069 InsertOp = Mips::INSERT_D; 3070 InsveOp = Mips::INSVE_D; 3071 VecRC = &Mips::MSA128DRegClass; 3072 break; 3073 } 3074 3075 if (IsFP) { 3076 unsigned Wt = RegInfo.createVirtualRegister(VecRC); 3077 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt) 3078 .addImm(0) 3079 .addReg(SrcValReg) 3080 .addImm(EltSizeInBytes == 8 ? Mips::sub_64 : Mips::sub_lo); 3081 SrcValReg = Wt; 3082 } 3083 3084 // Convert the lane index into a byte index 3085 if (EltSizeInBytes != 1) { 3086 unsigned LaneTmp1 = RegInfo.createVirtualRegister(GPRRC); 3087 BuildMI(*BB, MI, DL, TII->get(Mips::SLL), LaneTmp1) 3088 .addReg(LaneReg) 3089 .addImm(EltLog2Size); 3090 LaneReg = LaneTmp1; 3091 } 3092 3093 // Rotate bytes around so that the desired lane is element zero 3094 unsigned WdTmp1 = RegInfo.createVirtualRegister(VecRC); 3095 BuildMI(*BB, MI, DL, TII->get(Mips::SLD_B), WdTmp1) 3096 .addReg(SrcVecReg) 3097 .addReg(SrcVecReg) 3098 .addReg(LaneReg); 3099 3100 unsigned WdTmp2 = RegInfo.createVirtualRegister(VecRC); 3101 if (IsFP) { 3102 // Use insve.df to insert to element zero 3103 BuildMI(*BB, MI, DL, TII->get(InsveOp), WdTmp2) 3104 .addReg(WdTmp1) 3105 .addImm(0) 3106 .addReg(SrcValReg) 3107 .addImm(0); 3108 } else { 3109 // Use insert.df to insert to element zero 3110 BuildMI(*BB, MI, DL, TII->get(InsertOp), WdTmp2) 3111 .addReg(WdTmp1) 3112 .addReg(SrcValReg) 3113 .addImm(0); 3114 } 3115 3116 // Rotate elements the rest of the way for a full rotation. 3117 // sld.df inteprets $rt modulo the number of columns so we only need to negate 3118 // the lane index to do this. 3119 unsigned LaneTmp2 = RegInfo.createVirtualRegister(GPRRC); 3120 BuildMI(*BB, MI, DL, TII->get(Mips::SUB), LaneTmp2) 3121 .addReg(Mips::ZERO) 3122 .addReg(LaneReg); 3123 BuildMI(*BB, MI, DL, TII->get(Mips::SLD_B), Wd) 3124 .addReg(WdTmp2) 3125 .addReg(WdTmp2) 3126 .addReg(LaneTmp2); 3127 3128 MI->eraseFromParent(); // The pseudo instruction is gone now. 3129 return BB; 3130 } 3131 3132 // Emit the FILL_FW pseudo instruction. 3133 // 3134 // fill_fw_pseudo $wd, $fs 3135 // => 3136 // implicit_def $wt1 3137 // insert_subreg $wt2:subreg_lo, $wt1, $fs 3138 // splati.w $wd, $wt2[0] 3139 MachineBasicBlock * 3140 MipsSETargetLowering::emitFILL_FW(MachineInstr *MI, 3141 MachineBasicBlock *BB) const { 3142 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 3143 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 3144 DebugLoc DL = MI->getDebugLoc(); 3145 unsigned Wd = MI->getOperand(0).getReg(); 3146 unsigned Fs = MI->getOperand(1).getReg(); 3147 unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass); 3148 unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass); 3149 3150 BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1); 3151 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2) 3152 .addReg(Wt1) 3153 .addReg(Fs) 3154 .addImm(Mips::sub_lo); 3155 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wd).addReg(Wt2).addImm(0); 3156 3157 MI->eraseFromParent(); // The pseudo instruction is gone now. 3158 return BB; 3159 } 3160 3161 // Emit the FILL_FD pseudo instruction. 3162 // 3163 // fill_fd_pseudo $wd, $fs 3164 // => 3165 // implicit_def $wt1 3166 // insert_subreg $wt2:subreg_64, $wt1, $fs 3167 // splati.d $wd, $wt2[0] 3168 MachineBasicBlock * 3169 MipsSETargetLowering::emitFILL_FD(MachineInstr *MI, 3170 MachineBasicBlock *BB) const { 3171 assert(Subtarget.isFP64bit()); 3172 3173 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 3174 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 3175 DebugLoc DL = MI->getDebugLoc(); 3176 unsigned Wd = MI->getOperand(0).getReg(); 3177 unsigned Fs = MI->getOperand(1).getReg(); 3178 unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass); 3179 unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass); 3180 3181 BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1); 3182 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2) 3183 .addReg(Wt1) 3184 .addReg(Fs) 3185 .addImm(Mips::sub_64); 3186 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wd).addReg(Wt2).addImm(0); 3187 3188 MI->eraseFromParent(); // The pseudo instruction is gone now. 3189 return BB; 3190 } 3191 3192 // Emit the FEXP2_W_1 pseudo instructions. 3193 // 3194 // fexp2_w_1_pseudo $wd, $wt 3195 // => 3196 // ldi.w $ws, 1 3197 // fexp2.w $wd, $ws, $wt 3198 MachineBasicBlock * 3199 MipsSETargetLowering::emitFEXP2_W_1(MachineInstr *MI, 3200 MachineBasicBlock *BB) const { 3201 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 3202 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 3203 const TargetRegisterClass *RC = &Mips::MSA128WRegClass; 3204 unsigned Ws1 = RegInfo.createVirtualRegister(RC); 3205 unsigned Ws2 = RegInfo.createVirtualRegister(RC); 3206 DebugLoc DL = MI->getDebugLoc(); 3207 3208 // Splat 1.0 into a vector 3209 BuildMI(*BB, MI, DL, TII->get(Mips::LDI_W), Ws1).addImm(1); 3210 BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_W), Ws2).addReg(Ws1); 3211 3212 // Emit 1.0 * fexp2(Wt) 3213 BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_W), MI->getOperand(0).getReg()) 3214 .addReg(Ws2) 3215 .addReg(MI->getOperand(1).getReg()); 3216 3217 MI->eraseFromParent(); // The pseudo instruction is gone now. 3218 return BB; 3219 } 3220 3221 // Emit the FEXP2_D_1 pseudo instructions. 3222 // 3223 // fexp2_d_1_pseudo $wd, $wt 3224 // => 3225 // ldi.d $ws, 1 3226 // fexp2.d $wd, $ws, $wt 3227 MachineBasicBlock * 3228 MipsSETargetLowering::emitFEXP2_D_1(MachineInstr *MI, 3229 MachineBasicBlock *BB) const { 3230 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); 3231 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 3232 const TargetRegisterClass *RC = &Mips::MSA128DRegClass; 3233 unsigned Ws1 = RegInfo.createVirtualRegister(RC); 3234 unsigned Ws2 = RegInfo.createVirtualRegister(RC); 3235 DebugLoc DL = MI->getDebugLoc(); 3236 3237 // Splat 1.0 into a vector 3238 BuildMI(*BB, MI, DL, TII->get(Mips::LDI_D), Ws1).addImm(1); 3239 BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_D), Ws2).addReg(Ws1); 3240 3241 // Emit 1.0 * fexp2(Wt) 3242 BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_D), MI->getOperand(0).getReg()) 3243 .addReg(Ws2) 3244 .addReg(MI->getOperand(1).getReg()); 3245 3246 MI->eraseFromParent(); // The pseudo instruction is gone now. 3247 return BB; 3248 } 3249