1 //===-- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ---===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This implements the TargetLoweringBase class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/Target/TargetLowering.h" 15 #include "llvm/ADT/BitVector.h" 16 #include "llvm/ADT/STLExtras.h" 17 #include "llvm/ADT/Triple.h" 18 #include "llvm/CodeGen/Analysis.h" 19 #include "llvm/CodeGen/MachineFrameInfo.h" 20 #include "llvm/CodeGen/MachineFunction.h" 21 #include "llvm/CodeGen/MachineInstrBuilder.h" 22 #include "llvm/CodeGen/MachineJumpTableInfo.h" 23 #include "llvm/CodeGen/StackMaps.h" 24 #include "llvm/IR/DataLayout.h" 25 #include "llvm/IR/DerivedTypes.h" 26 #include "llvm/IR/GlobalVariable.h" 27 #include "llvm/IR/Mangler.h" 28 #include "llvm/MC/MCAsmInfo.h" 29 #include "llvm/MC/MCContext.h" 30 #include "llvm/MC/MCExpr.h" 31 #include "llvm/Support/CommandLine.h" 32 #include "llvm/Support/ErrorHandling.h" 33 #include "llvm/Support/MathExtras.h" 34 #include "llvm/Target/TargetLoweringObjectFile.h" 35 #include "llvm/Target/TargetMachine.h" 36 #include "llvm/Target/TargetRegisterInfo.h" 37 #include "llvm/Target/TargetSubtargetInfo.h" 38 #include <cctype> 39 using namespace llvm; 40 41 /// InitLibcallNames - Set default libcall names. 42 /// 43 static void InitLibcallNames(const char **Names, const Triple &TT) { 44 Names[RTLIB::SHL_I16] = "__ashlhi3"; 45 Names[RTLIB::SHL_I32] = "__ashlsi3"; 46 Names[RTLIB::SHL_I64] = "__ashldi3"; 47 Names[RTLIB::SHL_I128] = "__ashlti3"; 48 Names[RTLIB::SRL_I16] = "__lshrhi3"; 49 Names[RTLIB::SRL_I32] = "__lshrsi3"; 50 Names[RTLIB::SRL_I64] = "__lshrdi3"; 51 Names[RTLIB::SRL_I128] = "__lshrti3"; 52 Names[RTLIB::SRA_I16] = "__ashrhi3"; 53 Names[RTLIB::SRA_I32] = "__ashrsi3"; 54 Names[RTLIB::SRA_I64] = "__ashrdi3"; 55 Names[RTLIB::SRA_I128] = "__ashrti3"; 56 Names[RTLIB::MUL_I8] = "__mulqi3"; 57 Names[RTLIB::MUL_I16] = "__mulhi3"; 58 Names[RTLIB::MUL_I32] = "__mulsi3"; 59 Names[RTLIB::MUL_I64] = "__muldi3"; 60 Names[RTLIB::MUL_I128] = "__multi3"; 61 Names[RTLIB::MULO_I32] = "__mulosi4"; 62 Names[RTLIB::MULO_I64] = "__mulodi4"; 63 Names[RTLIB::MULO_I128] = "__muloti4"; 64 Names[RTLIB::SDIV_I8] = "__divqi3"; 65 Names[RTLIB::SDIV_I16] = "__divhi3"; 66 Names[RTLIB::SDIV_I32] = "__divsi3"; 67 Names[RTLIB::SDIV_I64] = "__divdi3"; 68 Names[RTLIB::SDIV_I128] = "__divti3"; 69 Names[RTLIB::UDIV_I8] = "__udivqi3"; 70 Names[RTLIB::UDIV_I16] = "__udivhi3"; 71 Names[RTLIB::UDIV_I32] = "__udivsi3"; 72 Names[RTLIB::UDIV_I64] = "__udivdi3"; 73 Names[RTLIB::UDIV_I128] = "__udivti3"; 74 Names[RTLIB::SREM_I8] = "__modqi3"; 75 Names[RTLIB::SREM_I16] = "__modhi3"; 76 Names[RTLIB::SREM_I32] = "__modsi3"; 77 Names[RTLIB::SREM_I64] = "__moddi3"; 78 Names[RTLIB::SREM_I128] = "__modti3"; 79 Names[RTLIB::UREM_I8] = "__umodqi3"; 80 Names[RTLIB::UREM_I16] = "__umodhi3"; 81 Names[RTLIB::UREM_I32] = "__umodsi3"; 82 Names[RTLIB::UREM_I64] = "__umoddi3"; 83 Names[RTLIB::UREM_I128] = "__umodti3"; 84 85 // These are generally not available. 86 Names[RTLIB::SDIVREM_I8] = nullptr; 87 Names[RTLIB::SDIVREM_I16] = nullptr; 88 Names[RTLIB::SDIVREM_I32] = nullptr; 89 Names[RTLIB::SDIVREM_I64] = nullptr; 90 Names[RTLIB::SDIVREM_I128] = nullptr; 91 Names[RTLIB::UDIVREM_I8] = nullptr; 92 Names[RTLIB::UDIVREM_I16] = nullptr; 93 Names[RTLIB::UDIVREM_I32] = nullptr; 94 Names[RTLIB::UDIVREM_I64] = nullptr; 95 Names[RTLIB::UDIVREM_I128] = nullptr; 96 97 Names[RTLIB::NEG_I32] = "__negsi2"; 98 Names[RTLIB::NEG_I64] = "__negdi2"; 99 Names[RTLIB::ADD_F32] = "__addsf3"; 100 Names[RTLIB::ADD_F64] = "__adddf3"; 101 Names[RTLIB::ADD_F80] = "__addxf3"; 102 Names[RTLIB::ADD_F128] = "__addtf3"; 103 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 104 Names[RTLIB::SUB_F32] = "__subsf3"; 105 Names[RTLIB::SUB_F64] = "__subdf3"; 106 Names[RTLIB::SUB_F80] = "__subxf3"; 107 Names[RTLIB::SUB_F128] = "__subtf3"; 108 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 109 Names[RTLIB::MUL_F32] = "__mulsf3"; 110 Names[RTLIB::MUL_F64] = "__muldf3"; 111 Names[RTLIB::MUL_F80] = "__mulxf3"; 112 Names[RTLIB::MUL_F128] = "__multf3"; 113 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 114 Names[RTLIB::DIV_F32] = "__divsf3"; 115 Names[RTLIB::DIV_F64] = "__divdf3"; 116 Names[RTLIB::DIV_F80] = "__divxf3"; 117 Names[RTLIB::DIV_F128] = "__divtf3"; 118 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 119 Names[RTLIB::REM_F32] = "fmodf"; 120 Names[RTLIB::REM_F64] = "fmod"; 121 Names[RTLIB::REM_F80] = "fmodl"; 122 Names[RTLIB::REM_F128] = "fmodl"; 123 Names[RTLIB::REM_PPCF128] = "fmodl"; 124 Names[RTLIB::FMA_F32] = "fmaf"; 125 Names[RTLIB::FMA_F64] = "fma"; 126 Names[RTLIB::FMA_F80] = "fmal"; 127 Names[RTLIB::FMA_F128] = "fmal"; 128 Names[RTLIB::FMA_PPCF128] = "fmal"; 129 Names[RTLIB::POWI_F32] = "__powisf2"; 130 Names[RTLIB::POWI_F64] = "__powidf2"; 131 Names[RTLIB::POWI_F80] = "__powixf2"; 132 Names[RTLIB::POWI_F128] = "__powitf2"; 133 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 134 Names[RTLIB::SQRT_F32] = "sqrtf"; 135 Names[RTLIB::SQRT_F64] = "sqrt"; 136 Names[RTLIB::SQRT_F80] = "sqrtl"; 137 Names[RTLIB::SQRT_F128] = "sqrtl"; 138 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 139 Names[RTLIB::LOG_F32] = "logf"; 140 Names[RTLIB::LOG_F64] = "log"; 141 Names[RTLIB::LOG_F80] = "logl"; 142 Names[RTLIB::LOG_F128] = "logl"; 143 Names[RTLIB::LOG_PPCF128] = "logl"; 144 Names[RTLIB::LOG2_F32] = "log2f"; 145 Names[RTLIB::LOG2_F64] = "log2"; 146 Names[RTLIB::LOG2_F80] = "log2l"; 147 Names[RTLIB::LOG2_F128] = "log2l"; 148 Names[RTLIB::LOG2_PPCF128] = "log2l"; 149 Names[RTLIB::LOG10_F32] = "log10f"; 150 Names[RTLIB::LOG10_F64] = "log10"; 151 Names[RTLIB::LOG10_F80] = "log10l"; 152 Names[RTLIB::LOG10_F128] = "log10l"; 153 Names[RTLIB::LOG10_PPCF128] = "log10l"; 154 Names[RTLIB::EXP_F32] = "expf"; 155 Names[RTLIB::EXP_F64] = "exp"; 156 Names[RTLIB::EXP_F80] = "expl"; 157 Names[RTLIB::EXP_F128] = "expl"; 158 Names[RTLIB::EXP_PPCF128] = "expl"; 159 Names[RTLIB::EXP2_F32] = "exp2f"; 160 Names[RTLIB::EXP2_F64] = "exp2"; 161 Names[RTLIB::EXP2_F80] = "exp2l"; 162 Names[RTLIB::EXP2_F128] = "exp2l"; 163 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 164 Names[RTLIB::SIN_F32] = "sinf"; 165 Names[RTLIB::SIN_F64] = "sin"; 166 Names[RTLIB::SIN_F80] = "sinl"; 167 Names[RTLIB::SIN_F128] = "sinl"; 168 Names[RTLIB::SIN_PPCF128] = "sinl"; 169 Names[RTLIB::COS_F32] = "cosf"; 170 Names[RTLIB::COS_F64] = "cos"; 171 Names[RTLIB::COS_F80] = "cosl"; 172 Names[RTLIB::COS_F128] = "cosl"; 173 Names[RTLIB::COS_PPCF128] = "cosl"; 174 Names[RTLIB::POW_F32] = "powf"; 175 Names[RTLIB::POW_F64] = "pow"; 176 Names[RTLIB::POW_F80] = "powl"; 177 Names[RTLIB::POW_F128] = "powl"; 178 Names[RTLIB::POW_PPCF128] = "powl"; 179 Names[RTLIB::CEIL_F32] = "ceilf"; 180 Names[RTLIB::CEIL_F64] = "ceil"; 181 Names[RTLIB::CEIL_F80] = "ceill"; 182 Names[RTLIB::CEIL_F128] = "ceill"; 183 Names[RTLIB::CEIL_PPCF128] = "ceill"; 184 Names[RTLIB::TRUNC_F32] = "truncf"; 185 Names[RTLIB::TRUNC_F64] = "trunc"; 186 Names[RTLIB::TRUNC_F80] = "truncl"; 187 Names[RTLIB::TRUNC_F128] = "truncl"; 188 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 189 Names[RTLIB::RINT_F32] = "rintf"; 190 Names[RTLIB::RINT_F64] = "rint"; 191 Names[RTLIB::RINT_F80] = "rintl"; 192 Names[RTLIB::RINT_F128] = "rintl"; 193 Names[RTLIB::RINT_PPCF128] = "rintl"; 194 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 195 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 196 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 197 Names[RTLIB::NEARBYINT_F128] = "nearbyintl"; 198 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 199 Names[RTLIB::ROUND_F32] = "roundf"; 200 Names[RTLIB::ROUND_F64] = "round"; 201 Names[RTLIB::ROUND_F80] = "roundl"; 202 Names[RTLIB::ROUND_F128] = "roundl"; 203 Names[RTLIB::ROUND_PPCF128] = "roundl"; 204 Names[RTLIB::FLOOR_F32] = "floorf"; 205 Names[RTLIB::FLOOR_F64] = "floor"; 206 Names[RTLIB::FLOOR_F80] = "floorl"; 207 Names[RTLIB::FLOOR_F128] = "floorl"; 208 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 209 Names[RTLIB::FMIN_F32] = "fminf"; 210 Names[RTLIB::FMIN_F64] = "fmin"; 211 Names[RTLIB::FMIN_F80] = "fminl"; 212 Names[RTLIB::FMIN_F128] = "fminl"; 213 Names[RTLIB::FMIN_PPCF128] = "fminl"; 214 Names[RTLIB::FMAX_F32] = "fmaxf"; 215 Names[RTLIB::FMAX_F64] = "fmax"; 216 Names[RTLIB::FMAX_F80] = "fmaxl"; 217 Names[RTLIB::FMAX_F128] = "fmaxl"; 218 Names[RTLIB::FMAX_PPCF128] = "fmaxl"; 219 Names[RTLIB::ROUND_F32] = "roundf"; 220 Names[RTLIB::ROUND_F64] = "round"; 221 Names[RTLIB::ROUND_F80] = "roundl"; 222 Names[RTLIB::ROUND_F128] = "roundl"; 223 Names[RTLIB::ROUND_PPCF128] = "roundl"; 224 Names[RTLIB::COPYSIGN_F32] = "copysignf"; 225 Names[RTLIB::COPYSIGN_F64] = "copysign"; 226 Names[RTLIB::COPYSIGN_F80] = "copysignl"; 227 Names[RTLIB::COPYSIGN_F128] = "copysignl"; 228 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl"; 229 Names[RTLIB::FPEXT_F64_F128] = "__extenddftf2"; 230 Names[RTLIB::FPEXT_F32_F128] = "__extendsftf2"; 231 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 232 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee"; 233 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee"; 234 Names[RTLIB::FPROUND_F64_F16] = "__truncdfhf2"; 235 Names[RTLIB::FPROUND_F80_F16] = "__truncxfhf2"; 236 Names[RTLIB::FPROUND_F128_F16] = "__trunctfhf2"; 237 Names[RTLIB::FPROUND_PPCF128_F16] = "__trunctfhf2"; 238 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 239 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 240 Names[RTLIB::FPROUND_F128_F32] = "__trunctfsf2"; 241 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2"; 242 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 243 Names[RTLIB::FPROUND_F128_F64] = "__trunctfdf2"; 244 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2"; 245 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi"; 246 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi"; 247 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 248 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 249 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 250 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi"; 251 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi"; 252 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 253 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 254 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 255 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 256 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 257 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 258 Names[RTLIB::FPTOSINT_F128_I32] = "__fixtfsi"; 259 Names[RTLIB::FPTOSINT_F128_I64] = "__fixtfdi"; 260 Names[RTLIB::FPTOSINT_F128_I128] = "__fixtfti"; 261 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi"; 262 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 263 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 264 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi"; 265 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi"; 266 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 267 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 268 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 269 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi"; 270 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi"; 271 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 272 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 273 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 274 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 275 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 276 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 277 Names[RTLIB::FPTOUINT_F128_I32] = "__fixunstfsi"; 278 Names[RTLIB::FPTOUINT_F128_I64] = "__fixunstfdi"; 279 Names[RTLIB::FPTOUINT_F128_I128] = "__fixunstfti"; 280 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 281 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 282 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 283 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 284 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 285 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 286 Names[RTLIB::SINTTOFP_I32_F128] = "__floatsitf"; 287 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf"; 288 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 289 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 290 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 291 Names[RTLIB::SINTTOFP_I64_F128] = "__floatditf"; 292 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 293 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 294 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 295 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 296 Names[RTLIB::SINTTOFP_I128_F128] = "__floattitf"; 297 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 298 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 299 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 300 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 301 Names[RTLIB::UINTTOFP_I32_F128] = "__floatunsitf"; 302 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf"; 303 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 304 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 305 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 306 Names[RTLIB::UINTTOFP_I64_F128] = "__floatunditf"; 307 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 308 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 309 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 310 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 311 Names[RTLIB::UINTTOFP_I128_F128] = "__floatuntitf"; 312 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 313 Names[RTLIB::OEQ_F32] = "__eqsf2"; 314 Names[RTLIB::OEQ_F64] = "__eqdf2"; 315 Names[RTLIB::OEQ_F128] = "__eqtf2"; 316 Names[RTLIB::UNE_F32] = "__nesf2"; 317 Names[RTLIB::UNE_F64] = "__nedf2"; 318 Names[RTLIB::UNE_F128] = "__netf2"; 319 Names[RTLIB::OGE_F32] = "__gesf2"; 320 Names[RTLIB::OGE_F64] = "__gedf2"; 321 Names[RTLIB::OGE_F128] = "__getf2"; 322 Names[RTLIB::OLT_F32] = "__ltsf2"; 323 Names[RTLIB::OLT_F64] = "__ltdf2"; 324 Names[RTLIB::OLT_F128] = "__lttf2"; 325 Names[RTLIB::OLE_F32] = "__lesf2"; 326 Names[RTLIB::OLE_F64] = "__ledf2"; 327 Names[RTLIB::OLE_F128] = "__letf2"; 328 Names[RTLIB::OGT_F32] = "__gtsf2"; 329 Names[RTLIB::OGT_F64] = "__gtdf2"; 330 Names[RTLIB::OGT_F128] = "__gttf2"; 331 Names[RTLIB::UO_F32] = "__unordsf2"; 332 Names[RTLIB::UO_F64] = "__unorddf2"; 333 Names[RTLIB::UO_F128] = "__unordtf2"; 334 Names[RTLIB::O_F32] = "__unordsf2"; 335 Names[RTLIB::O_F64] = "__unorddf2"; 336 Names[RTLIB::O_F128] = "__unordtf2"; 337 Names[RTLIB::MEMCPY] = "memcpy"; 338 Names[RTLIB::MEMMOVE] = "memmove"; 339 Names[RTLIB::MEMSET] = "memset"; 340 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume"; 341 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1"; 342 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2"; 343 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4"; 344 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8"; 345 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16] = "__sync_val_compare_and_swap_16"; 346 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1"; 347 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2"; 348 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4"; 349 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8"; 350 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_16] = "__sync_lock_test_and_set_16"; 351 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1"; 352 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2"; 353 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4"; 354 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8"; 355 Names[RTLIB::SYNC_FETCH_AND_ADD_16] = "__sync_fetch_and_add_16"; 356 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1"; 357 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2"; 358 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4"; 359 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8"; 360 Names[RTLIB::SYNC_FETCH_AND_SUB_16] = "__sync_fetch_and_sub_16"; 361 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1"; 362 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2"; 363 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4"; 364 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8"; 365 Names[RTLIB::SYNC_FETCH_AND_AND_16] = "__sync_fetch_and_and_16"; 366 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1"; 367 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2"; 368 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4"; 369 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8"; 370 Names[RTLIB::SYNC_FETCH_AND_OR_16] = "__sync_fetch_and_or_16"; 371 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1"; 372 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2"; 373 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4"; 374 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8"; 375 Names[RTLIB::SYNC_FETCH_AND_XOR_16] = "__sync_fetch_and_xor_16"; 376 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1"; 377 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2"; 378 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4"; 379 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8"; 380 Names[RTLIB::SYNC_FETCH_AND_NAND_16] = "__sync_fetch_and_nand_16"; 381 Names[RTLIB::SYNC_FETCH_AND_MAX_1] = "__sync_fetch_and_max_1"; 382 Names[RTLIB::SYNC_FETCH_AND_MAX_2] = "__sync_fetch_and_max_2"; 383 Names[RTLIB::SYNC_FETCH_AND_MAX_4] = "__sync_fetch_and_max_4"; 384 Names[RTLIB::SYNC_FETCH_AND_MAX_8] = "__sync_fetch_and_max_8"; 385 Names[RTLIB::SYNC_FETCH_AND_MAX_16] = "__sync_fetch_and_max_16"; 386 Names[RTLIB::SYNC_FETCH_AND_UMAX_1] = "__sync_fetch_and_umax_1"; 387 Names[RTLIB::SYNC_FETCH_AND_UMAX_2] = "__sync_fetch_and_umax_2"; 388 Names[RTLIB::SYNC_FETCH_AND_UMAX_4] = "__sync_fetch_and_umax_4"; 389 Names[RTLIB::SYNC_FETCH_AND_UMAX_8] = "__sync_fetch_and_umax_8"; 390 Names[RTLIB::SYNC_FETCH_AND_UMAX_16] = "__sync_fetch_and_umax_16"; 391 Names[RTLIB::SYNC_FETCH_AND_MIN_1] = "__sync_fetch_and_min_1"; 392 Names[RTLIB::SYNC_FETCH_AND_MIN_2] = "__sync_fetch_and_min_2"; 393 Names[RTLIB::SYNC_FETCH_AND_MIN_4] = "__sync_fetch_and_min_4"; 394 Names[RTLIB::SYNC_FETCH_AND_MIN_8] = "__sync_fetch_and_min_8"; 395 Names[RTLIB::SYNC_FETCH_AND_MIN_16] = "__sync_fetch_and_min_16"; 396 Names[RTLIB::SYNC_FETCH_AND_UMIN_1] = "__sync_fetch_and_umin_1"; 397 Names[RTLIB::SYNC_FETCH_AND_UMIN_2] = "__sync_fetch_and_umin_2"; 398 Names[RTLIB::SYNC_FETCH_AND_UMIN_4] = "__sync_fetch_and_umin_4"; 399 Names[RTLIB::SYNC_FETCH_AND_UMIN_8] = "__sync_fetch_and_umin_8"; 400 Names[RTLIB::SYNC_FETCH_AND_UMIN_16] = "__sync_fetch_and_umin_16"; 401 402 if (TT.getEnvironment() == Triple::GNU) { 403 Names[RTLIB::SINCOS_F32] = "sincosf"; 404 Names[RTLIB::SINCOS_F64] = "sincos"; 405 Names[RTLIB::SINCOS_F80] = "sincosl"; 406 Names[RTLIB::SINCOS_F128] = "sincosl"; 407 Names[RTLIB::SINCOS_PPCF128] = "sincosl"; 408 } else { 409 // These are generally not available. 410 Names[RTLIB::SINCOS_F32] = nullptr; 411 Names[RTLIB::SINCOS_F64] = nullptr; 412 Names[RTLIB::SINCOS_F80] = nullptr; 413 Names[RTLIB::SINCOS_F128] = nullptr; 414 Names[RTLIB::SINCOS_PPCF128] = nullptr; 415 } 416 417 if (!TT.isOSOpenBSD()) { 418 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = "__stack_chk_fail"; 419 } else { 420 // These are generally not available. 421 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = nullptr; 422 } 423 } 424 425 /// InitLibcallCallingConvs - Set default libcall CallingConvs. 426 /// 427 static void InitLibcallCallingConvs(CallingConv::ID *CCs) { 428 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) { 429 CCs[i] = CallingConv::C; 430 } 431 } 432 433 /// getFPEXT - Return the FPEXT_*_* value for the given types, or 434 /// UNKNOWN_LIBCALL if there is none. 435 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { 436 if (OpVT == MVT::f16) { 437 if (RetVT == MVT::f32) 438 return FPEXT_F16_F32; 439 } else if (OpVT == MVT::f32) { 440 if (RetVT == MVT::f64) 441 return FPEXT_F32_F64; 442 if (RetVT == MVT::f128) 443 return FPEXT_F32_F128; 444 } else if (OpVT == MVT::f64) { 445 if (RetVT == MVT::f128) 446 return FPEXT_F64_F128; 447 } 448 449 return UNKNOWN_LIBCALL; 450 } 451 452 /// getFPROUND - Return the FPROUND_*_* value for the given types, or 453 /// UNKNOWN_LIBCALL if there is none. 454 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { 455 if (RetVT == MVT::f16) { 456 if (OpVT == MVT::f32) 457 return FPROUND_F32_F16; 458 if (OpVT == MVT::f64) 459 return FPROUND_F64_F16; 460 if (OpVT == MVT::f80) 461 return FPROUND_F80_F16; 462 if (OpVT == MVT::f128) 463 return FPROUND_F128_F16; 464 if (OpVT == MVT::ppcf128) 465 return FPROUND_PPCF128_F16; 466 } else if (RetVT == MVT::f32) { 467 if (OpVT == MVT::f64) 468 return FPROUND_F64_F32; 469 if (OpVT == MVT::f80) 470 return FPROUND_F80_F32; 471 if (OpVT == MVT::f128) 472 return FPROUND_F128_F32; 473 if (OpVT == MVT::ppcf128) 474 return FPROUND_PPCF128_F32; 475 } else if (RetVT == MVT::f64) { 476 if (OpVT == MVT::f80) 477 return FPROUND_F80_F64; 478 if (OpVT == MVT::f128) 479 return FPROUND_F128_F64; 480 if (OpVT == MVT::ppcf128) 481 return FPROUND_PPCF128_F64; 482 } 483 484 return UNKNOWN_LIBCALL; 485 } 486 487 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 488 /// UNKNOWN_LIBCALL if there is none. 489 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { 490 if (OpVT == MVT::f32) { 491 if (RetVT == MVT::i8) 492 return FPTOSINT_F32_I8; 493 if (RetVT == MVT::i16) 494 return FPTOSINT_F32_I16; 495 if (RetVT == MVT::i32) 496 return FPTOSINT_F32_I32; 497 if (RetVT == MVT::i64) 498 return FPTOSINT_F32_I64; 499 if (RetVT == MVT::i128) 500 return FPTOSINT_F32_I128; 501 } else if (OpVT == MVT::f64) { 502 if (RetVT == MVT::i8) 503 return FPTOSINT_F64_I8; 504 if (RetVT == MVT::i16) 505 return FPTOSINT_F64_I16; 506 if (RetVT == MVT::i32) 507 return FPTOSINT_F64_I32; 508 if (RetVT == MVT::i64) 509 return FPTOSINT_F64_I64; 510 if (RetVT == MVT::i128) 511 return FPTOSINT_F64_I128; 512 } else if (OpVT == MVT::f80) { 513 if (RetVT == MVT::i32) 514 return FPTOSINT_F80_I32; 515 if (RetVT == MVT::i64) 516 return FPTOSINT_F80_I64; 517 if (RetVT == MVT::i128) 518 return FPTOSINT_F80_I128; 519 } else if (OpVT == MVT::f128) { 520 if (RetVT == MVT::i32) 521 return FPTOSINT_F128_I32; 522 if (RetVT == MVT::i64) 523 return FPTOSINT_F128_I64; 524 if (RetVT == MVT::i128) 525 return FPTOSINT_F128_I128; 526 } else if (OpVT == MVT::ppcf128) { 527 if (RetVT == MVT::i32) 528 return FPTOSINT_PPCF128_I32; 529 if (RetVT == MVT::i64) 530 return FPTOSINT_PPCF128_I64; 531 if (RetVT == MVT::i128) 532 return FPTOSINT_PPCF128_I128; 533 } 534 return UNKNOWN_LIBCALL; 535 } 536 537 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 538 /// UNKNOWN_LIBCALL if there is none. 539 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) { 540 if (OpVT == MVT::f32) { 541 if (RetVT == MVT::i8) 542 return FPTOUINT_F32_I8; 543 if (RetVT == MVT::i16) 544 return FPTOUINT_F32_I16; 545 if (RetVT == MVT::i32) 546 return FPTOUINT_F32_I32; 547 if (RetVT == MVT::i64) 548 return FPTOUINT_F32_I64; 549 if (RetVT == MVT::i128) 550 return FPTOUINT_F32_I128; 551 } else if (OpVT == MVT::f64) { 552 if (RetVT == MVT::i8) 553 return FPTOUINT_F64_I8; 554 if (RetVT == MVT::i16) 555 return FPTOUINT_F64_I16; 556 if (RetVT == MVT::i32) 557 return FPTOUINT_F64_I32; 558 if (RetVT == MVT::i64) 559 return FPTOUINT_F64_I64; 560 if (RetVT == MVT::i128) 561 return FPTOUINT_F64_I128; 562 } else if (OpVT == MVT::f80) { 563 if (RetVT == MVT::i32) 564 return FPTOUINT_F80_I32; 565 if (RetVT == MVT::i64) 566 return FPTOUINT_F80_I64; 567 if (RetVT == MVT::i128) 568 return FPTOUINT_F80_I128; 569 } else if (OpVT == MVT::f128) { 570 if (RetVT == MVT::i32) 571 return FPTOUINT_F128_I32; 572 if (RetVT == MVT::i64) 573 return FPTOUINT_F128_I64; 574 if (RetVT == MVT::i128) 575 return FPTOUINT_F128_I128; 576 } else if (OpVT == MVT::ppcf128) { 577 if (RetVT == MVT::i32) 578 return FPTOUINT_PPCF128_I32; 579 if (RetVT == MVT::i64) 580 return FPTOUINT_PPCF128_I64; 581 if (RetVT == MVT::i128) 582 return FPTOUINT_PPCF128_I128; 583 } 584 return UNKNOWN_LIBCALL; 585 } 586 587 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 588 /// UNKNOWN_LIBCALL if there is none. 589 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) { 590 if (OpVT == MVT::i32) { 591 if (RetVT == MVT::f32) 592 return SINTTOFP_I32_F32; 593 if (RetVT == MVT::f64) 594 return SINTTOFP_I32_F64; 595 if (RetVT == MVT::f80) 596 return SINTTOFP_I32_F80; 597 if (RetVT == MVT::f128) 598 return SINTTOFP_I32_F128; 599 if (RetVT == MVT::ppcf128) 600 return SINTTOFP_I32_PPCF128; 601 } else if (OpVT == MVT::i64) { 602 if (RetVT == MVT::f32) 603 return SINTTOFP_I64_F32; 604 if (RetVT == MVT::f64) 605 return SINTTOFP_I64_F64; 606 if (RetVT == MVT::f80) 607 return SINTTOFP_I64_F80; 608 if (RetVT == MVT::f128) 609 return SINTTOFP_I64_F128; 610 if (RetVT == MVT::ppcf128) 611 return SINTTOFP_I64_PPCF128; 612 } else if (OpVT == MVT::i128) { 613 if (RetVT == MVT::f32) 614 return SINTTOFP_I128_F32; 615 if (RetVT == MVT::f64) 616 return SINTTOFP_I128_F64; 617 if (RetVT == MVT::f80) 618 return SINTTOFP_I128_F80; 619 if (RetVT == MVT::f128) 620 return SINTTOFP_I128_F128; 621 if (RetVT == MVT::ppcf128) 622 return SINTTOFP_I128_PPCF128; 623 } 624 return UNKNOWN_LIBCALL; 625 } 626 627 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 628 /// UNKNOWN_LIBCALL if there is none. 629 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) { 630 if (OpVT == MVT::i32) { 631 if (RetVT == MVT::f32) 632 return UINTTOFP_I32_F32; 633 if (RetVT == MVT::f64) 634 return UINTTOFP_I32_F64; 635 if (RetVT == MVT::f80) 636 return UINTTOFP_I32_F80; 637 if (RetVT == MVT::f128) 638 return UINTTOFP_I32_F128; 639 if (RetVT == MVT::ppcf128) 640 return UINTTOFP_I32_PPCF128; 641 } else if (OpVT == MVT::i64) { 642 if (RetVT == MVT::f32) 643 return UINTTOFP_I64_F32; 644 if (RetVT == MVT::f64) 645 return UINTTOFP_I64_F64; 646 if (RetVT == MVT::f80) 647 return UINTTOFP_I64_F80; 648 if (RetVT == MVT::f128) 649 return UINTTOFP_I64_F128; 650 if (RetVT == MVT::ppcf128) 651 return UINTTOFP_I64_PPCF128; 652 } else if (OpVT == MVT::i128) { 653 if (RetVT == MVT::f32) 654 return UINTTOFP_I128_F32; 655 if (RetVT == MVT::f64) 656 return UINTTOFP_I128_F64; 657 if (RetVT == MVT::f80) 658 return UINTTOFP_I128_F80; 659 if (RetVT == MVT::f128) 660 return UINTTOFP_I128_F128; 661 if (RetVT == MVT::ppcf128) 662 return UINTTOFP_I128_PPCF128; 663 } 664 return UNKNOWN_LIBCALL; 665 } 666 667 RTLIB::Libcall RTLIB::getATOMIC(unsigned Opc, MVT VT) { 668 #define OP_TO_LIBCALL(Name, Enum) \ 669 case Name: \ 670 switch (VT.SimpleTy) { \ 671 default: \ 672 return UNKNOWN_LIBCALL; \ 673 case MVT::i8: \ 674 return Enum##_1; \ 675 case MVT::i16: \ 676 return Enum##_2; \ 677 case MVT::i32: \ 678 return Enum##_4; \ 679 case MVT::i64: \ 680 return Enum##_8; \ 681 case MVT::i128: \ 682 return Enum##_16; \ 683 } 684 685 switch (Opc) { 686 OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET) 687 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP) 688 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD) 689 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB) 690 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND) 691 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR) 692 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR) 693 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND) 694 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX) 695 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX) 696 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN) 697 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN) 698 } 699 700 #undef OP_TO_LIBCALL 701 702 return UNKNOWN_LIBCALL; 703 } 704 705 /// InitCmpLibcallCCs - Set default comparison libcall CC. 706 /// 707 static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 708 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 709 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 710 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 711 CCs[RTLIB::OEQ_F128] = ISD::SETEQ; 712 CCs[RTLIB::UNE_F32] = ISD::SETNE; 713 CCs[RTLIB::UNE_F64] = ISD::SETNE; 714 CCs[RTLIB::UNE_F128] = ISD::SETNE; 715 CCs[RTLIB::OGE_F32] = ISD::SETGE; 716 CCs[RTLIB::OGE_F64] = ISD::SETGE; 717 CCs[RTLIB::OGE_F128] = ISD::SETGE; 718 CCs[RTLIB::OLT_F32] = ISD::SETLT; 719 CCs[RTLIB::OLT_F64] = ISD::SETLT; 720 CCs[RTLIB::OLT_F128] = ISD::SETLT; 721 CCs[RTLIB::OLE_F32] = ISD::SETLE; 722 CCs[RTLIB::OLE_F64] = ISD::SETLE; 723 CCs[RTLIB::OLE_F128] = ISD::SETLE; 724 CCs[RTLIB::OGT_F32] = ISD::SETGT; 725 CCs[RTLIB::OGT_F64] = ISD::SETGT; 726 CCs[RTLIB::OGT_F128] = ISD::SETGT; 727 CCs[RTLIB::UO_F32] = ISD::SETNE; 728 CCs[RTLIB::UO_F64] = ISD::SETNE; 729 CCs[RTLIB::UO_F128] = ISD::SETNE; 730 CCs[RTLIB::O_F32] = ISD::SETEQ; 731 CCs[RTLIB::O_F64] = ISD::SETEQ; 732 CCs[RTLIB::O_F128] = ISD::SETEQ; 733 } 734 735 /// NOTE: The TargetMachine owns TLOF. 736 TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm) : TM(tm) { 737 initActions(); 738 739 // Perform these initializations only once. 740 IsLittleEndian = getDataLayout()->isLittleEndian(); 741 MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove = 8; 742 MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize 743 = MaxStoresPerMemmoveOptSize = 4; 744 UseUnderscoreSetJmp = false; 745 UseUnderscoreLongJmp = false; 746 SelectIsExpensive = false; 747 HasMultipleConditionRegisters = false; 748 HasExtractBitsInsn = false; 749 IntDivIsCheap = false; 750 FsqrtIsCheap = false; 751 Pow2SDivIsCheap = false; 752 JumpIsExpensive = false; 753 PredictableSelectIsExpensive = false; 754 MaskAndBranchFoldingIsLegal = false; 755 EnableExtLdPromotion = false; 756 HasFloatingPointExceptions = true; 757 StackPointerRegisterToSaveRestore = 0; 758 ExceptionPointerRegister = 0; 759 ExceptionSelectorRegister = 0; 760 BooleanContents = UndefinedBooleanContent; 761 BooleanFloatContents = UndefinedBooleanContent; 762 BooleanVectorContents = UndefinedBooleanContent; 763 SchedPreferenceInfo = Sched::ILP; 764 JumpBufSize = 0; 765 JumpBufAlignment = 0; 766 MinFunctionAlignment = 0; 767 PrefFunctionAlignment = 0; 768 PrefLoopAlignment = 0; 769 MinStackArgumentAlignment = 1; 770 InsertFencesForAtomic = false; 771 MinimumJumpTableEntries = 4; 772 773 InitLibcallNames(LibcallRoutineNames, Triple(TM.getTargetTriple())); 774 InitCmpLibcallCCs(CmpLibcallCCs); 775 InitLibcallCallingConvs(LibcallCallingConvs); 776 } 777 778 void TargetLoweringBase::initActions() { 779 // All operations default to being supported. 780 memset(OpActions, 0, sizeof(OpActions)); 781 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 782 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 783 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 784 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 785 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 786 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 787 788 // Set default actions for various operations. 789 for (MVT VT : MVT::all_valuetypes()) { 790 // Default all indexed load / store to expand. 791 for (unsigned IM = (unsigned)ISD::PRE_INC; 792 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 793 setIndexedLoadAction(IM, VT, Expand); 794 setIndexedStoreAction(IM, VT, Expand); 795 } 796 797 // Most backends expect to see the node which just returns the value loaded. 798 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Expand); 799 800 // These operations default to expand. 801 setOperationAction(ISD::FGETSIGN, VT, Expand); 802 setOperationAction(ISD::CONCAT_VECTORS, VT, Expand); 803 setOperationAction(ISD::FMINNUM, VT, Expand); 804 setOperationAction(ISD::FMAXNUM, VT, Expand); 805 setOperationAction(ISD::FMAD, VT, Expand); 806 807 // These library functions default to expand. 808 setOperationAction(ISD::FROUND, VT, Expand); 809 810 // These operations default to expand for vector types. 811 if (VT.isVector()) { 812 setOperationAction(ISD::FCOPYSIGN, VT, Expand); 813 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, VT, Expand); 814 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Expand); 815 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Expand); 816 } 817 } 818 819 // Most targets ignore the @llvm.prefetch intrinsic. 820 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 821 822 // ConstantFP nodes default to expand. Targets can either change this to 823 // Legal, in which case all fp constants are legal, or use isFPImmLegal() 824 // to optimize expansions for certain constants. 825 setOperationAction(ISD::ConstantFP, MVT::f16, Expand); 826 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 827 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 828 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 829 setOperationAction(ISD::ConstantFP, MVT::f128, Expand); 830 831 // These library functions default to expand. 832 for (MVT VT : {MVT::f32, MVT::f64, MVT::f128}) { 833 setOperationAction(ISD::FLOG , VT, Expand); 834 setOperationAction(ISD::FLOG2, VT, Expand); 835 setOperationAction(ISD::FLOG10, VT, Expand); 836 setOperationAction(ISD::FEXP , VT, Expand); 837 setOperationAction(ISD::FEXP2, VT, Expand); 838 setOperationAction(ISD::FFLOOR, VT, Expand); 839 setOperationAction(ISD::FMINNUM, VT, Expand); 840 setOperationAction(ISD::FMAXNUM, VT, Expand); 841 setOperationAction(ISD::FNEARBYINT, VT, Expand); 842 setOperationAction(ISD::FCEIL, VT, Expand); 843 setOperationAction(ISD::FRINT, VT, Expand); 844 setOperationAction(ISD::FTRUNC, VT, Expand); 845 setOperationAction(ISD::FROUND, VT, Expand); 846 } 847 848 // Default ISD::TRAP to expand (which turns it into abort). 849 setOperationAction(ISD::TRAP, MVT::Other, Expand); 850 851 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand" 852 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP. 853 // 854 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand); 855 } 856 857 MVT TargetLoweringBase::getPointerTy(uint32_t AS) const { 858 return MVT::getIntegerVT(getPointerSizeInBits(AS)); 859 } 860 861 unsigned TargetLoweringBase::getPointerSizeInBits(uint32_t AS) const { 862 return getDataLayout()->getPointerSizeInBits(AS); 863 } 864 865 unsigned TargetLoweringBase::getPointerTypeSizeInBits(Type *Ty) const { 866 assert(Ty->isPointerTy()); 867 return getPointerSizeInBits(Ty->getPointerAddressSpace()); 868 } 869 870 MVT TargetLoweringBase::getScalarShiftAmountTy(EVT LHSTy) const { 871 return MVT::getIntegerVT(8 * getDataLayout()->getPointerSize(0)); 872 } 873 874 EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy) const { 875 assert(LHSTy.isInteger() && "Shift amount is not an integer type!"); 876 if (LHSTy.isVector()) 877 return LHSTy; 878 return getScalarShiftAmountTy(LHSTy); 879 } 880 881 /// canOpTrap - Returns true if the operation can trap for the value type. 882 /// VT must be a legal type. 883 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const { 884 assert(isTypeLegal(VT)); 885 switch (Op) { 886 default: 887 return false; 888 case ISD::FDIV: 889 case ISD::FREM: 890 case ISD::SDIV: 891 case ISD::UDIV: 892 case ISD::SREM: 893 case ISD::UREM: 894 return true; 895 } 896 } 897 898 TargetLoweringBase::LegalizeKind 899 TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const { 900 // If this is a simple type, use the ComputeRegisterProp mechanism. 901 if (VT.isSimple()) { 902 MVT SVT = VT.getSimpleVT(); 903 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType)); 904 MVT NVT = TransformToType[SVT.SimpleTy]; 905 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT); 906 907 assert((LA == TypeLegal || LA == TypeSoftenFloat || 908 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger) && 909 "Promote may not follow Expand or Promote"); 910 911 if (LA == TypeSplitVector) 912 return LegalizeKind(LA, 913 EVT::getVectorVT(Context, SVT.getVectorElementType(), 914 SVT.getVectorNumElements() / 2)); 915 if (LA == TypeScalarizeVector) 916 return LegalizeKind(LA, SVT.getVectorElementType()); 917 return LegalizeKind(LA, NVT); 918 } 919 920 // Handle Extended Scalar Types. 921 if (!VT.isVector()) { 922 assert(VT.isInteger() && "Float types must be simple"); 923 unsigned BitSize = VT.getSizeInBits(); 924 // First promote to a power-of-two size, then expand if necessary. 925 if (BitSize < 8 || !isPowerOf2_32(BitSize)) { 926 EVT NVT = VT.getRoundIntegerType(Context); 927 assert(NVT != VT && "Unable to round integer VT"); 928 LegalizeKind NextStep = getTypeConversion(Context, NVT); 929 // Avoid multi-step promotion. 930 if (NextStep.first == TypePromoteInteger) 931 return NextStep; 932 // Return rounded integer type. 933 return LegalizeKind(TypePromoteInteger, NVT); 934 } 935 936 return LegalizeKind(TypeExpandInteger, 937 EVT::getIntegerVT(Context, VT.getSizeInBits() / 2)); 938 } 939 940 // Handle vector types. 941 unsigned NumElts = VT.getVectorNumElements(); 942 EVT EltVT = VT.getVectorElementType(); 943 944 // Vectors with only one element are always scalarized. 945 if (NumElts == 1) 946 return LegalizeKind(TypeScalarizeVector, EltVT); 947 948 // Try to widen vector elements until the element type is a power of two and 949 // promote it to a legal type later on, for example: 950 // <3 x i8> -> <4 x i8> -> <4 x i32> 951 if (EltVT.isInteger()) { 952 // Vectors with a number of elements that is not a power of two are always 953 // widened, for example <3 x i8> -> <4 x i8>. 954 if (!VT.isPow2VectorType()) { 955 NumElts = (unsigned)NextPowerOf2(NumElts); 956 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts); 957 return LegalizeKind(TypeWidenVector, NVT); 958 } 959 960 // Examine the element type. 961 LegalizeKind LK = getTypeConversion(Context, EltVT); 962 963 // If type is to be expanded, split the vector. 964 // <4 x i140> -> <2 x i140> 965 if (LK.first == TypeExpandInteger) 966 return LegalizeKind(TypeSplitVector, 967 EVT::getVectorVT(Context, EltVT, NumElts / 2)); 968 969 // Promote the integer element types until a legal vector type is found 970 // or until the element integer type is too big. If a legal type was not 971 // found, fallback to the usual mechanism of widening/splitting the 972 // vector. 973 EVT OldEltVT = EltVT; 974 while (1) { 975 // Increase the bitwidth of the element to the next pow-of-two 976 // (which is greater than 8 bits). 977 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits()) 978 .getRoundIntegerType(Context); 979 980 // Stop trying when getting a non-simple element type. 981 // Note that vector elements may be greater than legal vector element 982 // types. Example: X86 XMM registers hold 64bit element on 32bit 983 // systems. 984 if (!EltVT.isSimple()) 985 break; 986 987 // Build a new vector type and check if it is legal. 988 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); 989 // Found a legal promoted vector type. 990 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal) 991 return LegalizeKind(TypePromoteInteger, 992 EVT::getVectorVT(Context, EltVT, NumElts)); 993 } 994 995 // Reset the type to the unexpanded type if we did not find a legal vector 996 // type with a promoted vector element type. 997 EltVT = OldEltVT; 998 } 999 1000 // Try to widen the vector until a legal type is found. 1001 // If there is no wider legal type, split the vector. 1002 while (1) { 1003 // Round up to the next power of 2. 1004 NumElts = (unsigned)NextPowerOf2(NumElts); 1005 1006 // If there is no simple vector type with this many elements then there 1007 // cannot be a larger legal vector type. Note that this assumes that 1008 // there are no skipped intermediate vector types in the simple types. 1009 if (!EltVT.isSimple()) 1010 break; 1011 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); 1012 if (LargerVector == MVT()) 1013 break; 1014 1015 // If this type is legal then widen the vector. 1016 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal) 1017 return LegalizeKind(TypeWidenVector, LargerVector); 1018 } 1019 1020 // Widen odd vectors to next power of two. 1021 if (!VT.isPow2VectorType()) { 1022 EVT NVT = VT.getPow2VectorType(Context); 1023 return LegalizeKind(TypeWidenVector, NVT); 1024 } 1025 1026 // Vectors with illegal element types are expanded. 1027 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2); 1028 return LegalizeKind(TypeSplitVector, NVT); 1029 } 1030 1031 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, 1032 unsigned &NumIntermediates, 1033 MVT &RegisterVT, 1034 TargetLoweringBase *TLI) { 1035 // Figure out the right, legal destination reg to copy into. 1036 unsigned NumElts = VT.getVectorNumElements(); 1037 MVT EltTy = VT.getVectorElementType(); 1038 1039 unsigned NumVectorRegs = 1; 1040 1041 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 1042 // could break down into LHS/RHS like LegalizeDAG does. 1043 if (!isPowerOf2_32(NumElts)) { 1044 NumVectorRegs = NumElts; 1045 NumElts = 1; 1046 } 1047 1048 // Divide the input until we get to a supported size. This will always 1049 // end with a scalar if the target doesn't support vectors. 1050 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 1051 NumElts >>= 1; 1052 NumVectorRegs <<= 1; 1053 } 1054 1055 NumIntermediates = NumVectorRegs; 1056 1057 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 1058 if (!TLI->isTypeLegal(NewVT)) 1059 NewVT = EltTy; 1060 IntermediateVT = NewVT; 1061 1062 unsigned NewVTSize = NewVT.getSizeInBits(); 1063 1064 // Convert sizes such as i33 to i64. 1065 if (!isPowerOf2_32(NewVTSize)) 1066 NewVTSize = NextPowerOf2(NewVTSize); 1067 1068 MVT DestVT = TLI->getRegisterType(NewVT); 1069 RegisterVT = DestVT; 1070 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 1071 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 1072 1073 // Otherwise, promotion or legal types use the same number of registers as 1074 // the vector decimated to the appropriate level. 1075 return NumVectorRegs; 1076 } 1077 1078 /// isLegalRC - Return true if the value types that can be represented by the 1079 /// specified register class are all legal. 1080 bool TargetLoweringBase::isLegalRC(const TargetRegisterClass *RC) const { 1081 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 1082 I != E; ++I) { 1083 if (isTypeLegal(*I)) 1084 return true; 1085 } 1086 return false; 1087 } 1088 1089 /// Replace/modify any TargetFrameIndex operands with a targte-dependent 1090 /// sequence of memory operands that is recognized by PrologEpilogInserter. 1091 MachineBasicBlock* 1092 TargetLoweringBase::emitPatchPoint(MachineInstr *MI, 1093 MachineBasicBlock *MBB) const { 1094 MachineFunction &MF = *MI->getParent()->getParent(); 1095 1096 // MI changes inside this loop as we grow operands. 1097 for(unsigned OperIdx = 0; OperIdx != MI->getNumOperands(); ++OperIdx) { 1098 MachineOperand &MO = MI->getOperand(OperIdx); 1099 if (!MO.isFI()) 1100 continue; 1101 1102 // foldMemoryOperand builds a new MI after replacing a single FI operand 1103 // with the canonical set of five x86 addressing-mode operands. 1104 int FI = MO.getIndex(); 1105 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc()); 1106 1107 // Copy operands before the frame-index. 1108 for (unsigned i = 0; i < OperIdx; ++i) 1109 MIB.addOperand(MI->getOperand(i)); 1110 // Add frame index operands: direct-mem-ref tag, #FI, offset. 1111 MIB.addImm(StackMaps::DirectMemRefOp); 1112 MIB.addOperand(MI->getOperand(OperIdx)); 1113 MIB.addImm(0); 1114 // Copy the operands after the frame index. 1115 for (unsigned i = OperIdx + 1; i != MI->getNumOperands(); ++i) 1116 MIB.addOperand(MI->getOperand(i)); 1117 1118 // Inherit previous memory operands. 1119 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); 1120 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!"); 1121 1122 // Add a new memory operand for this FI. 1123 const MachineFrameInfo &MFI = *MF.getFrameInfo(); 1124 assert(MFI.getObjectOffset(FI) != -1); 1125 1126 unsigned Flags = MachineMemOperand::MOLoad; 1127 if (MI->getOpcode() == TargetOpcode::STATEPOINT) { 1128 Flags |= MachineMemOperand::MOStore; 1129 Flags |= MachineMemOperand::MOVolatile; 1130 } 1131 MachineMemOperand *MMO = MF.getMachineMemOperand( 1132 MachinePointerInfo::getFixedStack(FI), Flags, 1133 TM.getDataLayout()->getPointerSize(), MFI.getObjectAlignment(FI)); 1134 MIB->addMemOperand(MF, MMO); 1135 1136 // Replace the instruction and update the operand index. 1137 MBB->insert(MachineBasicBlock::iterator(MI), MIB); 1138 OperIdx += (MIB->getNumOperands() - MI->getNumOperands()) - 1; 1139 MI->eraseFromParent(); 1140 MI = MIB; 1141 } 1142 return MBB; 1143 } 1144 1145 /// findRepresentativeClass - Return the largest legal super-reg register class 1146 /// of the register class for the specified type and its associated "cost". 1147 // This function is in TargetLowering because it uses RegClassForVT which would 1148 // need to be moved to TargetRegisterInfo and would necessitate moving 1149 // isTypeLegal over as well - a massive change that would just require 1150 // TargetLowering having a TargetRegisterInfo class member that it would use. 1151 std::pair<const TargetRegisterClass *, uint8_t> 1152 TargetLoweringBase::findRepresentativeClass(const TargetRegisterInfo *TRI, 1153 MVT VT) const { 1154 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; 1155 if (!RC) 1156 return std::make_pair(RC, 0); 1157 1158 // Compute the set of all super-register classes. 1159 BitVector SuperRegRC(TRI->getNumRegClasses()); 1160 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI) 1161 SuperRegRC.setBitsInMask(RCI.getMask()); 1162 1163 // Find the first legal register class with the largest spill size. 1164 const TargetRegisterClass *BestRC = RC; 1165 for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) { 1166 const TargetRegisterClass *SuperRC = TRI->getRegClass(i); 1167 // We want the largest possible spill size. 1168 if (SuperRC->getSize() <= BestRC->getSize()) 1169 continue; 1170 if (!isLegalRC(SuperRC)) 1171 continue; 1172 BestRC = SuperRC; 1173 } 1174 return std::make_pair(BestRC, 1); 1175 } 1176 1177 /// computeRegisterProperties - Once all of the register classes are added, 1178 /// this allows us to compute derived properties we expose. 1179 void TargetLoweringBase::computeRegisterProperties( 1180 const TargetRegisterInfo *TRI) { 1181 static_assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE, 1182 "Too many value types for ValueTypeActions to hold!"); 1183 1184 // Everything defaults to needing one register. 1185 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 1186 NumRegistersForVT[i] = 1; 1187 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 1188 } 1189 // ...except isVoid, which doesn't need any registers. 1190 NumRegistersForVT[MVT::isVoid] = 0; 1191 1192 // Find the largest integer register class. 1193 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 1194 for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg) 1195 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 1196 1197 // Every integer value type larger than this largest register takes twice as 1198 // many registers to represent as the previous ValueType. 1199 for (unsigned ExpandedReg = LargestIntReg + 1; 1200 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) { 1201 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 1202 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 1203 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 1204 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg, 1205 TypeExpandInteger); 1206 } 1207 1208 // Inspect all of the ValueType's smaller than the largest integer 1209 // register to see which ones need promotion. 1210 unsigned LegalIntReg = LargestIntReg; 1211 for (unsigned IntReg = LargestIntReg - 1; 1212 IntReg >= (unsigned)MVT::i1; --IntReg) { 1213 MVT IVT = (MVT::SimpleValueType)IntReg; 1214 if (isTypeLegal(IVT)) { 1215 LegalIntReg = IntReg; 1216 } else { 1217 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 1218 (const MVT::SimpleValueType)LegalIntReg; 1219 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger); 1220 } 1221 } 1222 1223 // ppcf128 type is really two f64's. 1224 if (!isTypeLegal(MVT::ppcf128)) { 1225 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 1226 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 1227 TransformToType[MVT::ppcf128] = MVT::f64; 1228 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat); 1229 } 1230 1231 // Decide how to handle f128. If the target does not have native f128 support, 1232 // expand it to i128 and we will be generating soft float library calls. 1233 if (!isTypeLegal(MVT::f128)) { 1234 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128]; 1235 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128]; 1236 TransformToType[MVT::f128] = MVT::i128; 1237 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat); 1238 } 1239 1240 // Decide how to handle f64. If the target does not have native f64 support, 1241 // expand it to i64 and we will be generating soft float library calls. 1242 if (!isTypeLegal(MVT::f64)) { 1243 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 1244 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 1245 TransformToType[MVT::f64] = MVT::i64; 1246 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat); 1247 } 1248 1249 // Decide how to handle f32. If the target does not have native f32 support, 1250 // expand it to i32 and we will be generating soft float library calls. 1251 if (!isTypeLegal(MVT::f32)) { 1252 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 1253 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 1254 TransformToType[MVT::f32] = MVT::i32; 1255 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat); 1256 } 1257 1258 if (!isTypeLegal(MVT::f16)) { 1259 // If the target has native f32 support, promote f16 operations to f32. If 1260 // f32 is not supported, generate soft float library calls. 1261 if (isTypeLegal(MVT::f32)) { 1262 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32]; 1263 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32]; 1264 TransformToType[MVT::f16] = MVT::f32; 1265 ValueTypeActions.setTypeAction(MVT::f16, TypePromoteFloat); 1266 } else { 1267 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::i16]; 1268 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::i16]; 1269 TransformToType[MVT::f16] = MVT::i16; 1270 ValueTypeActions.setTypeAction(MVT::f16, TypeSoftenFloat); 1271 } 1272 } 1273 1274 // Loop over all of the vector value types to see which need transformations. 1275 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 1276 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 1277 MVT VT = (MVT::SimpleValueType) i; 1278 if (isTypeLegal(VT)) 1279 continue; 1280 1281 MVT EltVT = VT.getVectorElementType(); 1282 unsigned NElts = VT.getVectorNumElements(); 1283 bool IsLegalWiderType = false; 1284 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT); 1285 switch (PreferredAction) { 1286 case TypePromoteInteger: { 1287 // Try to promote the elements of integer vectors. If no legal 1288 // promotion was found, fall through to the widen-vector method. 1289 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 1290 MVT SVT = (MVT::SimpleValueType) nVT; 1291 // Promote vectors of integers to vectors with the same number 1292 // of elements, with a wider element type. 1293 if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits() 1294 && SVT.getVectorNumElements() == NElts && isTypeLegal(SVT) 1295 && SVT.getScalarType().isInteger()) { 1296 TransformToType[i] = SVT; 1297 RegisterTypeForVT[i] = SVT; 1298 NumRegistersForVT[i] = 1; 1299 ValueTypeActions.setTypeAction(VT, TypePromoteInteger); 1300 IsLegalWiderType = true; 1301 break; 1302 } 1303 } 1304 if (IsLegalWiderType) 1305 break; 1306 } 1307 case TypeWidenVector: { 1308 // Try to widen the vector. 1309 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 1310 MVT SVT = (MVT::SimpleValueType) nVT; 1311 if (SVT.getVectorElementType() == EltVT 1312 && SVT.getVectorNumElements() > NElts && isTypeLegal(SVT)) { 1313 TransformToType[i] = SVT; 1314 RegisterTypeForVT[i] = SVT; 1315 NumRegistersForVT[i] = 1; 1316 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 1317 IsLegalWiderType = true; 1318 break; 1319 } 1320 } 1321 if (IsLegalWiderType) 1322 break; 1323 } 1324 case TypeSplitVector: 1325 case TypeScalarizeVector: { 1326 MVT IntermediateVT; 1327 MVT RegisterVT; 1328 unsigned NumIntermediates; 1329 NumRegistersForVT[i] = getVectorTypeBreakdownMVT(VT, IntermediateVT, 1330 NumIntermediates, RegisterVT, this); 1331 RegisterTypeForVT[i] = RegisterVT; 1332 1333 MVT NVT = VT.getPow2VectorType(); 1334 if (NVT == VT) { 1335 // Type is already a power of 2. The default action is to split. 1336 TransformToType[i] = MVT::Other; 1337 if (PreferredAction == TypeScalarizeVector) 1338 ValueTypeActions.setTypeAction(VT, TypeScalarizeVector); 1339 else if (PreferredAction == TypeSplitVector) 1340 ValueTypeActions.setTypeAction(VT, TypeSplitVector); 1341 else 1342 // Set type action according to the number of elements. 1343 ValueTypeActions.setTypeAction(VT, NElts == 1 ? TypeScalarizeVector 1344 : TypeSplitVector); 1345 } else { 1346 TransformToType[i] = NVT; 1347 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 1348 } 1349 break; 1350 } 1351 default: 1352 llvm_unreachable("Unknown vector legalization action!"); 1353 } 1354 } 1355 1356 // Determine the 'representative' register class for each value type. 1357 // An representative register class is the largest (meaning one which is 1358 // not a sub-register class / subreg register class) legal register class for 1359 // a group of value types. For example, on i386, i8, i16, and i32 1360 // representative would be GR32; while on x86_64 it's GR64. 1361 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 1362 const TargetRegisterClass* RRC; 1363 uint8_t Cost; 1364 std::tie(RRC, Cost) = findRepresentativeClass(TRI, (MVT::SimpleValueType)i); 1365 RepRegClassForVT[i] = RRC; 1366 RepRegClassCostForVT[i] = Cost; 1367 } 1368 } 1369 1370 EVT TargetLoweringBase::getSetCCResultType(LLVMContext &, EVT VT) const { 1371 assert(!VT.isVector() && "No default SetCC type for vectors!"); 1372 return getPointerTy(0).SimpleTy; 1373 } 1374 1375 MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType() const { 1376 return MVT::i32; // return the default value 1377 } 1378 1379 /// getVectorTypeBreakdown - Vector types are broken down into some number of 1380 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 1381 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 1382 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 1383 /// 1384 /// This method returns the number of registers needed, and the VT for each 1385 /// register. It also returns the VT and quantity of the intermediate values 1386 /// before they are promoted/expanded. 1387 /// 1388 unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 1389 EVT &IntermediateVT, 1390 unsigned &NumIntermediates, 1391 MVT &RegisterVT) const { 1392 unsigned NumElts = VT.getVectorNumElements(); 1393 1394 // If there is a wider vector type with the same element type as this one, 1395 // or a promoted vector type that has the same number of elements which 1396 // are wider, then we should convert to that legal vector type. 1397 // This handles things like <2 x float> -> <4 x float> and 1398 // <4 x i1> -> <4 x i32>. 1399 LegalizeTypeAction TA = getTypeAction(Context, VT); 1400 if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) { 1401 EVT RegisterEVT = getTypeToTransformTo(Context, VT); 1402 if (isTypeLegal(RegisterEVT)) { 1403 IntermediateVT = RegisterEVT; 1404 RegisterVT = RegisterEVT.getSimpleVT(); 1405 NumIntermediates = 1; 1406 return 1; 1407 } 1408 } 1409 1410 // Figure out the right, legal destination reg to copy into. 1411 EVT EltTy = VT.getVectorElementType(); 1412 1413 unsigned NumVectorRegs = 1; 1414 1415 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 1416 // could break down into LHS/RHS like LegalizeDAG does. 1417 if (!isPowerOf2_32(NumElts)) { 1418 NumVectorRegs = NumElts; 1419 NumElts = 1; 1420 } 1421 1422 // Divide the input until we get to a supported size. This will always 1423 // end with a scalar if the target doesn't support vectors. 1424 while (NumElts > 1 && !isTypeLegal( 1425 EVT::getVectorVT(Context, EltTy, NumElts))) { 1426 NumElts >>= 1; 1427 NumVectorRegs <<= 1; 1428 } 1429 1430 NumIntermediates = NumVectorRegs; 1431 1432 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts); 1433 if (!isTypeLegal(NewVT)) 1434 NewVT = EltTy; 1435 IntermediateVT = NewVT; 1436 1437 MVT DestVT = getRegisterType(Context, NewVT); 1438 RegisterVT = DestVT; 1439 unsigned NewVTSize = NewVT.getSizeInBits(); 1440 1441 // Convert sizes such as i33 to i64. 1442 if (!isPowerOf2_32(NewVTSize)) 1443 NewVTSize = NextPowerOf2(NewVTSize); 1444 1445 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 1446 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 1447 1448 // Otherwise, promotion or legal types use the same number of registers as 1449 // the vector decimated to the appropriate level. 1450 return NumVectorRegs; 1451 } 1452 1453 /// Get the EVTs and ArgFlags collections that represent the legalized return 1454 /// type of the given function. This does not require a DAG or a return value, 1455 /// and is suitable for use before any DAGs for the function are constructed. 1456 /// TODO: Move this out of TargetLowering.cpp. 1457 void llvm::GetReturnInfo(Type* ReturnType, AttributeSet attr, 1458 SmallVectorImpl<ISD::OutputArg> &Outs, 1459 const TargetLowering &TLI) { 1460 SmallVector<EVT, 4> ValueVTs; 1461 ComputeValueVTs(TLI, ReturnType, ValueVTs); 1462 unsigned NumValues = ValueVTs.size(); 1463 if (NumValues == 0) return; 1464 1465 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1466 EVT VT = ValueVTs[j]; 1467 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1468 1469 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt)) 1470 ExtendKind = ISD::SIGN_EXTEND; 1471 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt)) 1472 ExtendKind = ISD::ZERO_EXTEND; 1473 1474 // FIXME: C calling convention requires the return type to be promoted to 1475 // at least 32-bit. But this is not necessary for non-C calling 1476 // conventions. The frontend should mark functions whose return values 1477 // require promoting with signext or zeroext attributes. 1478 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 1479 MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32); 1480 if (VT.bitsLT(MinVT)) 1481 VT = MinVT; 1482 } 1483 1484 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT); 1485 MVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT); 1486 1487 // 'inreg' on function refers to return value 1488 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1489 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::InReg)) 1490 Flags.setInReg(); 1491 1492 // Propagate extension type if any 1493 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt)) 1494 Flags.setSExt(); 1495 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt)) 1496 Flags.setZExt(); 1497 1498 for (unsigned i = 0; i < NumParts; ++i) 1499 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isFixed=*/true, 0, 0)); 1500 } 1501 } 1502 1503 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1504 /// function arguments in the caller parameter area. This is the actual 1505 /// alignment, not its logarithm. 1506 unsigned TargetLoweringBase::getByValTypeAlignment(Type *Ty) const { 1507 return getDataLayout()->getABITypeAlignment(Ty); 1508 } 1509 1510 //===----------------------------------------------------------------------===// 1511 // TargetTransformInfo Helpers 1512 //===----------------------------------------------------------------------===// 1513 1514 int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const { 1515 enum InstructionOpcodes { 1516 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM, 1517 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM 1518 #include "llvm/IR/Instruction.def" 1519 }; 1520 switch (static_cast<InstructionOpcodes>(Opcode)) { 1521 case Ret: return 0; 1522 case Br: return 0; 1523 case Switch: return 0; 1524 case IndirectBr: return 0; 1525 case Invoke: return 0; 1526 case Resume: return 0; 1527 case Unreachable: return 0; 1528 case Add: return ISD::ADD; 1529 case FAdd: return ISD::FADD; 1530 case Sub: return ISD::SUB; 1531 case FSub: return ISD::FSUB; 1532 case Mul: return ISD::MUL; 1533 case FMul: return ISD::FMUL; 1534 case UDiv: return ISD::UDIV; 1535 case SDiv: return ISD::SDIV; 1536 case FDiv: return ISD::FDIV; 1537 case URem: return ISD::UREM; 1538 case SRem: return ISD::SREM; 1539 case FRem: return ISD::FREM; 1540 case Shl: return ISD::SHL; 1541 case LShr: return ISD::SRL; 1542 case AShr: return ISD::SRA; 1543 case And: return ISD::AND; 1544 case Or: return ISD::OR; 1545 case Xor: return ISD::XOR; 1546 case Alloca: return 0; 1547 case Load: return ISD::LOAD; 1548 case Store: return ISD::STORE; 1549 case GetElementPtr: return 0; 1550 case Fence: return 0; 1551 case AtomicCmpXchg: return 0; 1552 case AtomicRMW: return 0; 1553 case Trunc: return ISD::TRUNCATE; 1554 case ZExt: return ISD::ZERO_EXTEND; 1555 case SExt: return ISD::SIGN_EXTEND; 1556 case FPToUI: return ISD::FP_TO_UINT; 1557 case FPToSI: return ISD::FP_TO_SINT; 1558 case UIToFP: return ISD::UINT_TO_FP; 1559 case SIToFP: return ISD::SINT_TO_FP; 1560 case FPTrunc: return ISD::FP_ROUND; 1561 case FPExt: return ISD::FP_EXTEND; 1562 case PtrToInt: return ISD::BITCAST; 1563 case IntToPtr: return ISD::BITCAST; 1564 case BitCast: return ISD::BITCAST; 1565 case AddrSpaceCast: return ISD::ADDRSPACECAST; 1566 case ICmp: return ISD::SETCC; 1567 case FCmp: return ISD::SETCC; 1568 case PHI: return 0; 1569 case Call: return 0; 1570 case Select: return ISD::SELECT; 1571 case UserOp1: return 0; 1572 case UserOp2: return 0; 1573 case VAArg: return 0; 1574 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT; 1575 case InsertElement: return ISD::INSERT_VECTOR_ELT; 1576 case ShuffleVector: return ISD::VECTOR_SHUFFLE; 1577 case ExtractValue: return ISD::MERGE_VALUES; 1578 case InsertValue: return ISD::MERGE_VALUES; 1579 case LandingPad: return 0; 1580 } 1581 1582 llvm_unreachable("Unknown instruction type encountered!"); 1583 } 1584 1585 std::pair<unsigned, MVT> 1586 TargetLoweringBase::getTypeLegalizationCost(Type *Ty) const { 1587 LLVMContext &C = Ty->getContext(); 1588 EVT MTy = getValueType(Ty); 1589 1590 unsigned Cost = 1; 1591 // We keep legalizing the type until we find a legal kind. We assume that 1592 // the only operation that costs anything is the split. After splitting 1593 // we need to handle two types. 1594 while (true) { 1595 LegalizeKind LK = getTypeConversion(C, MTy); 1596 1597 if (LK.first == TypeLegal) 1598 return std::make_pair(Cost, MTy.getSimpleVT()); 1599 1600 if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger) 1601 Cost *= 2; 1602 1603 // Keep legalizing the type. 1604 MTy = LK.second; 1605 } 1606 } 1607 1608 //===----------------------------------------------------------------------===// 1609 // Loop Strength Reduction hooks 1610 //===----------------------------------------------------------------------===// 1611 1612 /// isLegalAddressingMode - Return true if the addressing mode represented 1613 /// by AM is legal for this target, for a load/store of the specified type. 1614 bool TargetLoweringBase::isLegalAddressingMode(const AddrMode &AM, 1615 Type *Ty) const { 1616 // The default implementation of this implements a conservative RISCy, r+r and 1617 // r+i addr mode. 1618 1619 // Allows a sign-extended 16-bit immediate field. 1620 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 1621 return false; 1622 1623 // No global is ever allowed as a base. 1624 if (AM.BaseGV) 1625 return false; 1626 1627 // Only support r+r, 1628 switch (AM.Scale) { 1629 case 0: // "r+i" or just "i", depending on HasBaseReg. 1630 break; 1631 case 1: 1632 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 1633 return false; 1634 // Otherwise we have r+r or r+i. 1635 break; 1636 case 2: 1637 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 1638 return false; 1639 // Allow 2*r as r+r. 1640 break; 1641 default: // Don't allow n * r 1642 return false; 1643 } 1644 1645 return true; 1646 } 1647
