1 //===-- XCoreISelLowering.cpp - XCore DAG Lowering Implementation ---------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the XCoreTargetLowering class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "XCoreISelLowering.h" 15 #include "XCore.h" 16 #include "XCoreMachineFunctionInfo.h" 17 #include "XCoreSubtarget.h" 18 #include "XCoreTargetMachine.h" 19 #include "XCoreTargetObjectFile.h" 20 #include "llvm/CodeGen/CallingConvLower.h" 21 #include "llvm/CodeGen/MachineFrameInfo.h" 22 #include "llvm/CodeGen/MachineFunction.h" 23 #include "llvm/CodeGen/MachineInstrBuilder.h" 24 #include "llvm/CodeGen/MachineJumpTableInfo.h" 25 #include "llvm/CodeGen/MachineRegisterInfo.h" 26 #include "llvm/CodeGen/SelectionDAGISel.h" 27 #include "llvm/CodeGen/ValueTypes.h" 28 #include "llvm/IR/CallingConv.h" 29 #include "llvm/IR/Constants.h" 30 #include "llvm/IR/DerivedTypes.h" 31 #include "llvm/IR/Function.h" 32 #include "llvm/IR/GlobalAlias.h" 33 #include "llvm/IR/GlobalVariable.h" 34 #include "llvm/IR/Intrinsics.h" 35 #include "llvm/Support/Debug.h" 36 #include "llvm/Support/ErrorHandling.h" 37 #include "llvm/Support/raw_ostream.h" 38 #include <algorithm> 39 40 using namespace llvm; 41 42 #define DEBUG_TYPE "xcore-lower" 43 44 const char *XCoreTargetLowering:: 45 getTargetNodeName(unsigned Opcode) const 46 { 47 switch (Opcode) 48 { 49 case XCoreISD::BL : return "XCoreISD::BL"; 50 case XCoreISD::PCRelativeWrapper : return "XCoreISD::PCRelativeWrapper"; 51 case XCoreISD::DPRelativeWrapper : return "XCoreISD::DPRelativeWrapper"; 52 case XCoreISD::CPRelativeWrapper : return "XCoreISD::CPRelativeWrapper"; 53 case XCoreISD::LDWSP : return "XCoreISD::LDWSP"; 54 case XCoreISD::STWSP : return "XCoreISD::STWSP"; 55 case XCoreISD::RETSP : return "XCoreISD::RETSP"; 56 case XCoreISD::LADD : return "XCoreISD::LADD"; 57 case XCoreISD::LSUB : return "XCoreISD::LSUB"; 58 case XCoreISD::LMUL : return "XCoreISD::LMUL"; 59 case XCoreISD::MACCU : return "XCoreISD::MACCU"; 60 case XCoreISD::MACCS : return "XCoreISD::MACCS"; 61 case XCoreISD::CRC8 : return "XCoreISD::CRC8"; 62 case XCoreISD::BR_JT : return "XCoreISD::BR_JT"; 63 case XCoreISD::BR_JT32 : return "XCoreISD::BR_JT32"; 64 case XCoreISD::FRAME_TO_ARGS_OFFSET : return "XCoreISD::FRAME_TO_ARGS_OFFSET"; 65 case XCoreISD::EH_RETURN : return "XCoreISD::EH_RETURN"; 66 case XCoreISD::MEMBARRIER : return "XCoreISD::MEMBARRIER"; 67 default : return nullptr; 68 } 69 } 70 71 XCoreTargetLowering::XCoreTargetLowering(const TargetMachine &TM, 72 const XCoreSubtarget &Subtarget) 73 : TargetLowering(TM), TM(TM), Subtarget(Subtarget) { 74 75 // Set up the register classes. 76 addRegisterClass(MVT::i32, &XCore::GRRegsRegClass); 77 78 // Compute derived properties from the register classes 79 computeRegisterProperties(Subtarget.getRegisterInfo()); 80 81 // Division is expensive 82 setIntDivIsCheap(false); 83 84 setStackPointerRegisterToSaveRestore(XCore::SP); 85 86 setSchedulingPreference(Sched::Source); 87 88 // Use i32 for setcc operations results (slt, sgt, ...). 89 setBooleanContents(ZeroOrOneBooleanContent); 90 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct? 91 92 // XCore does not have the NodeTypes below. 93 setOperationAction(ISD::BR_CC, MVT::i32, Expand); 94 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); 95 setOperationAction(ISD::ADDC, MVT::i32, Expand); 96 setOperationAction(ISD::ADDE, MVT::i32, Expand); 97 setOperationAction(ISD::SUBC, MVT::i32, Expand); 98 setOperationAction(ISD::SUBE, MVT::i32, Expand); 99 100 // 64bit 101 setOperationAction(ISD::ADD, MVT::i64, Custom); 102 setOperationAction(ISD::SUB, MVT::i64, Custom); 103 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom); 104 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom); 105 setOperationAction(ISD::MULHS, MVT::i32, Expand); 106 setOperationAction(ISD::MULHU, MVT::i32, Expand); 107 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 108 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 109 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 110 111 // Bit Manipulation 112 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 113 setOperationAction(ISD::ROTL , MVT::i32, Expand); 114 setOperationAction(ISD::ROTR , MVT::i32, Expand); 115 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); 116 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); 117 118 setOperationAction(ISD::TRAP, MVT::Other, Legal); 119 120 // Jump tables. 121 setOperationAction(ISD::BR_JT, MVT::Other, Custom); 122 123 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 124 setOperationAction(ISD::BlockAddress, MVT::i32 , Custom); 125 126 // Conversion of i64 -> double produces constantpool nodes 127 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 128 129 // Loads 130 for (MVT VT : MVT::integer_valuetypes()) { 131 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); 132 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); 133 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); 134 135 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand); 136 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Expand); 137 } 138 139 // Custom expand misaligned loads / stores. 140 setOperationAction(ISD::LOAD, MVT::i32, Custom); 141 setOperationAction(ISD::STORE, MVT::i32, Custom); 142 143 // Varargs 144 setOperationAction(ISD::VAEND, MVT::Other, Expand); 145 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 146 setOperationAction(ISD::VAARG, MVT::Other, Custom); 147 setOperationAction(ISD::VASTART, MVT::Other, Custom); 148 149 // Dynamic stack 150 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 151 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 152 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 153 154 // Exception handling 155 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom); 156 setExceptionPointerRegister(XCore::R0); 157 setExceptionSelectorRegister(XCore::R1); 158 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); 159 160 // Atomic operations 161 // We request a fence for ATOMIC_* instructions, to reduce them to Monotonic. 162 // As we are always Sequential Consistent, an ATOMIC_FENCE becomes a no OP. 163 setInsertFencesForAtomic(true); 164 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); 165 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom); 166 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom); 167 168 // TRAMPOLINE is custom lowered. 169 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom); 170 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom); 171 172 // We want to custom lower some of our intrinsics. 173 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 174 175 MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 4; 176 MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize 177 = MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 2; 178 179 // We have target-specific dag combine patterns for the following nodes: 180 setTargetDAGCombine(ISD::STORE); 181 setTargetDAGCombine(ISD::ADD); 182 setTargetDAGCombine(ISD::INTRINSIC_VOID); 183 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN); 184 185 setMinFunctionAlignment(1); 186 setPrefFunctionAlignment(2); 187 } 188 189 bool XCoreTargetLowering::isZExtFree(SDValue Val, EVT VT2) const { 190 if (Val.getOpcode() != ISD::LOAD) 191 return false; 192 193 EVT VT1 = Val.getValueType(); 194 if (!VT1.isSimple() || !VT1.isInteger() || 195 !VT2.isSimple() || !VT2.isInteger()) 196 return false; 197 198 switch (VT1.getSimpleVT().SimpleTy) { 199 default: break; 200 case MVT::i8: 201 return true; 202 } 203 204 return false; 205 } 206 207 SDValue XCoreTargetLowering:: 208 LowerOperation(SDValue Op, SelectionDAG &DAG) const { 209 switch (Op.getOpcode()) 210 { 211 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); 212 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 213 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 214 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 215 case ISD::BR_JT: return LowerBR_JT(Op, DAG); 216 case ISD::LOAD: return LowerLOAD(Op, DAG); 217 case ISD::STORE: return LowerSTORE(Op, DAG); 218 case ISD::VAARG: return LowerVAARG(Op, DAG); 219 case ISD::VASTART: return LowerVASTART(Op, DAG); 220 case ISD::SMUL_LOHI: return LowerSMUL_LOHI(Op, DAG); 221 case ISD::UMUL_LOHI: return LowerUMUL_LOHI(Op, DAG); 222 // FIXME: Remove these when LegalizeDAGTypes lands. 223 case ISD::ADD: 224 case ISD::SUB: return ExpandADDSUB(Op.getNode(), DAG); 225 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 226 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 227 case ISD::FRAME_TO_ARGS_OFFSET: return LowerFRAME_TO_ARGS_OFFSET(Op, DAG); 228 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG); 229 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG); 230 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 231 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG); 232 case ISD::ATOMIC_LOAD: return LowerATOMIC_LOAD(Op, DAG); 233 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op, DAG); 234 default: 235 llvm_unreachable("unimplemented operand"); 236 } 237 } 238 239 /// ReplaceNodeResults - Replace the results of node with an illegal result 240 /// type with new values built out of custom code. 241 void XCoreTargetLowering::ReplaceNodeResults(SDNode *N, 242 SmallVectorImpl<SDValue>&Results, 243 SelectionDAG &DAG) const { 244 switch (N->getOpcode()) { 245 default: 246 llvm_unreachable("Don't know how to custom expand this!"); 247 case ISD::ADD: 248 case ISD::SUB: 249 Results.push_back(ExpandADDSUB(N, DAG)); 250 return; 251 } 252 } 253 254 //===----------------------------------------------------------------------===// 255 // Misc Lower Operation implementation 256 //===----------------------------------------------------------------------===// 257 258 SDValue XCoreTargetLowering::getGlobalAddressWrapper(SDValue GA, 259 const GlobalValue *GV, 260 SelectionDAG &DAG) const { 261 // FIXME there is no actual debug info here 262 SDLoc dl(GA); 263 264 if (GV->getType()->getElementType()->isFunctionTy()) 265 return DAG.getNode(XCoreISD::PCRelativeWrapper, dl, MVT::i32, GA); 266 267 const auto *GVar = dyn_cast<GlobalVariable>(GV); 268 if ((GV->hasSection() && StringRef(GV->getSection()).startswith(".cp.")) || 269 (GVar && GVar->isConstant() && GV->hasLocalLinkage())) 270 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, GA); 271 272 return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, GA); 273 } 274 275 static bool IsSmallObject(const GlobalValue *GV, const XCoreTargetLowering &XTL) { 276 if (XTL.getTargetMachine().getCodeModel() == CodeModel::Small) 277 return true; 278 279 Type *ObjType = GV->getType()->getPointerElementType(); 280 if (!ObjType->isSized()) 281 return false; 282 283 unsigned ObjSize = XTL.getDataLayout()->getTypeAllocSize(ObjType); 284 return ObjSize < CodeModelLargeSize && ObjSize != 0; 285 } 286 287 SDValue XCoreTargetLowering:: 288 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const 289 { 290 const GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Op); 291 const GlobalValue *GV = GN->getGlobal(); 292 SDLoc DL(GN); 293 int64_t Offset = GN->getOffset(); 294 if (IsSmallObject(GV, *this)) { 295 // We can only fold positive offsets that are a multiple of the word size. 296 int64_t FoldedOffset = std::max(Offset & ~3, (int64_t)0); 297 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, FoldedOffset); 298 GA = getGlobalAddressWrapper(GA, GV, DAG); 299 // Handle the rest of the offset. 300 if (Offset != FoldedOffset) { 301 SDValue Remaining = DAG.getConstant(Offset - FoldedOffset, MVT::i32); 302 GA = DAG.getNode(ISD::ADD, DL, MVT::i32, GA, Remaining); 303 } 304 return GA; 305 } else { 306 // Ideally we would not fold in offset with an index <= 11. 307 Type *Ty = Type::getInt8PtrTy(*DAG.getContext()); 308 Constant *GA = ConstantExpr::getBitCast(const_cast<GlobalValue*>(GV), Ty); 309 Ty = Type::getInt32Ty(*DAG.getContext()); 310 Constant *Idx = ConstantInt::get(Ty, Offset); 311 Constant *GAI = ConstantExpr::getGetElementPtr( 312 Type::getInt8Ty(*DAG.getContext()), GA, Idx); 313 SDValue CP = DAG.getConstantPool(GAI, MVT::i32); 314 return DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), CP, 315 MachinePointerInfo(), false, false, false, 0); 316 } 317 } 318 319 SDValue XCoreTargetLowering:: 320 LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const 321 { 322 SDLoc DL(Op); 323 324 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 325 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy()); 326 327 return DAG.getNode(XCoreISD::PCRelativeWrapper, DL, getPointerTy(), Result); 328 } 329 330 SDValue XCoreTargetLowering:: 331 LowerConstantPool(SDValue Op, SelectionDAG &DAG) const 332 { 333 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 334 // FIXME there isn't really debug info here 335 SDLoc dl(CP); 336 EVT PtrVT = Op.getValueType(); 337 SDValue Res; 338 if (CP->isMachineConstantPoolEntry()) { 339 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, 340 CP->getAlignment(), CP->getOffset()); 341 } else { 342 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, 343 CP->getAlignment(), CP->getOffset()); 344 } 345 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, Res); 346 } 347 348 unsigned XCoreTargetLowering::getJumpTableEncoding() const { 349 return MachineJumpTableInfo::EK_Inline; 350 } 351 352 SDValue XCoreTargetLowering:: 353 LowerBR_JT(SDValue Op, SelectionDAG &DAG) const 354 { 355 SDValue Chain = Op.getOperand(0); 356 SDValue Table = Op.getOperand(1); 357 SDValue Index = Op.getOperand(2); 358 SDLoc dl(Op); 359 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table); 360 unsigned JTI = JT->getIndex(); 361 MachineFunction &MF = DAG.getMachineFunction(); 362 const MachineJumpTableInfo *MJTI = MF.getJumpTableInfo(); 363 SDValue TargetJT = DAG.getTargetJumpTable(JT->getIndex(), MVT::i32); 364 365 unsigned NumEntries = MJTI->getJumpTables()[JTI].MBBs.size(); 366 if (NumEntries <= 32) { 367 return DAG.getNode(XCoreISD::BR_JT, dl, MVT::Other, Chain, TargetJT, Index); 368 } 369 assert((NumEntries >> 31) == 0); 370 SDValue ScaledIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index, 371 DAG.getConstant(1, MVT::i32)); 372 return DAG.getNode(XCoreISD::BR_JT32, dl, MVT::Other, Chain, TargetJT, 373 ScaledIndex); 374 } 375 376 SDValue XCoreTargetLowering:: 377 lowerLoadWordFromAlignedBasePlusOffset(SDLoc DL, SDValue Chain, SDValue Base, 378 int64_t Offset, SelectionDAG &DAG) const 379 { 380 if ((Offset & 0x3) == 0) { 381 return DAG.getLoad(getPointerTy(), DL, Chain, Base, MachinePointerInfo(), 382 false, false, false, 0); 383 } 384 // Lower to pair of consecutive word aligned loads plus some bit shifting. 385 int32_t HighOffset = RoundUpToAlignment(Offset, 4); 386 int32_t LowOffset = HighOffset - 4; 387 SDValue LowAddr, HighAddr; 388 if (GlobalAddressSDNode *GASD = 389 dyn_cast<GlobalAddressSDNode>(Base.getNode())) { 390 LowAddr = DAG.getGlobalAddress(GASD->getGlobal(), DL, Base.getValueType(), 391 LowOffset); 392 HighAddr = DAG.getGlobalAddress(GASD->getGlobal(), DL, Base.getValueType(), 393 HighOffset); 394 } else { 395 LowAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, Base, 396 DAG.getConstant(LowOffset, MVT::i32)); 397 HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, Base, 398 DAG.getConstant(HighOffset, MVT::i32)); 399 } 400 SDValue LowShift = DAG.getConstant((Offset - LowOffset) * 8, MVT::i32); 401 SDValue HighShift = DAG.getConstant((HighOffset - Offset) * 8, MVT::i32); 402 403 SDValue Low = DAG.getLoad(getPointerTy(), DL, Chain, 404 LowAddr, MachinePointerInfo(), 405 false, false, false, 0); 406 SDValue High = DAG.getLoad(getPointerTy(), DL, Chain, 407 HighAddr, MachinePointerInfo(), 408 false, false, false, 0); 409 SDValue LowShifted = DAG.getNode(ISD::SRL, DL, MVT::i32, Low, LowShift); 410 SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High, HighShift); 411 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, LowShifted, HighShifted); 412 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Low.getValue(1), 413 High.getValue(1)); 414 SDValue Ops[] = { Result, Chain }; 415 return DAG.getMergeValues(Ops, DL); 416 } 417 418 static bool isWordAligned(SDValue Value, SelectionDAG &DAG) 419 { 420 APInt KnownZero, KnownOne; 421 DAG.computeKnownBits(Value, KnownZero, KnownOne); 422 return KnownZero.countTrailingOnes() >= 2; 423 } 424 425 SDValue XCoreTargetLowering:: 426 LowerLOAD(SDValue Op, SelectionDAG &DAG) const { 427 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 428 LoadSDNode *LD = cast<LoadSDNode>(Op); 429 assert(LD->getExtensionType() == ISD::NON_EXTLOAD && 430 "Unexpected extension type"); 431 assert(LD->getMemoryVT() == MVT::i32 && "Unexpected load EVT"); 432 if (allowsMisalignedMemoryAccesses(LD->getMemoryVT(), 433 LD->getAddressSpace(), 434 LD->getAlignment())) 435 return SDValue(); 436 437 unsigned ABIAlignment = getDataLayout()-> 438 getABITypeAlignment(LD->getMemoryVT().getTypeForEVT(*DAG.getContext())); 439 // Leave aligned load alone. 440 if (LD->getAlignment() >= ABIAlignment) 441 return SDValue(); 442 443 SDValue Chain = LD->getChain(); 444 SDValue BasePtr = LD->getBasePtr(); 445 SDLoc DL(Op); 446 447 if (!LD->isVolatile()) { 448 const GlobalValue *GV; 449 int64_t Offset = 0; 450 if (DAG.isBaseWithConstantOffset(BasePtr) && 451 isWordAligned(BasePtr->getOperand(0), DAG)) { 452 SDValue NewBasePtr = BasePtr->getOperand(0); 453 Offset = cast<ConstantSDNode>(BasePtr->getOperand(1))->getSExtValue(); 454 return lowerLoadWordFromAlignedBasePlusOffset(DL, Chain, NewBasePtr, 455 Offset, DAG); 456 } 457 if (TLI.isGAPlusOffset(BasePtr.getNode(), GV, Offset) && 458 MinAlign(GV->getAlignment(), 4) == 4) { 459 SDValue NewBasePtr = DAG.getGlobalAddress(GV, DL, 460 BasePtr->getValueType(0)); 461 return lowerLoadWordFromAlignedBasePlusOffset(DL, Chain, NewBasePtr, 462 Offset, DAG); 463 } 464 } 465 466 if (LD->getAlignment() == 2) { 467 SDValue Low = DAG.getExtLoad(ISD::ZEXTLOAD, DL, MVT::i32, Chain, 468 BasePtr, LD->getPointerInfo(), MVT::i16, 469 LD->isVolatile(), LD->isNonTemporal(), 470 LD->isInvariant(), 2); 471 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, 472 DAG.getConstant(2, MVT::i32)); 473 SDValue High = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain, 474 HighAddr, 475 LD->getPointerInfo().getWithOffset(2), 476 MVT::i16, LD->isVolatile(), 477 LD->isNonTemporal(), LD->isInvariant(), 2); 478 SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High, 479 DAG.getConstant(16, MVT::i32)); 480 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Low, HighShifted); 481 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Low.getValue(1), 482 High.getValue(1)); 483 SDValue Ops[] = { Result, Chain }; 484 return DAG.getMergeValues(Ops, DL); 485 } 486 487 // Lower to a call to __misaligned_load(BasePtr). 488 Type *IntPtrTy = getDataLayout()->getIntPtrType(*DAG.getContext()); 489 TargetLowering::ArgListTy Args; 490 TargetLowering::ArgListEntry Entry; 491 492 Entry.Ty = IntPtrTy; 493 Entry.Node = BasePtr; 494 Args.push_back(Entry); 495 496 TargetLowering::CallLoweringInfo CLI(DAG); 497 CLI.setDebugLoc(DL).setChain(Chain) 498 .setCallee(CallingConv::C, IntPtrTy, 499 DAG.getExternalSymbol("__misaligned_load", getPointerTy()), 500 std::move(Args), 0); 501 502 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 503 SDValue Ops[] = { CallResult.first, CallResult.second }; 504 return DAG.getMergeValues(Ops, DL); 505 } 506 507 SDValue XCoreTargetLowering:: 508 LowerSTORE(SDValue Op, SelectionDAG &DAG) const 509 { 510 StoreSDNode *ST = cast<StoreSDNode>(Op); 511 assert(!ST->isTruncatingStore() && "Unexpected store type"); 512 assert(ST->getMemoryVT() == MVT::i32 && "Unexpected store EVT"); 513 if (allowsMisalignedMemoryAccesses(ST->getMemoryVT(), 514 ST->getAddressSpace(), 515 ST->getAlignment())) { 516 return SDValue(); 517 } 518 unsigned ABIAlignment = getDataLayout()-> 519 getABITypeAlignment(ST->getMemoryVT().getTypeForEVT(*DAG.getContext())); 520 // Leave aligned store alone. 521 if (ST->getAlignment() >= ABIAlignment) { 522 return SDValue(); 523 } 524 SDValue Chain = ST->getChain(); 525 SDValue BasePtr = ST->getBasePtr(); 526 SDValue Value = ST->getValue(); 527 SDLoc dl(Op); 528 529 if (ST->getAlignment() == 2) { 530 SDValue Low = Value; 531 SDValue High = DAG.getNode(ISD::SRL, dl, MVT::i32, Value, 532 DAG.getConstant(16, MVT::i32)); 533 SDValue StoreLow = DAG.getTruncStore(Chain, dl, Low, BasePtr, 534 ST->getPointerInfo(), MVT::i16, 535 ST->isVolatile(), ST->isNonTemporal(), 536 2); 537 SDValue HighAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, BasePtr, 538 DAG.getConstant(2, MVT::i32)); 539 SDValue StoreHigh = DAG.getTruncStore(Chain, dl, High, HighAddr, 540 ST->getPointerInfo().getWithOffset(2), 541 MVT::i16, ST->isVolatile(), 542 ST->isNonTemporal(), 2); 543 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, StoreLow, StoreHigh); 544 } 545 546 // Lower to a call to __misaligned_store(BasePtr, Value). 547 Type *IntPtrTy = getDataLayout()->getIntPtrType(*DAG.getContext()); 548 TargetLowering::ArgListTy Args; 549 TargetLowering::ArgListEntry Entry; 550 551 Entry.Ty = IntPtrTy; 552 Entry.Node = BasePtr; 553 Args.push_back(Entry); 554 555 Entry.Node = Value; 556 Args.push_back(Entry); 557 558 TargetLowering::CallLoweringInfo CLI(DAG); 559 CLI.setDebugLoc(dl).setChain(Chain) 560 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()), 561 DAG.getExternalSymbol("__misaligned_store", getPointerTy()), 562 std::move(Args), 0); 563 564 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); 565 return CallResult.second; 566 } 567 568 SDValue XCoreTargetLowering:: 569 LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const 570 { 571 assert(Op.getValueType() == MVT::i32 && Op.getOpcode() == ISD::SMUL_LOHI && 572 "Unexpected operand to lower!"); 573 SDLoc dl(Op); 574 SDValue LHS = Op.getOperand(0); 575 SDValue RHS = Op.getOperand(1); 576 SDValue Zero = DAG.getConstant(0, MVT::i32); 577 SDValue Hi = DAG.getNode(XCoreISD::MACCS, dl, 578 DAG.getVTList(MVT::i32, MVT::i32), Zero, Zero, 579 LHS, RHS); 580 SDValue Lo(Hi.getNode(), 1); 581 SDValue Ops[] = { Lo, Hi }; 582 return DAG.getMergeValues(Ops, dl); 583 } 584 585 SDValue XCoreTargetLowering:: 586 LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const 587 { 588 assert(Op.getValueType() == MVT::i32 && Op.getOpcode() == ISD::UMUL_LOHI && 589 "Unexpected operand to lower!"); 590 SDLoc dl(Op); 591 SDValue LHS = Op.getOperand(0); 592 SDValue RHS = Op.getOperand(1); 593 SDValue Zero = DAG.getConstant(0, MVT::i32); 594 SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl, 595 DAG.getVTList(MVT::i32, MVT::i32), LHS, RHS, 596 Zero, Zero); 597 SDValue Lo(Hi.getNode(), 1); 598 SDValue Ops[] = { Lo, Hi }; 599 return DAG.getMergeValues(Ops, dl); 600 } 601 602 /// isADDADDMUL - Return whether Op is in a form that is equivalent to 603 /// add(add(mul(x,y),a),b). If requireIntermediatesHaveOneUse is true then 604 /// each intermediate result in the calculation must also have a single use. 605 /// If the Op is in the correct form the constituent parts are written to Mul0, 606 /// Mul1, Addend0 and Addend1. 607 static bool 608 isADDADDMUL(SDValue Op, SDValue &Mul0, SDValue &Mul1, SDValue &Addend0, 609 SDValue &Addend1, bool requireIntermediatesHaveOneUse) 610 { 611 if (Op.getOpcode() != ISD::ADD) 612 return false; 613 SDValue N0 = Op.getOperand(0); 614 SDValue N1 = Op.getOperand(1); 615 SDValue AddOp; 616 SDValue OtherOp; 617 if (N0.getOpcode() == ISD::ADD) { 618 AddOp = N0; 619 OtherOp = N1; 620 } else if (N1.getOpcode() == ISD::ADD) { 621 AddOp = N1; 622 OtherOp = N0; 623 } else { 624 return false; 625 } 626 if (requireIntermediatesHaveOneUse && !AddOp.hasOneUse()) 627 return false; 628 if (OtherOp.getOpcode() == ISD::MUL) { 629 // add(add(a,b),mul(x,y)) 630 if (requireIntermediatesHaveOneUse && !OtherOp.hasOneUse()) 631 return false; 632 Mul0 = OtherOp.getOperand(0); 633 Mul1 = OtherOp.getOperand(1); 634 Addend0 = AddOp.getOperand(0); 635 Addend1 = AddOp.getOperand(1); 636 return true; 637 } 638 if (AddOp.getOperand(0).getOpcode() == ISD::MUL) { 639 // add(add(mul(x,y),a),b) 640 if (requireIntermediatesHaveOneUse && !AddOp.getOperand(0).hasOneUse()) 641 return false; 642 Mul0 = AddOp.getOperand(0).getOperand(0); 643 Mul1 = AddOp.getOperand(0).getOperand(1); 644 Addend0 = AddOp.getOperand(1); 645 Addend1 = OtherOp; 646 return true; 647 } 648 if (AddOp.getOperand(1).getOpcode() == ISD::MUL) { 649 // add(add(a,mul(x,y)),b) 650 if (requireIntermediatesHaveOneUse && !AddOp.getOperand(1).hasOneUse()) 651 return false; 652 Mul0 = AddOp.getOperand(1).getOperand(0); 653 Mul1 = AddOp.getOperand(1).getOperand(1); 654 Addend0 = AddOp.getOperand(0); 655 Addend1 = OtherOp; 656 return true; 657 } 658 return false; 659 } 660 661 SDValue XCoreTargetLowering:: 662 TryExpandADDWithMul(SDNode *N, SelectionDAG &DAG) const 663 { 664 SDValue Mul; 665 SDValue Other; 666 if (N->getOperand(0).getOpcode() == ISD::MUL) { 667 Mul = N->getOperand(0); 668 Other = N->getOperand(1); 669 } else if (N->getOperand(1).getOpcode() == ISD::MUL) { 670 Mul = N->getOperand(1); 671 Other = N->getOperand(0); 672 } else { 673 return SDValue(); 674 } 675 SDLoc dl(N); 676 SDValue LL, RL, AddendL, AddendH; 677 LL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 678 Mul.getOperand(0), DAG.getConstant(0, MVT::i32)); 679 RL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 680 Mul.getOperand(1), DAG.getConstant(0, MVT::i32)); 681 AddendL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 682 Other, DAG.getConstant(0, MVT::i32)); 683 AddendH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 684 Other, DAG.getConstant(1, MVT::i32)); 685 APInt HighMask = APInt::getHighBitsSet(64, 32); 686 unsigned LHSSB = DAG.ComputeNumSignBits(Mul.getOperand(0)); 687 unsigned RHSSB = DAG.ComputeNumSignBits(Mul.getOperand(1)); 688 if (DAG.MaskedValueIsZero(Mul.getOperand(0), HighMask) && 689 DAG.MaskedValueIsZero(Mul.getOperand(1), HighMask)) { 690 // The inputs are both zero-extended. 691 SDValue Hi = DAG.getNode(XCoreISD::MACCU, dl, 692 DAG.getVTList(MVT::i32, MVT::i32), AddendH, 693 AddendL, LL, RL); 694 SDValue Lo(Hi.getNode(), 1); 695 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); 696 } 697 if (LHSSB > 32 && RHSSB > 32) { 698 // The inputs are both sign-extended. 699 SDValue Hi = DAG.getNode(XCoreISD::MACCS, dl, 700 DAG.getVTList(MVT::i32, MVT::i32), AddendH, 701 AddendL, LL, RL); 702 SDValue Lo(Hi.getNode(), 1); 703 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); 704 } 705 SDValue LH, RH; 706 LH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 707 Mul.getOperand(0), DAG.getConstant(1, MVT::i32)); 708 RH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 709 Mul.getOperand(1), DAG.getConstant(1, MVT::i32)); 710 SDValue Hi = DAG.getNode(XCoreISD::MACCU, dl, 711 DAG.getVTList(MVT::i32, MVT::i32), AddendH, 712 AddendL, LL, RL); 713 SDValue Lo(Hi.getNode(), 1); 714 RH = DAG.getNode(ISD::MUL, dl, MVT::i32, LL, RH); 715 LH = DAG.getNode(ISD::MUL, dl, MVT::i32, LH, RL); 716 Hi = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, RH); 717 Hi = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, LH); 718 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); 719 } 720 721 SDValue XCoreTargetLowering:: 722 ExpandADDSUB(SDNode *N, SelectionDAG &DAG) const 723 { 724 assert(N->getValueType(0) == MVT::i64 && 725 (N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && 726 "Unknown operand to lower!"); 727 728 if (N->getOpcode() == ISD::ADD) { 729 SDValue Result = TryExpandADDWithMul(N, DAG); 730 if (Result.getNode()) 731 return Result; 732 } 733 734 SDLoc dl(N); 735 736 // Extract components 737 SDValue LHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 738 N->getOperand(0), DAG.getConstant(0, MVT::i32)); 739 SDValue LHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 740 N->getOperand(0), DAG.getConstant(1, MVT::i32)); 741 SDValue RHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 742 N->getOperand(1), DAG.getConstant(0, MVT::i32)); 743 SDValue RHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 744 N->getOperand(1), DAG.getConstant(1, MVT::i32)); 745 746 // Expand 747 unsigned Opcode = (N->getOpcode() == ISD::ADD) ? XCoreISD::LADD : 748 XCoreISD::LSUB; 749 SDValue Zero = DAG.getConstant(0, MVT::i32); 750 SDValue Lo = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32), 751 LHSL, RHSL, Zero); 752 SDValue Carry(Lo.getNode(), 1); 753 754 SDValue Hi = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32), 755 LHSH, RHSH, Carry); 756 SDValue Ignored(Hi.getNode(), 1); 757 // Merge the pieces 758 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); 759 } 760 761 SDValue XCoreTargetLowering:: 762 LowerVAARG(SDValue Op, SelectionDAG &DAG) const 763 { 764 // Whist llvm does not support aggregate varargs we can ignore 765 // the possibility of the ValueType being an implicit byVal vararg. 766 SDNode *Node = Op.getNode(); 767 EVT VT = Node->getValueType(0); // not an aggregate 768 SDValue InChain = Node->getOperand(0); 769 SDValue VAListPtr = Node->getOperand(1); 770 EVT PtrVT = VAListPtr.getValueType(); 771 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 772 SDLoc dl(Node); 773 SDValue VAList = DAG.getLoad(PtrVT, dl, InChain, 774 VAListPtr, MachinePointerInfo(SV), 775 false, false, false, 0); 776 // Increment the pointer, VAList, to the next vararg 777 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAList, 778 DAG.getIntPtrConstant(VT.getSizeInBits() / 8)); 779 // Store the incremented VAList to the legalized pointer 780 InChain = DAG.getStore(VAList.getValue(1), dl, nextPtr, VAListPtr, 781 MachinePointerInfo(SV), false, false, 0); 782 // Load the actual argument out of the pointer VAList 783 return DAG.getLoad(VT, dl, InChain, VAList, MachinePointerInfo(), 784 false, false, false, 0); 785 } 786 787 SDValue XCoreTargetLowering:: 788 LowerVASTART(SDValue Op, SelectionDAG &DAG) const 789 { 790 SDLoc dl(Op); 791 // vastart stores the address of the VarArgsFrameIndex slot into the 792 // memory location argument 793 MachineFunction &MF = DAG.getMachineFunction(); 794 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>(); 795 SDValue Addr = DAG.getFrameIndex(XFI->getVarArgsFrameIndex(), MVT::i32); 796 return DAG.getStore(Op.getOperand(0), dl, Addr, Op.getOperand(1), 797 MachinePointerInfo(), false, false, 0); 798 } 799 800 SDValue XCoreTargetLowering::LowerFRAMEADDR(SDValue Op, 801 SelectionDAG &DAG) const { 802 // This nodes represent llvm.frameaddress on the DAG. 803 // It takes one operand, the index of the frame address to return. 804 // An index of zero corresponds to the current function's frame address. 805 // An index of one to the parent's frame address, and so on. 806 // Depths > 0 not supported yet! 807 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0) 808 return SDValue(); 809 810 MachineFunction &MF = DAG.getMachineFunction(); 811 const TargetRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); 812 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), 813 RegInfo->getFrameRegister(MF), MVT::i32); 814 } 815 816 SDValue XCoreTargetLowering:: 817 LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const { 818 // This nodes represent llvm.returnaddress on the DAG. 819 // It takes one operand, the index of the return address to return. 820 // An index of zero corresponds to the current function's return address. 821 // An index of one to the parent's return address, and so on. 822 // Depths > 0 not supported yet! 823 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0) 824 return SDValue(); 825 826 MachineFunction &MF = DAG.getMachineFunction(); 827 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>(); 828 int FI = XFI->createLRSpillSlot(MF); 829 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); 830 return DAG.getLoad(getPointerTy(), SDLoc(Op), DAG.getEntryNode(), FIN, 831 MachinePointerInfo::getFixedStack(FI), false, false, 832 false, 0); 833 } 834 835 SDValue XCoreTargetLowering:: 836 LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const { 837 // This node represents offset from frame pointer to first on-stack argument. 838 // This is needed for correct stack adjustment during unwind. 839 // However, we don't know the offset until after the frame has be finalised. 840 // This is done during the XCoreFTAOElim pass. 841 return DAG.getNode(XCoreISD::FRAME_TO_ARGS_OFFSET, SDLoc(Op), MVT::i32); 842 } 843 844 SDValue XCoreTargetLowering:: 845 LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const { 846 // OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) 847 // This node represents 'eh_return' gcc dwarf builtin, which is used to 848 // return from exception. The general meaning is: adjust stack by OFFSET and 849 // pass execution to HANDLER. 850 MachineFunction &MF = DAG.getMachineFunction(); 851 SDValue Chain = Op.getOperand(0); 852 SDValue Offset = Op.getOperand(1); 853 SDValue Handler = Op.getOperand(2); 854 SDLoc dl(Op); 855 856 // Absolute SP = (FP + FrameToArgs) + Offset 857 const TargetRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); 858 SDValue Stack = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 859 RegInfo->getFrameRegister(MF), MVT::i32); 860 SDValue FrameToArgs = DAG.getNode(XCoreISD::FRAME_TO_ARGS_OFFSET, dl, 861 MVT::i32); 862 Stack = DAG.getNode(ISD::ADD, dl, MVT::i32, Stack, FrameToArgs); 863 Stack = DAG.getNode(ISD::ADD, dl, MVT::i32, Stack, Offset); 864 865 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 866 // which leaves 2 caller saved registers, R2 & R3 for us to use. 867 unsigned StackReg = XCore::R2; 868 unsigned HandlerReg = XCore::R3; 869 870 SDValue OutChains[] = { 871 DAG.getCopyToReg(Chain, dl, StackReg, Stack), 872 DAG.getCopyToReg(Chain, dl, HandlerReg, Handler) 873 }; 874 875 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains); 876 877 return DAG.getNode(XCoreISD::EH_RETURN, dl, MVT::Other, Chain, 878 DAG.getRegister(StackReg, MVT::i32), 879 DAG.getRegister(HandlerReg, MVT::i32)); 880 881 } 882 883 SDValue XCoreTargetLowering:: 884 LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const { 885 return Op.getOperand(0); 886 } 887 888 SDValue XCoreTargetLowering:: 889 LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const { 890 SDValue Chain = Op.getOperand(0); 891 SDValue Trmp = Op.getOperand(1); // trampoline 892 SDValue FPtr = Op.getOperand(2); // nested function 893 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 894 895 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 896 897 // .align 4 898 // LDAPF_u10 r11, nest 899 // LDW_2rus r11, r11[0] 900 // STWSP_ru6 r11, sp[0] 901 // LDAPF_u10 r11, fptr 902 // LDW_2rus r11, r11[0] 903 // BAU_1r r11 904 // nest: 905 // .word nest 906 // fptr: 907 // .word fptr 908 SDValue OutChains[5]; 909 910 SDValue Addr = Trmp; 911 912 SDLoc dl(Op); 913 OutChains[0] = DAG.getStore(Chain, dl, DAG.getConstant(0x0a3cd805, MVT::i32), 914 Addr, MachinePointerInfo(TrmpAddr), false, false, 915 0); 916 917 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 918 DAG.getConstant(4, MVT::i32)); 919 OutChains[1] = DAG.getStore(Chain, dl, DAG.getConstant(0xd80456c0, MVT::i32), 920 Addr, MachinePointerInfo(TrmpAddr, 4), false, 921 false, 0); 922 923 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 924 DAG.getConstant(8, MVT::i32)); 925 OutChains[2] = DAG.getStore(Chain, dl, DAG.getConstant(0x27fb0a3c, MVT::i32), 926 Addr, MachinePointerInfo(TrmpAddr, 8), false, 927 false, 0); 928 929 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 930 DAG.getConstant(12, MVT::i32)); 931 OutChains[3] = DAG.getStore(Chain, dl, Nest, Addr, 932 MachinePointerInfo(TrmpAddr, 12), false, false, 933 0); 934 935 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 936 DAG.getConstant(16, MVT::i32)); 937 OutChains[4] = DAG.getStore(Chain, dl, FPtr, Addr, 938 MachinePointerInfo(TrmpAddr, 16), false, false, 939 0); 940 941 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains); 942 } 943 944 SDValue XCoreTargetLowering:: 945 LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const { 946 SDLoc DL(Op); 947 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 948 switch (IntNo) { 949 case Intrinsic::xcore_crc8: 950 EVT VT = Op.getValueType(); 951 SDValue Data = 952 DAG.getNode(XCoreISD::CRC8, DL, DAG.getVTList(VT, VT), 953 Op.getOperand(1), Op.getOperand(2) , Op.getOperand(3)); 954 SDValue Crc(Data.getNode(), 1); 955 SDValue Results[] = { Crc, Data }; 956 return DAG.getMergeValues(Results, DL); 957 } 958 return SDValue(); 959 } 960 961 SDValue XCoreTargetLowering:: 962 LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const { 963 SDLoc DL(Op); 964 return DAG.getNode(XCoreISD::MEMBARRIER, DL, MVT::Other, Op.getOperand(0)); 965 } 966 967 SDValue XCoreTargetLowering:: 968 LowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const { 969 AtomicSDNode *N = cast<AtomicSDNode>(Op); 970 assert(N->getOpcode() == ISD::ATOMIC_LOAD && "Bad Atomic OP"); 971 assert(N->getOrdering() <= Monotonic && 972 "setInsertFencesForAtomic(true) and yet greater than Monotonic"); 973 if (N->getMemoryVT() == MVT::i32) { 974 if (N->getAlignment() < 4) 975 report_fatal_error("atomic load must be aligned"); 976 return DAG.getLoad(getPointerTy(), SDLoc(Op), N->getChain(), 977 N->getBasePtr(), N->getPointerInfo(), 978 N->isVolatile(), N->isNonTemporal(), 979 N->isInvariant(), N->getAlignment(), 980 N->getAAInfo(), N->getRanges()); 981 } 982 if (N->getMemoryVT() == MVT::i16) { 983 if (N->getAlignment() < 2) 984 report_fatal_error("atomic load must be aligned"); 985 return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), MVT::i32, N->getChain(), 986 N->getBasePtr(), N->getPointerInfo(), MVT::i16, 987 N->isVolatile(), N->isNonTemporal(), 988 N->isInvariant(), N->getAlignment(), N->getAAInfo()); 989 } 990 if (N->getMemoryVT() == MVT::i8) 991 return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), MVT::i32, N->getChain(), 992 N->getBasePtr(), N->getPointerInfo(), MVT::i8, 993 N->isVolatile(), N->isNonTemporal(), 994 N->isInvariant(), N->getAlignment(), N->getAAInfo()); 995 return SDValue(); 996 } 997 998 SDValue XCoreTargetLowering:: 999 LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const { 1000 AtomicSDNode *N = cast<AtomicSDNode>(Op); 1001 assert(N->getOpcode() == ISD::ATOMIC_STORE && "Bad Atomic OP"); 1002 assert(N->getOrdering() <= Monotonic && 1003 "setInsertFencesForAtomic(true) and yet greater than Monotonic"); 1004 if (N->getMemoryVT() == MVT::i32) { 1005 if (N->getAlignment() < 4) 1006 report_fatal_error("atomic store must be aligned"); 1007 return DAG.getStore(N->getChain(), SDLoc(Op), N->getVal(), 1008 N->getBasePtr(), N->getPointerInfo(), 1009 N->isVolatile(), N->isNonTemporal(), 1010 N->getAlignment(), N->getAAInfo()); 1011 } 1012 if (N->getMemoryVT() == MVT::i16) { 1013 if (N->getAlignment() < 2) 1014 report_fatal_error("atomic store must be aligned"); 1015 return DAG.getTruncStore(N->getChain(), SDLoc(Op), N->getVal(), 1016 N->getBasePtr(), N->getPointerInfo(), MVT::i16, 1017 N->isVolatile(), N->isNonTemporal(), 1018 N->getAlignment(), N->getAAInfo()); 1019 } 1020 if (N->getMemoryVT() == MVT::i8) 1021 return DAG.getTruncStore(N->getChain(), SDLoc(Op), N->getVal(), 1022 N->getBasePtr(), N->getPointerInfo(), MVT::i8, 1023 N->isVolatile(), N->isNonTemporal(), 1024 N->getAlignment(), N->getAAInfo()); 1025 return SDValue(); 1026 } 1027 1028 //===----------------------------------------------------------------------===// 1029 // Calling Convention Implementation 1030 //===----------------------------------------------------------------------===// 1031 1032 #include "XCoreGenCallingConv.inc" 1033 1034 //===----------------------------------------------------------------------===// 1035 // Call Calling Convention Implementation 1036 //===----------------------------------------------------------------------===// 1037 1038 /// XCore call implementation 1039 SDValue 1040 XCoreTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 1041 SmallVectorImpl<SDValue> &InVals) const { 1042 SelectionDAG &DAG = CLI.DAG; 1043 SDLoc &dl = CLI.DL; 1044 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; 1045 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; 1046 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; 1047 SDValue Chain = CLI.Chain; 1048 SDValue Callee = CLI.Callee; 1049 bool &isTailCall = CLI.IsTailCall; 1050 CallingConv::ID CallConv = CLI.CallConv; 1051 bool isVarArg = CLI.IsVarArg; 1052 1053 // XCore target does not yet support tail call optimization. 1054 isTailCall = false; 1055 1056 // For now, only CallingConv::C implemented 1057 switch (CallConv) 1058 { 1059 default: 1060 llvm_unreachable("Unsupported calling convention"); 1061 case CallingConv::Fast: 1062 case CallingConv::C: 1063 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall, 1064 Outs, OutVals, Ins, dl, DAG, InVals); 1065 } 1066 } 1067 1068 /// LowerCallResult - Lower the result values of a call into the 1069 /// appropriate copies out of appropriate physical registers / memory locations. 1070 static SDValue 1071 LowerCallResult(SDValue Chain, SDValue InFlag, 1072 const SmallVectorImpl<CCValAssign> &RVLocs, 1073 SDLoc dl, SelectionDAG &DAG, 1074 SmallVectorImpl<SDValue> &InVals) { 1075 SmallVector<std::pair<int, unsigned>, 4> ResultMemLocs; 1076 // Copy results out of physical registers. 1077 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 1078 const CCValAssign &VA = RVLocs[i]; 1079 if (VA.isRegLoc()) { 1080 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getValVT(), 1081 InFlag).getValue(1); 1082 InFlag = Chain.getValue(2); 1083 InVals.push_back(Chain.getValue(0)); 1084 } else { 1085 assert(VA.isMemLoc()); 1086 ResultMemLocs.push_back(std::make_pair(VA.getLocMemOffset(), 1087 InVals.size())); 1088 // Reserve space for this result. 1089 InVals.push_back(SDValue()); 1090 } 1091 } 1092 1093 // Copy results out of memory. 1094 SmallVector<SDValue, 4> MemOpChains; 1095 for (unsigned i = 0, e = ResultMemLocs.size(); i != e; ++i) { 1096 int offset = ResultMemLocs[i].first; 1097 unsigned index = ResultMemLocs[i].second; 1098 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other); 1099 SDValue Ops[] = { Chain, DAG.getConstant(offset / 4, MVT::i32) }; 1100 SDValue load = DAG.getNode(XCoreISD::LDWSP, dl, VTs, Ops); 1101 InVals[index] = load; 1102 MemOpChains.push_back(load.getValue(1)); 1103 } 1104 1105 // Transform all loads nodes into one single node because 1106 // all load nodes are independent of each other. 1107 if (!MemOpChains.empty()) 1108 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); 1109 1110 return Chain; 1111 } 1112 1113 /// LowerCCCCallTo - functions arguments are copied from virtual 1114 /// regs to (physical regs)/(stack frame), CALLSEQ_START and 1115 /// CALLSEQ_END are emitted. 1116 /// TODO: isTailCall, sret. 1117 SDValue 1118 XCoreTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee, 1119 CallingConv::ID CallConv, bool isVarArg, 1120 bool isTailCall, 1121 const SmallVectorImpl<ISD::OutputArg> &Outs, 1122 const SmallVectorImpl<SDValue> &OutVals, 1123 const SmallVectorImpl<ISD::InputArg> &Ins, 1124 SDLoc dl, SelectionDAG &DAG, 1125 SmallVectorImpl<SDValue> &InVals) const { 1126 1127 // Analyze operands of the call, assigning locations to each operand. 1128 SmallVector<CCValAssign, 16> ArgLocs; 1129 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, 1130 *DAG.getContext()); 1131 1132 // The ABI dictates there should be one stack slot available to the callee 1133 // on function entry (for saving lr). 1134 CCInfo.AllocateStack(4, 4); 1135 1136 CCInfo.AnalyzeCallOperands(Outs, CC_XCore); 1137 1138 SmallVector<CCValAssign, 16> RVLocs; 1139 // Analyze return values to determine the number of bytes of stack required. 1140 CCState RetCCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, 1141 *DAG.getContext()); 1142 RetCCInfo.AllocateStack(CCInfo.getNextStackOffset(), 4); 1143 RetCCInfo.AnalyzeCallResult(Ins, RetCC_XCore); 1144 1145 // Get a count of how many bytes are to be pushed on the stack. 1146 unsigned NumBytes = RetCCInfo.getNextStackOffset(); 1147 1148 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, 1149 getPointerTy(), true), dl); 1150 1151 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass; 1152 SmallVector<SDValue, 12> MemOpChains; 1153 1154 // Walk the register/memloc assignments, inserting copies/loads. 1155 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1156 CCValAssign &VA = ArgLocs[i]; 1157 SDValue Arg = OutVals[i]; 1158 1159 // Promote the value if needed. 1160 switch (VA.getLocInfo()) { 1161 default: llvm_unreachable("Unknown loc info!"); 1162 case CCValAssign::Full: break; 1163 case CCValAssign::SExt: 1164 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 1165 break; 1166 case CCValAssign::ZExt: 1167 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 1168 break; 1169 case CCValAssign::AExt: 1170 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 1171 break; 1172 } 1173 1174 // Arguments that can be passed on register must be kept at 1175 // RegsToPass vector 1176 if (VA.isRegLoc()) { 1177 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 1178 } else { 1179 assert(VA.isMemLoc()); 1180 1181 int Offset = VA.getLocMemOffset(); 1182 1183 MemOpChains.push_back(DAG.getNode(XCoreISD::STWSP, dl, MVT::Other, 1184 Chain, Arg, 1185 DAG.getConstant(Offset/4, MVT::i32))); 1186 } 1187 } 1188 1189 // Transform all store nodes into one single node because 1190 // all store nodes are independent of each other. 1191 if (!MemOpChains.empty()) 1192 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); 1193 1194 // Build a sequence of copy-to-reg nodes chained together with token 1195 // chain and flag operands which copy the outgoing args into registers. 1196 // The InFlag in necessary since all emitted instructions must be 1197 // stuck together. 1198 SDValue InFlag; 1199 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1200 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 1201 RegsToPass[i].second, InFlag); 1202 InFlag = Chain.getValue(1); 1203 } 1204 1205 // If the callee is a GlobalAddress node (quite common, every direct call is) 1206 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 1207 // Likewise ExternalSymbol -> TargetExternalSymbol. 1208 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 1209 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32); 1210 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 1211 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32); 1212 1213 // XCoreBranchLink = #chain, #target_address, #opt_in_flags... 1214 // = Chain, Callee, Reg#1, Reg#2, ... 1215 // 1216 // Returns a chain & a flag for retval copy to use. 1217 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 1218 SmallVector<SDValue, 8> Ops; 1219 Ops.push_back(Chain); 1220 Ops.push_back(Callee); 1221 1222 // Add argument registers to the end of the list so that they are 1223 // known live into the call. 1224 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1225 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 1226 RegsToPass[i].second.getValueType())); 1227 1228 if (InFlag.getNode()) 1229 Ops.push_back(InFlag); 1230 1231 Chain = DAG.getNode(XCoreISD::BL, dl, NodeTys, Ops); 1232 InFlag = Chain.getValue(1); 1233 1234 // Create the CALLSEQ_END node. 1235 Chain = DAG.getCALLSEQ_END(Chain, 1236 DAG.getConstant(NumBytes, getPointerTy(), true), 1237 DAG.getConstant(0, getPointerTy(), true), 1238 InFlag, dl); 1239 InFlag = Chain.getValue(1); 1240 1241 // Handle result values, copying them out of physregs into vregs that we 1242 // return. 1243 return LowerCallResult(Chain, InFlag, RVLocs, dl, DAG, InVals); 1244 } 1245 1246 //===----------------------------------------------------------------------===// 1247 // Formal Arguments Calling Convention Implementation 1248 //===----------------------------------------------------------------------===// 1249 1250 namespace { 1251 struct ArgDataPair { SDValue SDV; ISD::ArgFlagsTy Flags; }; 1252 } 1253 1254 /// XCore formal arguments implementation 1255 SDValue 1256 XCoreTargetLowering::LowerFormalArguments(SDValue Chain, 1257 CallingConv::ID CallConv, 1258 bool isVarArg, 1259 const SmallVectorImpl<ISD::InputArg> &Ins, 1260 SDLoc dl, 1261 SelectionDAG &DAG, 1262 SmallVectorImpl<SDValue> &InVals) 1263 const { 1264 switch (CallConv) 1265 { 1266 default: 1267 llvm_unreachable("Unsupported calling convention"); 1268 case CallingConv::C: 1269 case CallingConv::Fast: 1270 return LowerCCCArguments(Chain, CallConv, isVarArg, 1271 Ins, dl, DAG, InVals); 1272 } 1273 } 1274 1275 /// LowerCCCArguments - transform physical registers into 1276 /// virtual registers and generate load operations for 1277 /// arguments places on the stack. 1278 /// TODO: sret 1279 SDValue 1280 XCoreTargetLowering::LowerCCCArguments(SDValue Chain, 1281 CallingConv::ID CallConv, 1282 bool isVarArg, 1283 const SmallVectorImpl<ISD::InputArg> 1284 &Ins, 1285 SDLoc dl, 1286 SelectionDAG &DAG, 1287 SmallVectorImpl<SDValue> &InVals) const { 1288 MachineFunction &MF = DAG.getMachineFunction(); 1289 MachineFrameInfo *MFI = MF.getFrameInfo(); 1290 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 1291 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>(); 1292 1293 // Assign locations to all of the incoming arguments. 1294 SmallVector<CCValAssign, 16> ArgLocs; 1295 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, 1296 *DAG.getContext()); 1297 1298 CCInfo.AnalyzeFormalArguments(Ins, CC_XCore); 1299 1300 unsigned StackSlotSize = XCoreFrameLowering::stackSlotSize(); 1301 1302 unsigned LRSaveSize = StackSlotSize; 1303 1304 if (!isVarArg) 1305 XFI->setReturnStackOffset(CCInfo.getNextStackOffset() + LRSaveSize); 1306 1307 // All getCopyFromReg ops must precede any getMemcpys to prevent the 1308 // scheduler clobbering a register before it has been copied. 1309 // The stages are: 1310 // 1. CopyFromReg (and load) arg & vararg registers. 1311 // 2. Chain CopyFromReg nodes into a TokenFactor. 1312 // 3. Memcpy 'byVal' args & push final InVals. 1313 // 4. Chain mem ops nodes into a TokenFactor. 1314 SmallVector<SDValue, 4> CFRegNode; 1315 SmallVector<ArgDataPair, 4> ArgData; 1316 SmallVector<SDValue, 4> MemOps; 1317 1318 // 1a. CopyFromReg (and load) arg registers. 1319 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1320 1321 CCValAssign &VA = ArgLocs[i]; 1322 SDValue ArgIn; 1323 1324 if (VA.isRegLoc()) { 1325 // Arguments passed in registers 1326 EVT RegVT = VA.getLocVT(); 1327 switch (RegVT.getSimpleVT().SimpleTy) { 1328 default: 1329 { 1330 #ifndef NDEBUG 1331 errs() << "LowerFormalArguments Unhandled argument type: " 1332 << RegVT.getSimpleVT().SimpleTy << "\n"; 1333 #endif 1334 llvm_unreachable(nullptr); 1335 } 1336 case MVT::i32: 1337 unsigned VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass); 1338 RegInfo.addLiveIn(VA.getLocReg(), VReg); 1339 ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); 1340 CFRegNode.push_back(ArgIn.getValue(ArgIn->getNumValues() - 1)); 1341 } 1342 } else { 1343 // sanity check 1344 assert(VA.isMemLoc()); 1345 // Load the argument to a virtual register 1346 unsigned ObjSize = VA.getLocVT().getSizeInBits()/8; 1347 if (ObjSize > StackSlotSize) { 1348 errs() << "LowerFormalArguments Unhandled argument type: " 1349 << EVT(VA.getLocVT()).getEVTString() 1350 << "\n"; 1351 } 1352 // Create the frame index object for this incoming parameter... 1353 int FI = MFI->CreateFixedObject(ObjSize, 1354 LRSaveSize + VA.getLocMemOffset(), 1355 true); 1356 1357 // Create the SelectionDAG nodes corresponding to a load 1358 //from this parameter 1359 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); 1360 ArgIn = DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, 1361 MachinePointerInfo::getFixedStack(FI), 1362 false, false, false, 0); 1363 } 1364 const ArgDataPair ADP = { ArgIn, Ins[i].Flags }; 1365 ArgData.push_back(ADP); 1366 } 1367 1368 // 1b. CopyFromReg vararg registers. 1369 if (isVarArg) { 1370 // Argument registers 1371 static const MCPhysReg ArgRegs[] = { 1372 XCore::R0, XCore::R1, XCore::R2, XCore::R3 1373 }; 1374 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>(); 1375 unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs); 1376 if (FirstVAReg < array_lengthof(ArgRegs)) { 1377 int offset = 0; 1378 // Save remaining registers, storing higher register numbers at a higher 1379 // address 1380 for (int i = array_lengthof(ArgRegs) - 1; i >= (int)FirstVAReg; --i) { 1381 // Create a stack slot 1382 int FI = MFI->CreateFixedObject(4, offset, true); 1383 if (i == (int)FirstVAReg) { 1384 XFI->setVarArgsFrameIndex(FI); 1385 } 1386 offset -= StackSlotSize; 1387 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); 1388 // Move argument from phys reg -> virt reg 1389 unsigned VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass); 1390 RegInfo.addLiveIn(ArgRegs[i], VReg); 1391 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); 1392 CFRegNode.push_back(Val.getValue(Val->getNumValues() - 1)); 1393 // Move argument from virt reg -> stack 1394 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, 1395 MachinePointerInfo(), false, false, 0); 1396 MemOps.push_back(Store); 1397 } 1398 } else { 1399 // This will point to the next argument passed via stack. 1400 XFI->setVarArgsFrameIndex( 1401 MFI->CreateFixedObject(4, LRSaveSize + CCInfo.getNextStackOffset(), 1402 true)); 1403 } 1404 } 1405 1406 // 2. chain CopyFromReg nodes into a TokenFactor. 1407 if (!CFRegNode.empty()) 1408 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, CFRegNode); 1409 1410 // 3. Memcpy 'byVal' args & push final InVals. 1411 // Aggregates passed "byVal" need to be copied by the callee. 1412 // The callee will use a pointer to this copy, rather than the original 1413 // pointer. 1414 for (SmallVectorImpl<ArgDataPair>::const_iterator ArgDI = ArgData.begin(), 1415 ArgDE = ArgData.end(); 1416 ArgDI != ArgDE; ++ArgDI) { 1417 if (ArgDI->Flags.isByVal() && ArgDI->Flags.getByValSize()) { 1418 unsigned Size = ArgDI->Flags.getByValSize(); 1419 unsigned Align = std::max(StackSlotSize, ArgDI->Flags.getByValAlign()); 1420 // Create a new object on the stack and copy the pointee into it. 1421 int FI = MFI->CreateStackObject(Size, Align, false); 1422 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); 1423 InVals.push_back(FIN); 1424 MemOps.push_back(DAG.getMemcpy(Chain, dl, FIN, ArgDI->SDV, 1425 DAG.getConstant(Size, MVT::i32), 1426 Align, false, false, false, 1427 MachinePointerInfo(), 1428 MachinePointerInfo())); 1429 } else { 1430 InVals.push_back(ArgDI->SDV); 1431 } 1432 } 1433 1434 // 4, chain mem ops nodes into a TokenFactor. 1435 if (!MemOps.empty()) { 1436 MemOps.push_back(Chain); 1437 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps); 1438 } 1439 1440 return Chain; 1441 } 1442 1443 //===----------------------------------------------------------------------===// 1444 // Return Value Calling Convention Implementation 1445 //===----------------------------------------------------------------------===// 1446 1447 bool XCoreTargetLowering:: 1448 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 1449 bool isVarArg, 1450 const SmallVectorImpl<ISD::OutputArg> &Outs, 1451 LLVMContext &Context) const { 1452 SmallVector<CCValAssign, 16> RVLocs; 1453 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context); 1454 if (!CCInfo.CheckReturn(Outs, RetCC_XCore)) 1455 return false; 1456 if (CCInfo.getNextStackOffset() != 0 && isVarArg) 1457 return false; 1458 return true; 1459 } 1460 1461 SDValue 1462 XCoreTargetLowering::LowerReturn(SDValue Chain, 1463 CallingConv::ID CallConv, bool isVarArg, 1464 const SmallVectorImpl<ISD::OutputArg> &Outs, 1465 const SmallVectorImpl<SDValue> &OutVals, 1466 SDLoc dl, SelectionDAG &DAG) const { 1467 1468 XCoreFunctionInfo *XFI = 1469 DAG.getMachineFunction().getInfo<XCoreFunctionInfo>(); 1470 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1471 1472 // CCValAssign - represent the assignment of 1473 // the return value to a location 1474 SmallVector<CCValAssign, 16> RVLocs; 1475 1476 // CCState - Info about the registers and stack slot. 1477 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, 1478 *DAG.getContext()); 1479 1480 // Analyze return values. 1481 if (!isVarArg) 1482 CCInfo.AllocateStack(XFI->getReturnStackOffset(), 4); 1483 1484 CCInfo.AnalyzeReturn(Outs, RetCC_XCore); 1485 1486 SDValue Flag; 1487 SmallVector<SDValue, 4> RetOps(1, Chain); 1488 1489 // Return on XCore is always a "retsp 0" 1490 RetOps.push_back(DAG.getConstant(0, MVT::i32)); 1491 1492 SmallVector<SDValue, 4> MemOpChains; 1493 // Handle return values that must be copied to memory. 1494 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 1495 CCValAssign &VA = RVLocs[i]; 1496 if (VA.isRegLoc()) 1497 continue; 1498 assert(VA.isMemLoc()); 1499 if (isVarArg) { 1500 report_fatal_error("Can't return value from vararg function in memory"); 1501 } 1502 1503 int Offset = VA.getLocMemOffset(); 1504 unsigned ObjSize = VA.getLocVT().getSizeInBits() / 8; 1505 // Create the frame index object for the memory location. 1506 int FI = MFI->CreateFixedObject(ObjSize, Offset, false); 1507 1508 // Create a SelectionDAG node corresponding to a store 1509 // to this memory location. 1510 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); 1511 MemOpChains.push_back(DAG.getStore(Chain, dl, OutVals[i], FIN, 1512 MachinePointerInfo::getFixedStack(FI), false, false, 1513 0)); 1514 } 1515 1516 // Transform all store nodes into one single node because 1517 // all stores are independent of each other. 1518 if (!MemOpChains.empty()) 1519 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); 1520 1521 // Now handle return values copied to registers. 1522 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 1523 CCValAssign &VA = RVLocs[i]; 1524 if (!VA.isRegLoc()) 1525 continue; 1526 // Copy the result values into the output registers. 1527 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); 1528 1529 // guarantee that all emitted copies are 1530 // stuck together, avoiding something bad 1531 Flag = Chain.getValue(1); 1532 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 1533 } 1534 1535 RetOps[0] = Chain; // Update chain. 1536 1537 // Add the flag if we have it. 1538 if (Flag.getNode()) 1539 RetOps.push_back(Flag); 1540 1541 return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other, RetOps); 1542 } 1543 1544 //===----------------------------------------------------------------------===// 1545 // Other Lowering Code 1546 //===----------------------------------------------------------------------===// 1547 1548 MachineBasicBlock * 1549 XCoreTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 1550 MachineBasicBlock *BB) const { 1551 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 1552 DebugLoc dl = MI->getDebugLoc(); 1553 assert((MI->getOpcode() == XCore::SELECT_CC) && 1554 "Unexpected instr type to insert"); 1555 1556 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 1557 // control-flow pattern. The incoming instruction knows the destination vreg 1558 // to set, the condition code register to branch on, the true/false values to 1559 // select between, and a branch opcode to use. 1560 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1561 MachineFunction::iterator It = BB; 1562 ++It; 1563 1564 // thisMBB: 1565 // ... 1566 // TrueVal = ... 1567 // cmpTY ccX, r1, r2 1568 // bCC copy1MBB 1569 // fallthrough --> copy0MBB 1570 MachineBasicBlock *thisMBB = BB; 1571 MachineFunction *F = BB->getParent(); 1572 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 1573 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 1574 F->insert(It, copy0MBB); 1575 F->insert(It, sinkMBB); 1576 1577 // Transfer the remainder of BB and its successor edges to sinkMBB. 1578 sinkMBB->splice(sinkMBB->begin(), BB, 1579 std::next(MachineBasicBlock::iterator(MI)), BB->end()); 1580 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 1581 1582 // Next, add the true and fallthrough blocks as its successors. 1583 BB->addSuccessor(copy0MBB); 1584 BB->addSuccessor(sinkMBB); 1585 1586 BuildMI(BB, dl, TII.get(XCore::BRFT_lru6)) 1587 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB); 1588 1589 // copy0MBB: 1590 // %FalseValue = ... 1591 // # fallthrough to sinkMBB 1592 BB = copy0MBB; 1593 1594 // Update machine-CFG edges 1595 BB->addSuccessor(sinkMBB); 1596 1597 // sinkMBB: 1598 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 1599 // ... 1600 BB = sinkMBB; 1601 BuildMI(*BB, BB->begin(), dl, 1602 TII.get(XCore::PHI), MI->getOperand(0).getReg()) 1603 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB) 1604 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 1605 1606 MI->eraseFromParent(); // The pseudo instruction is gone now. 1607 return BB; 1608 } 1609 1610 //===----------------------------------------------------------------------===// 1611 // Target Optimization Hooks 1612 //===----------------------------------------------------------------------===// 1613 1614 SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N, 1615 DAGCombinerInfo &DCI) const { 1616 SelectionDAG &DAG = DCI.DAG; 1617 SDLoc dl(N); 1618 switch (N->getOpcode()) { 1619 default: break; 1620 case ISD::INTRINSIC_VOID: 1621 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) { 1622 case Intrinsic::xcore_outt: 1623 case Intrinsic::xcore_outct: 1624 case Intrinsic::xcore_chkct: { 1625 SDValue OutVal = N->getOperand(3); 1626 // These instructions ignore the high bits. 1627 if (OutVal.hasOneUse()) { 1628 unsigned BitWidth = OutVal.getValueSizeInBits(); 1629 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, 8); 1630 APInt KnownZero, KnownOne; 1631 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), 1632 !DCI.isBeforeLegalizeOps()); 1633 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 1634 if (TLO.ShrinkDemandedConstant(OutVal, DemandedMask) || 1635 TLI.SimplifyDemandedBits(OutVal, DemandedMask, KnownZero, KnownOne, 1636 TLO)) 1637 DCI.CommitTargetLoweringOpt(TLO); 1638 } 1639 break; 1640 } 1641 case Intrinsic::xcore_setpt: { 1642 SDValue Time = N->getOperand(3); 1643 // This instruction ignores the high bits. 1644 if (Time.hasOneUse()) { 1645 unsigned BitWidth = Time.getValueSizeInBits(); 1646 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, 16); 1647 APInt KnownZero, KnownOne; 1648 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), 1649 !DCI.isBeforeLegalizeOps()); 1650 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 1651 if (TLO.ShrinkDemandedConstant(Time, DemandedMask) || 1652 TLI.SimplifyDemandedBits(Time, DemandedMask, KnownZero, KnownOne, 1653 TLO)) 1654 DCI.CommitTargetLoweringOpt(TLO); 1655 } 1656 break; 1657 } 1658 } 1659 break; 1660 case XCoreISD::LADD: { 1661 SDValue N0 = N->getOperand(0); 1662 SDValue N1 = N->getOperand(1); 1663 SDValue N2 = N->getOperand(2); 1664 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1665 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1666 EVT VT = N0.getValueType(); 1667 1668 // canonicalize constant to RHS 1669 if (N0C && !N1C) 1670 return DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N1, N0, N2); 1671 1672 // fold (ladd 0, 0, x) -> 0, x & 1 1673 if (N0C && N0C->isNullValue() && N1C && N1C->isNullValue()) { 1674 SDValue Carry = DAG.getConstant(0, VT); 1675 SDValue Result = DAG.getNode(ISD::AND, dl, VT, N2, 1676 DAG.getConstant(1, VT)); 1677 SDValue Ops[] = { Result, Carry }; 1678 return DAG.getMergeValues(Ops, dl); 1679 } 1680 1681 // fold (ladd x, 0, y) -> 0, add x, y iff carry is unused and y has only the 1682 // low bit set 1683 if (N1C && N1C->isNullValue() && N->hasNUsesOfValue(0, 1)) { 1684 APInt KnownZero, KnownOne; 1685 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), 1686 VT.getSizeInBits() - 1); 1687 DAG.computeKnownBits(N2, KnownZero, KnownOne); 1688 if ((KnownZero & Mask) == Mask) { 1689 SDValue Carry = DAG.getConstant(0, VT); 1690 SDValue Result = DAG.getNode(ISD::ADD, dl, VT, N0, N2); 1691 SDValue Ops[] = { Result, Carry }; 1692 return DAG.getMergeValues(Ops, dl); 1693 } 1694 } 1695 } 1696 break; 1697 case XCoreISD::LSUB: { 1698 SDValue N0 = N->getOperand(0); 1699 SDValue N1 = N->getOperand(1); 1700 SDValue N2 = N->getOperand(2); 1701 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1702 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1703 EVT VT = N0.getValueType(); 1704 1705 // fold (lsub 0, 0, x) -> x, -x iff x has only the low bit set 1706 if (N0C && N0C->isNullValue() && N1C && N1C->isNullValue()) { 1707 APInt KnownZero, KnownOne; 1708 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), 1709 VT.getSizeInBits() - 1); 1710 DAG.computeKnownBits(N2, KnownZero, KnownOne); 1711 if ((KnownZero & Mask) == Mask) { 1712 SDValue Borrow = N2; 1713 SDValue Result = DAG.getNode(ISD::SUB, dl, VT, 1714 DAG.getConstant(0, VT), N2); 1715 SDValue Ops[] = { Result, Borrow }; 1716 return DAG.getMergeValues(Ops, dl); 1717 } 1718 } 1719 1720 // fold (lsub x, 0, y) -> 0, sub x, y iff borrow is unused and y has only the 1721 // low bit set 1722 if (N1C && N1C->isNullValue() && N->hasNUsesOfValue(0, 1)) { 1723 APInt KnownZero, KnownOne; 1724 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), 1725 VT.getSizeInBits() - 1); 1726 DAG.computeKnownBits(N2, KnownZero, KnownOne); 1727 if ((KnownZero & Mask) == Mask) { 1728 SDValue Borrow = DAG.getConstant(0, VT); 1729 SDValue Result = DAG.getNode(ISD::SUB, dl, VT, N0, N2); 1730 SDValue Ops[] = { Result, Borrow }; 1731 return DAG.getMergeValues(Ops, dl); 1732 } 1733 } 1734 } 1735 break; 1736 case XCoreISD::LMUL: { 1737 SDValue N0 = N->getOperand(0); 1738 SDValue N1 = N->getOperand(1); 1739 SDValue N2 = N->getOperand(2); 1740 SDValue N3 = N->getOperand(3); 1741 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1742 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1743 EVT VT = N0.getValueType(); 1744 // Canonicalize multiplicative constant to RHS. If both multiplicative 1745 // operands are constant canonicalize smallest to RHS. 1746 if ((N0C && !N1C) || 1747 (N0C && N1C && N0C->getZExtValue() < N1C->getZExtValue())) 1748 return DAG.getNode(XCoreISD::LMUL, dl, DAG.getVTList(VT, VT), 1749 N1, N0, N2, N3); 1750 1751 // lmul(x, 0, a, b) 1752 if (N1C && N1C->isNullValue()) { 1753 // If the high result is unused fold to add(a, b) 1754 if (N->hasNUsesOfValue(0, 0)) { 1755 SDValue Lo = DAG.getNode(ISD::ADD, dl, VT, N2, N3); 1756 SDValue Ops[] = { Lo, Lo }; 1757 return DAG.getMergeValues(Ops, dl); 1758 } 1759 // Otherwise fold to ladd(a, b, 0) 1760 SDValue Result = 1761 DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N2, N3, N1); 1762 SDValue Carry(Result.getNode(), 1); 1763 SDValue Ops[] = { Carry, Result }; 1764 return DAG.getMergeValues(Ops, dl); 1765 } 1766 } 1767 break; 1768 case ISD::ADD: { 1769 // Fold 32 bit expressions such as add(add(mul(x,y),a),b) -> 1770 // lmul(x, y, a, b). The high result of lmul will be ignored. 1771 // This is only profitable if the intermediate results are unused 1772 // elsewhere. 1773 SDValue Mul0, Mul1, Addend0, Addend1; 1774 if (N->getValueType(0) == MVT::i32 && 1775 isADDADDMUL(SDValue(N, 0), Mul0, Mul1, Addend0, Addend1, true)) { 1776 SDValue Ignored = DAG.getNode(XCoreISD::LMUL, dl, 1777 DAG.getVTList(MVT::i32, MVT::i32), Mul0, 1778 Mul1, Addend0, Addend1); 1779 SDValue Result(Ignored.getNode(), 1); 1780 return Result; 1781 } 1782 APInt HighMask = APInt::getHighBitsSet(64, 32); 1783 // Fold 64 bit expression such as add(add(mul(x,y),a),b) -> 1784 // lmul(x, y, a, b) if all operands are zero-extended. We do this 1785 // before type legalization as it is messy to match the operands after 1786 // that. 1787 if (N->getValueType(0) == MVT::i64 && 1788 isADDADDMUL(SDValue(N, 0), Mul0, Mul1, Addend0, Addend1, false) && 1789 DAG.MaskedValueIsZero(Mul0, HighMask) && 1790 DAG.MaskedValueIsZero(Mul1, HighMask) && 1791 DAG.MaskedValueIsZero(Addend0, HighMask) && 1792 DAG.MaskedValueIsZero(Addend1, HighMask)) { 1793 SDValue Mul0L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 1794 Mul0, DAG.getConstant(0, MVT::i32)); 1795 SDValue Mul1L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 1796 Mul1, DAG.getConstant(0, MVT::i32)); 1797 SDValue Addend0L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 1798 Addend0, DAG.getConstant(0, MVT::i32)); 1799 SDValue Addend1L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 1800 Addend1, DAG.getConstant(0, MVT::i32)); 1801 SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl, 1802 DAG.getVTList(MVT::i32, MVT::i32), Mul0L, Mul1L, 1803 Addend0L, Addend1L); 1804 SDValue Lo(Hi.getNode(), 1); 1805 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); 1806 } 1807 } 1808 break; 1809 case ISD::STORE: { 1810 // Replace unaligned store of unaligned load with memmove. 1811 StoreSDNode *ST = cast<StoreSDNode>(N); 1812 if (!DCI.isBeforeLegalize() || 1813 allowsMisalignedMemoryAccesses(ST->getMemoryVT(), 1814 ST->getAddressSpace(), 1815 ST->getAlignment()) || 1816 ST->isVolatile() || ST->isIndexed()) { 1817 break; 1818 } 1819 SDValue Chain = ST->getChain(); 1820 1821 unsigned StoreBits = ST->getMemoryVT().getStoreSizeInBits(); 1822 if (StoreBits % 8) { 1823 break; 1824 } 1825 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment( 1826 ST->getMemoryVT().getTypeForEVT(*DCI.DAG.getContext())); 1827 unsigned Alignment = ST->getAlignment(); 1828 if (Alignment >= ABIAlignment) { 1829 break; 1830 } 1831 1832 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(ST->getValue())) { 1833 if (LD->hasNUsesOfValue(1, 0) && ST->getMemoryVT() == LD->getMemoryVT() && 1834 LD->getAlignment() == Alignment && 1835 !LD->isVolatile() && !LD->isIndexed() && 1836 Chain.reachesChainWithoutSideEffects(SDValue(LD, 1))) { 1837 bool isTail = isInTailCallPosition(DAG, ST, Chain); 1838 return DAG.getMemmove(Chain, dl, ST->getBasePtr(), 1839 LD->getBasePtr(), 1840 DAG.getConstant(StoreBits/8, MVT::i32), 1841 Alignment, false, isTail, ST->getPointerInfo(), 1842 LD->getPointerInfo()); 1843 } 1844 } 1845 break; 1846 } 1847 } 1848 return SDValue(); 1849 } 1850 1851 void XCoreTargetLowering::computeKnownBitsForTargetNode(const SDValue Op, 1852 APInt &KnownZero, 1853 APInt &KnownOne, 1854 const SelectionDAG &DAG, 1855 unsigned Depth) const { 1856 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0); 1857 switch (Op.getOpcode()) { 1858 default: break; 1859 case XCoreISD::LADD: 1860 case XCoreISD::LSUB: 1861 if (Op.getResNo() == 1) { 1862 // Top bits of carry / borrow are clear. 1863 KnownZero = APInt::getHighBitsSet(KnownZero.getBitWidth(), 1864 KnownZero.getBitWidth() - 1); 1865 } 1866 break; 1867 case ISD::INTRINSIC_W_CHAIN: 1868 { 1869 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 1870 switch (IntNo) { 1871 case Intrinsic::xcore_getts: 1872 // High bits are known to be zero. 1873 KnownZero = APInt::getHighBitsSet(KnownZero.getBitWidth(), 1874 KnownZero.getBitWidth() - 16); 1875 break; 1876 case Intrinsic::xcore_int: 1877 case Intrinsic::xcore_inct: 1878 // High bits are known to be zero. 1879 KnownZero = APInt::getHighBitsSet(KnownZero.getBitWidth(), 1880 KnownZero.getBitWidth() - 8); 1881 break; 1882 case Intrinsic::xcore_testct: 1883 // Result is either 0 or 1. 1884 KnownZero = APInt::getHighBitsSet(KnownZero.getBitWidth(), 1885 KnownZero.getBitWidth() - 1); 1886 break; 1887 case Intrinsic::xcore_testwct: 1888 // Result is in the range 0 - 4. 1889 KnownZero = APInt::getHighBitsSet(KnownZero.getBitWidth(), 1890 KnownZero.getBitWidth() - 3); 1891 break; 1892 } 1893 } 1894 break; 1895 } 1896 } 1897 1898 //===----------------------------------------------------------------------===// 1899 // Addressing mode description hooks 1900 //===----------------------------------------------------------------------===// 1901 1902 static inline bool isImmUs(int64_t val) 1903 { 1904 return (val >= 0 && val <= 11); 1905 } 1906 1907 static inline bool isImmUs2(int64_t val) 1908 { 1909 return (val%2 == 0 && isImmUs(val/2)); 1910 } 1911 1912 static inline bool isImmUs4(int64_t val) 1913 { 1914 return (val%4 == 0 && isImmUs(val/4)); 1915 } 1916 1917 /// isLegalAddressingMode - Return true if the addressing mode represented 1918 /// by AM is legal for this target, for a load/store of the specified type. 1919 bool 1920 XCoreTargetLowering::isLegalAddressingMode(const AddrMode &AM, 1921 Type *Ty) const { 1922 if (Ty->getTypeID() == Type::VoidTyID) 1923 return AM.Scale == 0 && isImmUs(AM.BaseOffs) && isImmUs4(AM.BaseOffs); 1924 1925 const DataLayout *TD = TM.getDataLayout(); 1926 unsigned Size = TD->getTypeAllocSize(Ty); 1927 if (AM.BaseGV) { 1928 return Size >= 4 && !AM.HasBaseReg && AM.Scale == 0 && 1929 AM.BaseOffs%4 == 0; 1930 } 1931 1932 switch (Size) { 1933 case 1: 1934 // reg + imm 1935 if (AM.Scale == 0) { 1936 return isImmUs(AM.BaseOffs); 1937 } 1938 // reg + reg 1939 return AM.Scale == 1 && AM.BaseOffs == 0; 1940 case 2: 1941 case 3: 1942 // reg + imm 1943 if (AM.Scale == 0) { 1944 return isImmUs2(AM.BaseOffs); 1945 } 1946 // reg + reg<<1 1947 return AM.Scale == 2 && AM.BaseOffs == 0; 1948 default: 1949 // reg + imm 1950 if (AM.Scale == 0) { 1951 return isImmUs4(AM.BaseOffs); 1952 } 1953 // reg + reg<<2 1954 return AM.Scale == 4 && AM.BaseOffs == 0; 1955 } 1956 } 1957 1958 //===----------------------------------------------------------------------===// 1959 // XCore Inline Assembly Support 1960 //===----------------------------------------------------------------------===// 1961 1962 std::pair<unsigned, const TargetRegisterClass *> 1963 XCoreTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 1964 const std::string &Constraint, 1965 MVT VT) const { 1966 if (Constraint.size() == 1) { 1967 switch (Constraint[0]) { 1968 default : break; 1969 case 'r': 1970 return std::make_pair(0U, &XCore::GRRegsRegClass); 1971 } 1972 } 1973 // Use the default implementation in TargetLowering to convert the register 1974 // constraint into a member of a register class. 1975 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); 1976 } 1977