/external/llvm/lib/CodeGen/ |
ScheduleDAG.cpp | 71 if (!Required && I->getSUnit() == D.getSUnit()) 76 SUnit *PredSU = I->getSUnit(); 95 SUnit *N = D.getSUnit(); 141 SUnit *N = D.getSUnit(); 187 SUnit *SuccSU = I->getSUnit(); 203 SUnit *PredSU = I->getSUnit(); 244 SUnit *PredSU = I->getSUnit(); 277 SUnit *SuccSU = I->getSUnit(); 303 unsigned MaxDepth = BestI->getSUnit()->getDepth() [all...] |
LatencyPriorityQueue.cpp | 60 SUnit &Pred = *I->getSUnit(); 79 if (getSingleUnscheduledPred(I->getSUnit()) == SU) 95 AdjustPriorityOfUnscheduledPreds(I->getSUnit());
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ScheduleDAGInstrs.cpp | 438 SUnit *DefSU = getSUnit(Def); 623 iterateChainSucc(AA, MFI, DL, SUa, I->getSUnit(), ExitSU, Depth, Visited); 656 iterateChainSucc(AA, MFI, DL, SU, J->getSUnit(), ExitSU, &Depth, [all...] |
AggressiveAntiDepBreaker.cpp | 274 const SUnit *PredSU = P->getSUnit(); 287 return (Next) ? Next->getSUnit() : nullptr; 823 SUnit *NextSU = Edge->getSUnit(); 867 if (P->getSUnit() == NextSU ? 876 if ((P->getSUnit() == NextSU) && (P->getKind() != SDep::Anti) && 881 } else if ((P->getSUnit() != NextSU) && [all...] |
MachineScheduler.cpp | 526 if (Topo.IsReachable(PredDep.getSUnit(), SuccSU)) 528 Topo.AddPred(SuccSU, PredDep.getSUnit()); 540 SUnit *SuccSU = SuccEdge->getSUnit(); 579 SUnit *PredSU = PredEdge->getSUnit(); 827 if (SUnit *SU = getSUnit(&(*MI))) [all...] |
CriticalAntiDepBreaker.cpp | 136 const SUnit *PredSU = P->getSUnit(); 541 const SUnit *NextSU = Edge->getSUnit(); 565 if (P->getSUnit() == NextSU ?
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PostRASchedulerList.cpp | 436 SUnit *SuccSU = SuccEdge->getSUnit();
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/external/llvm/include/llvm/CodeGen/ |
ScheduleDAGInstrs.h | 187 /// getSUnit - Return an existing SUnit for this MI, or NULL. 188 SUnit *getSUnit(MachineInstr *MI) const; 270 /// getSUnit - Return an existing SUnit for this MI, or NULL. 271 inline SUnit *ScheduleDAGInstrs::getSUnit(MachineInstr *MI) const {
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ScheduleDAG.h | 159 //// getSUnit - Return the SUnit to which this edge points. 160 SUnit *getSUnit() const { 460 if (Preds[i].getSUnit() == N) 468 if (Succs[i].getSUnit() == N) 632 return Node->Preds[Operand].getSUnit();
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/external/llvm/lib/CodeGen/SelectionDAG/ |
ResourcePriorityQueue.cpp | 77 SUnit *PredSU = I->getSUnit(); 115 SUnit *SuccSU = I->getSUnit(); 219 SUnit &Pred = *I->getSUnit(); 237 if (getSingleUnscheduledPred(I->getSUnit()) == SU) 281 if (I->getSUnit() == SU) 511 if (I->isCtrl() || (I->getSUnit()->NumRegDefsLeft == 0)) 513 --I->getSUnit()->NumRegDefsLeft; 527 adjustPriorityOfUnscheduledPreds(I->getSUnit());
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ScheduleDAGFast.cpp | 141 SUnit *PredSU = PredEdge->getSUnit(); 173 LiveRegDefs[I->getReg()] = I->getSUnit(); 197 if (LiveRegCycles[I->getReg()] == I->getSUnit()->getHeight()) { 290 else if (I->getSUnit()->getNode() && 291 I->getSUnit()->getNode()->isOperandOf(LoadNode)) 304 if (ChainPred.getSUnit()) { 323 SUnit *SuccDep = D.getSUnit(); 331 SUnit *SuccDep = D.getSUnit(); 370 SUnit *SuccSU = I->getSUnit(); 407 SUnit *SuccSU = I->getSUnit(); [all...] |
ScheduleDAGRRList.cpp | 200 Topo.AddPred(SU, D.getSUnit()); 208 Topo.RemovePred(SU, D.getSUnit()); 366 SUnit *PredSU = PredEdge->getSUnit(); 536 assert((!RegDef || RegDef == SU || RegDef == I->getSUnit()) && 538 LiveRegDefs[I->getReg()] = I->getSUnit(); 792 SUnit *PredSU = PredEdge->getSUnit(); 814 assert(LiveRegDefs[I->getReg()] == I->getSUnit() && 860 I->getSUnit()->getHeight() < LiveRegGens[I->getReg()]->getHeight()) 861 LiveRegGens[I->getReg()] = I->getSUnit(); [all...] |
ScheduleDAGVLIW.cpp | 117 SUnit *SuccSU = D.getSUnit();
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ScheduleDAGSDNodes.cpp | 765 if (I->getSUnit()->CopyDstRC) { 767 DenseMap<SUnit*, unsigned>::iterator VRI = VRBaseMap.find(I->getSUnit()); [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCHazardRecognizers.cpp | 41 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit()); 49 if (SU->Preds[i].getSUnit() == CurGroup[j]) 67 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit()); 75 if (SU->Preds[i].getSUnit() == CurGroup[j])
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/external/llvm/lib/Target/Hexagon/ |
HexagonMachineScheduler.cpp | 75 if (I->getSUnit() == SU) 230 unsigned PredReadyCycle = I->getSUnit()->TopReadyCycle; 249 unsigned SuccReadyCycle = I->getSUnit()->BotReadyCycle; 431 SUnit &Pred = *I->getSUnit(); 449 SUnit &Succ = *I->getSUnit(); 510 if (getSingleUnscheduledPred(I->getSUnit()) == SU) 516 if (getSingleUnscheduledSucc(I->getSUnit()) == SU)
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HexagonVLIWPacketizer.cpp | 818 if ((PacketSU->Succs[i].getSUnit() == PacketSUDep) && [all...] |
/external/llvm/lib/Target/R600/ |
R600Packetizer.cpp | 202 if (Dep.getSUnit() != SUI)
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