| /external/clang/test/CodeGenCXX/ |
| debug-info-byval.cpp | 5 class DAG {
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCHazardRecognizers.h | 27 const ScheduleDAG *DAG;
37 ScoreboardHazardRecognizer(ItinData, DAG_), DAG(DAG_),
57 const ScheduleDAG &DAG;
78 PPCHazardRecognizer970(const ScheduleDAG &DAG);
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGSDNodes.h | 34 /// the DAG and must be handled explicitly by schedulers.
39 SelectionDAG *DAG; // DAG of the current basic block
51 void Run(SelectionDAG *dag, MachineBasicBlock *bb);
83 /// BuildSchedGraph - Build the SUnit graph from the selection dag that we
|
| LegalizeTypes.h | 1 //===-- LegalizeTypes.h - DAG Type Legalizer class definition ---*- C++ -*-===//
36 SelectionDAG &DAG;
67 return TLI.getTypeAction(*DAG.getContext(), VT);
72 return TLI.getTypeAction(*DAG.getContext(), VT) == TargetLowering::TypeLegal;
85 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
90 return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
141 explicit DAGTypeLegalizer(SelectionDAG &dag)
142 : TLI(dag.getTargetLoweringInfo()), DAG(dag)
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| LegalizeDAG.cpp | 61 SelectionDAG &DAG;
71 return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
77 SelectionDAGLegalize(SelectionDAG &DAG,
80 : TM(DAG.getTarget()), TLI(DAG.getTargetLoweringInfo()), DAG(DAG),
172 DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
173 dbgs() << " with: "; New->dump(&DAG));
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| LegalizeVectorOps.cpp | 36 SelectionDAG& DAG;
128 /// \brief Begin legalizer the vector operations in the DAG.
130 VectorLegalizer(SelectionDAG& dag) :
131 DAG(dag), TLI(dag.getTargetLoweringInfo()), Changed(false) {}
137 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
138 E = std::prev(DAG.allnodes_end()); I != std::next(E); ++I) {
160 DAG.AssignTopologicalOrder();
161 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin()
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| SelectionDAGBuilder.h | 1 //===-- SelectionDAGBuilder.h - Selection-DAG building --------*- C++ -*---===//
415 /// implying one could not create a DAG Combine to move the callinst.
574 SelectionDAG &DAG;
608 /// no subsequent DAG nodes should be created.
614 SelectionDAGBuilder(SelectionDAG &dag, FunctionLoweringInfo &funcinfo,
616 : CurInst(nullptr), SDNodeOrder(LowestSDNodeOrder), TM(dag.getTarget()),
617 DAG(dag), FuncInfo(funcinfo),
640 /// getRoot - Return the current virtual root of the Selection DAG,
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| /external/llvm/include/llvm/CodeGen/ |
| ScoreboardHazardRecognizer.h | 95 const ScheduleDAG *DAG;
108 const ScheduleDAG *DAG,
|
| SelectionDAG.h | 1 //===-- llvm/CodeGen/SelectionDAG.h - InstSelection DAG ---------*- C++ -*-===//
166 void checkForCycles(const SelectionDAG *DAG, bool force = false);
169 /// Data Dependence DAG representation suitable for instruction selection.
170 /// This DAG is constructed as the first step of instruction selection in order
190 /// The root of the entire DAG.
193 /// A linked list of nodes in the current DAG.
222 /// the DAG can optionally implement this interface. This allows the clients
225 /// A DAGUpdateListener automatically registers itself with DAG when it is
229 SelectionDAG &DAG;
232 : Next(D.UpdateListeners), DAG(D)
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| MachineScheduler.h | 18 // scheduled. Targets can override the DAG builder and scheduler without
26 // The default scheduler, ScheduleDAGMILive, builds the DAG and drives list
28 // intervals. Most targets don't need to override the DAG builder and list
38 // The DAG builder can also be customized in a sense by adding DAG mutations
39 // that will run after DAG building and before list scheduling. DAG mutations
45 // ScheduleDAGMI *DAG = new ScheduleDAGMI(C, CustomStrategy(C));
46 // DAG->addMutation(new CustomDependencies(DAG->TII, DAG->TRI))
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| /external/llvm/lib/Target/AMDGPU/ |
| R600MachineScheduler.h | 29 const ScheduleDAGMILive *DAG;
71 DAG(nullptr), TII(nullptr), TRI(nullptr), MRI(nullptr) {
76 void initialize(ScheduleDAGMI *dag) override;
|
| R600ISelLowering.cpp | 1 //===-- R600ISelLowering.cpp - R600 DAG Lowering Implementation -----------===//
11 /// \brief Custom DAG lowering for R600
584 // Custom DAG Lowering Operations
587 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
588 MachineFunction &MF = DAG.getMachineFunction();
591 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
592 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
593 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
594 case ISD::SHL_PARTS: return LowerSHLParts(Op, DAG);
596 case ISD::SRL_PARTS: return LowerSRXParts(Op, DAG);
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| SIISelLowering.cpp | 1 //===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===//
11 /// \brief Custom DAG lowering for SI
537 SDValue SITargetLowering::LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
540 const DataLayout &DL = DAG.getDataLayout();
541 MachineFunction &MF = DAG.getMachineFunction();
546 Type *Ty = VT.getTypeForEVT(*DAG.getContext());
548 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
551 SDValue BasePtr = DAG.getCopyFromReg(Chain, SL,
553 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
554 DAG.getConstant(Offset, SL, PtrVT))
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| /external/llvm/lib/Target/Hexagon/ |
| HexagonMachineScheduler.h | 103 /// Perform platform-specific DAG postprocessing.
134 VLIWMachineScheduler *DAG;
156 DAG(nullptr), SchedModel(nullptr), Available(ID, Name+".A"),
167 void init(VLIWMachineScheduler *dag, const TargetSchedModel *smodel) {
168 DAG = dag;
191 VLIWMachineScheduler *DAG;
207 : DAG(nullptr), SchedModel(nullptr), Top(TopQID, "TopQ"),
210 void initialize(ScheduleDAGMI *dag) override;
|
| HexagonISelDAGToDAG.cpp | 1 //===-- HexagonISelDAGToDAG.cpp - A dag to dag inst selector for Hexagon --===//
84 return "Hexagon DAG->DAG Pattern Instruction Selection";
187 /// createHexagonISelDag - This pass converts a legalized DAG into a
188 /// Hexagon-specific DAG, ready for instruction scheduling.
198 const char *Name = "Hexagon DAG->DAG Pattern Instruction Selection";
758 // If there is an zero_extend followed an intrinsic in DAG (this means - the
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIISelLowering.cpp | 1 //===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===//
10 // Most of the DAG lowering is handled in AMDGPUISelLowering.cpp. This file is
258 // Custom DAG Lowering Operations
261 SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
264 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
265 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
266 case ISD::LOAD: return LowerLOAD(Op, DAG);
267 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
268 case ISD::AND: return Loweri1ContextSwitch(Op, DAG, ISD::AND);
275 return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass
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| /external/llvm/lib/Target/BPF/ |
| BPFISelLowering.cpp | 1 //===-- BPFISelLowering.cpp - BPF DAG Lowering Implementation ------------===//
11 // selection DAG.
172 SDValue BPFTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
175 return LowerBR_CC(Op, DAG);
177 return LowerGlobalAddress(Op, DAG);
179 return LowerSELECT_CC(Op, DAG);
190 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
200 MachineFunction &MF = DAG.getMachineFunction();
205 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
221 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT)
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| /external/llvm/lib/Target/Mips/ |
| Mips16ISelLowering.cpp | 1 //===-- Mips16ISelLowering.h - Mips16 DAG Lowering Interface ----*- C++ -*-===//
428 SelectionDAG &DAG = CLI.DAG;
429 MachineFunction &MF = DAG.getMachineFunction();
505 JumpTarget = DAG.getExternalSymbol(Mips16HelperFunction,
506 getPointerTy(DAG.getDataLayout()));
508 JumpTarget = getAddrGlobal(S, CLI.DL, JumpTarget.getValueType(), DAG,
|
| MipsSEISelLowering.cpp | 1 //===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===//
361 SelectionDAG &DAG) const {
363 case ISD::LOAD: return lowerLOAD(Op, DAG);
364 case ISD::STORE: return lowerSTORE(Op, DAG);
365 case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
366 case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
367 case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
368 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
369 case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
370 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
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| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyISelLowering.cpp | 1 //=- WebAssemblyISelLowering.cpp - WebAssembly DAG Lowering Implementation -==//
296 static void fail(SDLoc DL, SelectionDAG &DAG, const char *msg) {
297 MachineFunction &MF = DAG.getMachineFunction();
298 DAG.getContext()->diagnose(
318 SelectionDAG &DAG = CLI.DAG;
322 MachineFunction &MF = DAG.getMachineFunction();
326 fail(DL, DAG,
330 fail(DL, DAG, "WebAssembly doesn't support patch point yet");
337 fail(DL, DAG, "WebAssembly doesn't support tail call yet")
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| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 1 //===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation ------===//
184 SelectionDAG &DAG) const {
188 case ISD::SRA: return LowerShifts(Op, DAG);
189 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
190 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
191 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
192 case ISD::SETCC: return LowerSETCC(Op, DAG);
193 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
194 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
195 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG);
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| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 10 // selection DAG.
276 // We have some custom DAG combine patterns for these nodes
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 1 //===-- SystemZISelLowering.cpp - SystemZ DAG lowering implementation -----===//
723 SelectionDAG &DAG) const {
730 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
737 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
744 Ops.push_back(DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
751 Ops.push_back(DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
758 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
763 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
802 static SDValue convertLocVTToValVT(SelectionDAG &DAG, SDLoc DL,
808 Value = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Value
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| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | 1 //===-- AArch64ISelDAGToDAG.cpp - A dag to dag inst selector for AArch64 --===//
544 /// being extended to be a GPR32, but the incoming DAG might be acting on a
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| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 1 //===-- XCoreISelLowering.cpp - XCore DAG Lowering Implementation ---------===//
175 // We have target-specific dag combine patterns for the following nodes:
204 LowerOperation(SDValue Op, SelectionDAG &DAG) const {
207 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
208 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
209 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
210 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
211 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
212 case ISD::LOAD: return LowerLOAD(Op, DAG);
213 case ISD::STORE: return LowerSTORE(Op, DAG);
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